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    ABSTRACT: Introduction Recently, demands for the high-density non-volatile memory products are exploding, but the most difficult problems are still under the surface at the same time. For the breakthrough of scaling limit, simple structure memories are developed and also multi-bit operation memories are introduced concurrently. Multi-bit memories based on localized charge trapping in nitride [1] have received much interest for their simple structure (i.e. no floating gate) and high-density application. But, due lo some critical issues such as charge redistribution during the program [2] and charge diffusion [3] in silicon-nitride after injection, it would be difficult to obtain 2-bit characteristics in sub 100-nm regime. We present a new scalable 2-bit SONOS memory. Since the charge spreading during and after charge injection is confined within nitride, it is possible to manipulate charge distribution through the nano-patteming of the local nitride under a single gate. Damascene gate process with inverted sidewall patterning (ISP) produced two localized 30-nm x 9- nm (W=100-nm) nitride boxes under a 90-nm gate without lithography-limit, misalignment, and net memory size increase. The new cell structure has shown not only perfect 2-bit program and erase characteristics but also excellent endurance and retention compared with the conventional single ONO type SONOS in the sub-90-nm regime.
    Full-text · Article · Jan 2003
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    ABSTRACT: For the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and a low impurity concentration in the rest of the channel. Besides having excellent DC output characteristics, better V<sub>th</sub>-L roll-off control, lower DIBL, higher breakdown voltages and kink free operation, these devices show higher AC transconductance, higher output resistance and better dynamic intrinsic gain (g<sub>m</sub>R<sub>0</sub>). Experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance, in comparison with the conventional (CON) homogeneously doped SOI MOSFETs. From 2D device simulations, the lower hot carrier degradation mechanism in SH-SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.
    Full-text · Conference Paper · Nov 2003
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