## No full-text available

To read the full-text of this research,

you can request a copy directly from the authors.

Flash, already one of the dominant forms of data storage for mobile consumer devices, such as smartphones and media players, is experiencing explosive growth in cloud and enterprise applications. Flash devices offer very high access speeds, low power consumption, and physical resiliency. Our goal in this article is to provide a high-level overview of error correction for Flash. We will begin by discussing Flash functionality and design. We will introduce the nature of Flash deficiencies. Afterwards, we describe the basics of ECCs. We discuss BCH and LDPC codes in particular and wrap up the article with more directions for Flash coding.

To read the full-text of this research,

you can request a copy directly from the authors.

... As for the long term, charge leakage may be one of critical issues of multi-level cell memories. As documented in [8][9][10][11][12][13], voltage of a cell decreases and some cells even become defective over time. The amount of charge leakage, which can be modeled as gain and/or offset mismatch, depends on various physical parameters, such as the device 1. INTRODUCTION temperature, the magnitude of the charge, and the time elapsed between writing and reading data [11]. ...

... As documented in [8][9][10][11][12][13], voltage of a cell decreases and some cells even become defective over time. The amount of charge leakage, which can be modeled as gain and/or offset mismatch, depends on various physical parameters, such as the device 1. INTRODUCTION temperature, the magnitude of the charge, and the time elapsed between writing and reading data [11]. Importantly, the charge leakage leads to a severe shift in the voltage distribution over time. ...

... There are many examples of channels with offset and gain mismatch. Reading errors in Flash memories may originate from cell drift in aging devices [11]. In the digital optical recording, fingerprints and scratches on the surface of discs result in offset variations of the retrieved signal [65]. ...

... These suggested code's primary purpose is to shape the user data to strengthen it to be less prone to errors and better support for the synchronization. For the ECC codes, an overview of error correction for Flash was summarized in [13]. A typical 4/6 error-correction constrained code to mitigate the effect of intertrack-interference for bit-patterned recording systems was also presented in [14]. ...

... As a result, the more the number of 0 → 1 switchings, the higher BER is. Constrained (modulation) codes have been used in commercial data storage systems for a long time [13]. These codes have an essential role in preventing interference and supporting system synchronization. ...

A design of 7/9-rate sparse code for spin-torque transfer magnetic random access memory (STT-MRAM) is proposed in this work. The STT-MRAM using spin-polarized current through magnetic tunnel junction (MTJ) to write data is one of the most promising candidates for the next-generation nonvolatile memory technologies in consumer and data center applications. The proposed code is designed to exploit the asymmetric write failure feature of the STT-MRAM. In particular, 7-bit user-data sequences incoming the encoder is encoded into 9-bit codewords, where the Hamming weights of the codewords are equal to 2 and 4 only. A single look-up table accomplishes encoding, whereas the maximum likelihood decoding is deployed in this work. Simulation results demonstrate that the designed code can provide significant improvements for the reliability of STT-MRAM under the effect of both write and read errors.

... Note that the output bit is generated with a finite bit error rate (BER) due to the non-zero probability that device mismatch or readout errors cause overlap between the stored states, as shown in Fig. 3(b). Error control coding (ECC) bits can be added to the stored data to detect and correct these errors, analogous to that used in other commercial memory technologies such as optical discs [40] and NOR/NAND flash [41]; methods for implementing ECC are discussed later. ...

The paper describes a device-level encryption approach for implementing intrinsically secure non-volatile memory (NVM) using resistive RAM (ReRAM). Data are encoded in the ReRAM filament morphology, making it robust to both electrical and optical probing methods. The encoded resistance states are randomized to maximize the entropy of the ReRAM resistance distribution, thus providing robustness to reverse engineering (RE) attacks. Simulations of data encryption and decryption using experimental data from Ru(BE)/ALD-HfO2 (MO)/Zr/W(TE) ReRAM devices reveals an uncorrected bit error rate (BER) < 0.02 and a maximum key entropy of ≈17.3 bits per device. A compensation procedure is also developed for maintaining BER in the presence of temperature changes.

... Constrained codes can also be exploited to guide deep learning-based detection of resistive random access memory [6]. Two-dimensional, chess boardlike, constraints are important for avoiding 'sneaky' paths in non-volatile memories, such as memristors [7,8,9,10]. ...

Constrained coding is a somewhat nebulous term which we may define by either inclusion or exclusion. A constrained system is defined by a constrained set of 'good' or 'allowable' sequences to be recorded or transmitted. Constrained coding focuses on the analysis of constrained systems and the design of efficient encoders and decoders that transform arbitrary user sequences into constrained sequences. Constrained coding has extensively been used since the advent in the 1950s of digital storage and communication devices. They have found application in all hard disk, non-volatile memories, optical discs, such as CD, DVD and Blu-Ray Disc, and they are now projected for usage in DNA-based storage. We survey theory and practice of constrained coding, tracing the evolution of the subject from its origins in Shannon's classic 1948 paper to present-day applications in DNA-based data storage systems.

... Based on [1] and [2], gain and/or offset mismatch often occur on modern storages and communication channels. In non-volatile memories, for instance: a flash memory, the data is stored in a floating gate. ...

The phenomena of unknown gain or offset on communication systems and modern storages such as optical data storage and non-volatile memory (flash) becomes a serious problem. This problem can be handled by Pearson distance applied to the detector because it offers immunity to gain and offset mismatch. This distance can only be used for a specific set of codewords, called Pearson codes. An interesting example of Pearson code can be found in T-constrained code class. In this paper, we present binary 2-constrained codes with cyclic property. The construction of this code is adopted from cyclic codes, but it cannot be considered as cyclic codes.

... While noise may vary from symbol to symbol, it is often assumed that the offset is constant within a block of symbols. For example, charge leakage from memory cells may cause such an offset of the stored signal values [12]. While Euclidean distance based decoders are known to be optimal if the transmitted or stored signal is only disturbed by Gaussian noise, they may perform badly if there is offset as well. ...

Decoders minimizing the Euclidean distance between the received word and the candidate codewords are known to be optimal for channels suffering from Gaussian noise. However, when the stored or transmitted signals are also corrupted by an unknown offset, other decoders may perform better. In particular, applying the Euclidean distance on normalized words makes the decoding result independent of the offset. The use of this distance measure calls for alternative code design criteria in order to get good performance in the presence of both noise and offset. In this context, various adapted versions of classical binary block codes are proposed, such as (i) cosets of linear codes, (ii) (unions of) constant weight codes, and (iii) unordered codes. It is shown that considerable performance improvements can be achieved, particularly when the offset is large compared to the noise.

... These techniques incorporate redundant resources (e.g., spare columns and spare blocks, etc.) to replace the detected faulty cells. Besides these spare-based techniques, error-correction code (ECC) is also considered as the most popular and cost-effective method [4,11,15,21,22,25,27] for repairing flash memories by incorporating check bits for locating and correcting faulty bits. Two popularly used ECC techniques include the Bose-Chaudhuri-Hocquenghem (BCH) code [14] and the Hamming code [7]. ...

Novel fault leveling techniques based on address remapping (AR) are proposed in this paper. We can change the logical-to-physical address mapping of the page buffer such that faulty cells within a flash page can be evenly distributed into different codewords. Therefore, the adopted ECC scheme can correct them effectively. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the heuristic fault leveling analysis (FLA) algorithm and evaluating control words used to steer fault leveling. A new page buffer architecture suitable for address remapping is also proposed. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.

... In general, we can say that dealing with varying offset and/or gain is an important issue in signal processing for modern storage and communication systems. For example, methods to solve these difficulties in flash memories have been discussed in, e.g., [3], [4], and [5]. Also, in optical disc media, the retrieved signal depends on the dimensions of the written features and upon the quality of the light path, which may be obscured by fingerprints or scratches on the substrate, leading to offset and gain variations of the retrieved signal. ...

Besides the omnipresent noise, other important inconveniences in communication and storage systems are formed by gain and/or offset mismatches. In the prior art, a maximum likelihood (ML) decision criterion has already been developed for Gaussian noise channels suffering from unknown gain and offset mismatches. Here, such criteria are considered for Gaussian noise channels suffering from either an unknown offset or an unknown gain. Furthermore, ML decision criteria are derived when assuming a Gaussian or uniform distribution for the offset in the absence of gain mismatch.

... Dealing with rapidly varying offset and/or gain is an important issue in signal processing for modern storage and communication systems. For example, methods to solve these difficulties in Flash memories have been discussed in, e.g., [7], [9], and [11]. Also, in optical disc media, the retrieved signal depends on the dimensions of the written features and upon the quality of the light path, which may be obscured by fingerprints or scratches on the substrate, leading to offset and gain variations of the retrieved signal. ...

The recently proposed Pearson codes offer immunity against channel gain and offset mismatch. These codes have very low redundancy, but efficient coding procedures were lacking. In this paper, systematic Pearson coding schemes are presented. The redundancy of these schemes is analyzed for memoryless uniform sources. It is concluded that simple coding can be established at only a modest rate loss.

... Many other advanced codes suitable for memory exist in the research literature. Several works have explored source coding and channel coding for fault models other than the BSC by focusing on emerging non-volatile random-access memories (NVMs) [15], [16], [17], [18] and storage-class flash memory [19], [20], [21], [22], [23]. ECCs that are suitable to approximate computing, e.g., Variable-Strength ECC [24] have been proposed. ...

Conventional error-correcting codes (ECCs) and system-level fault-tolerance mechanisms are currently treated as separate abstraction layers. This can reduce the overall efficacy of error detection and correction (EDAC) capabilities, impacting the reliability of memories by causing crashes or silent data corruption. To address this shortcoming, we propose Software-Defined ECC (SWD-ECC), a new class of heuristic techniques to recover from detected but uncorrectable errors (DUEs) in memory. It uses available side information to estimate the original message by first filtering and then ranking the possible candidate codewords for a DUE. SWD-ECC does not incur any hardware or software overheads in the cases where DUEs do not occur.
As an exemplar for SWD-ECC, we show through offline analysis on SPEC CPU2006 benchmarks how to heuristically recover from 2-bit DUEs in MIPS instruction memory using a common (39,32) single-error-correcting, double-error-detecting (SECDED) code. We first apply coding theory to compute all of the candidate codewords for a given DUE. Second, we filter out the candidates that are not legal MIPS instructions, increasing the chance of successful recovery. Finally, we choose a valid candidate whose logical operation (e.g., add or load) occurs most frequently in the application binary image. Our results show that on average, 33% of all possible 2-bit DUEs in the evaluated set of instructions can be successfully recovered using this heuristic decoding strategy. We believe this is a significant achievement compared to an otherwise-guaranteed crash which can be undesirable in many systems and applications. Moreover, there is room for future improvement of this result with more sophisticated uses of side information. We look forward to future work in this area.

... The channel is motivated by the properties of flash memory. We give some basic details of this setting here; see [1,9] for more detailed introductions, and see (for example) [6,7,8] for another approach to modelling the problem using rank modulation codes. Flash memory is made up of an array of floating-gate transistors, known as flash cells. ...

K.A.S. Immink and J.H. Weber recently defined and studied a channel with both
gain and offset mismatch, modelling the behaviour of charge-leakage in flash
memory. They proposed a decoding measure for this channel based on minimising
Pearson distance (a notion from cluster analysis). The paper derives a formula
for maximum likelihood decoding for this channel, and also defines and
justifies a notion of minimum distance of a code in this context.

... As a result, the offset between different groups of cells may be very different so that prior art automatic offset or gain control, which estimates the mismatch from the previously received data, can not be applied. Methods to solve these difficulties in Flash memories have been discussed in, for example, [4]- [7]. In optical disc media, such as the popular Compact Disc, DVD, and Blu-ray disc, the retrieved signal depends on the dimensions of the written features and upon the quality of the light path, which may be obscured by fingerprints or scratches on the substrate. ...

The Pearson distance has been advocated for improving the error performance
of noisy channels with unknown gain and offset. The Pearson distance can only
fruitfully be used for sets of $q$-ary codewords, called Pearson codes, that
satisfy specific properties. We will analyze constructions and properties of
optimal Pearson codes. We will compare the redundancy of optimal Pearson codes
with the redundancy of prior art $T$-constrained codes, which consist of
$q$-ary sequences in which $T$ pre-determined reference symbols appear at least
once. In particular, it will be shown that for $q\le 3$ the $2$-constrained
codes are optimal Pearson codes, while for $q\ge 4$ these codes are not
optimal.

In many channels, the transmitted signals do not only face noise, but offset mismatch as well. In the prior art, maximum likelihood (ML) decision criteria have already been developed for noisy channels suffering from
signal independent offset
. In this paper, such ML criterion is considered for the case of binary signals suffering from Gaussian noise and
signal dependent offset
. The signal dependency of the offset signifies that it may differ for distinct signal levels, i.e., the offset experienced by the zeroes in a transmitted codeword is not necessarily the same as the offset for the ones. Besides the ML criterion itself, also an option to reduce the complexity is considered. Further, a brief performance analysis is provided, confirming the superiority of the newly developed ML decoder over classical decoders based on the Euclidean or Pearson distances.

Maximum likelihood (ML) decision criteria have been developed for channels suffering from signal independent offset mismatch. Here, such criteria are considered for signal dependent offset, which means that the value of the offset may differ for distinct signal levels rather than being the same for all levels. An ML decision criterion is derived, assuming uniform distributions for both the noise and the offset. In particular, for the proposed ML decoder, bounds are determined on the standard deviations of the noise and the offset which lead to a word error rate equal to zero. Simulation results are presented confirming the findings.

Multilevel flash memories enable multiple bits to be stored in a single memory cell and hence a significant increase of the storage capacity. The multiple bits that are used for labeling the threshold voltage level of a memory cell belong to different pages. A multilevel flash memory channel resembles a multi-user channel with asymmetric noise, while the data of different pages, which are encoded independently, resembles data of multiple users. In this paper, performance analyses are proposed for this channel by using the union bound technique. In particular, we investigated two different binary labeling schemes of a cell level, the Gray labeling and non-Gray labeling with three maximum-likelihood (ML) based decoding schemes, which are the joint multi-page ML decoding, page-separate ML decoding, and default setting ML decoding. Our analysis reveals an asymptotic diminishing rate of decoding errors as the channel noise approaches zero, based on which code design criteria are proposed. It is shown theoretically that Gray mapping has no joint (i.e. multi-page) decoding gain. The corresponding diminishing decoding error rate is dominated by the weakest code in each page and hence a separate decoding scheme is adequate. On the other hand, the non-Gray mapping has a joint decoding gain which means the weak code can exploit the decoding of the strong code and the diminishing rate of its decoding errors is not subject to the cask effect. Therefore, for Gray mapping, a symmetric coding scheme using equal-strength code for each page achieves better error performance, while for non-Gray mapping with joint decoding, the symmetric coding is not necessary. Moreover, by using the asymmetric coding scheme through assigning different code rates to different pages, non-Gray mapping can achieve higher overall sum rate than Gray mapping with a similar decoding error rate performance.

We extend the lifetime of Flash memory in embedded processors by exploiting the fact that data from sensors is inherently analog. Prior work in the computer architecture community has assumed that all data is digital and has overlooked the opportunities available when working with analog data, such as the data recorded by sensors. In this work, we introduce redundancy into the quantization of sensor data in order to provide several alternative representations. Notably, we trade off distortion-the difference between the sensed analog value and the digital quantization of that value-to improve lifetime. Our simulations show that when combining rate, distortion and lifetime tradeoffs we can extend Flash lifetime at a far smaller capacity cost compared to prior work. More specifically the simulated system shows that it is possible to achieve up to 2.75× less capacity cost compared to redundant Flash memory and 1.29× less capacity cost compared to the state of the art coding schemes.

The performance of certain transmission and storage channels, such as optical data storage and nonvolatile memory (flash), is seriously hampered by the phenomena of unknown offset (drift) or gain. We will show that minimum Pearson distance (MPD) detection, unlike conventional minimum Euclidean distance detection, is immune to offset and/or gain mismatch. MPD detection is used in conjunction with (T) -constrained codes that consist of (q) -ary codewords, where in each codeword (T) reference symbols appear at least once. We will analyze the redundancy of the new (q) -ary coding technique and compute the error performance of MPD detection in the presence of additive noise. Implementation issues of MPD detection will be discussed, and results of simulations will be given.

In this chapter, we discuss a number of codes for error control. Only block codes are treated here. Discussion on convolutional
codes will be deferred until next chapter. After reviewing some information theoretic foundations of coding in the first section,
linear block codes are treated in Section 3.2. The concepts of parity-check and generator matrices to represent linear block
codes are discussed. Several examples of block codes are given, including the important class of Hamming codes. Principles
behind syndrome decoding and decoding using a standard array are treated in Section 3.3. Section 3.4 provides some useful
bounds on coding and introduces the concept of coding gain. Section 3.5 discusses the principles behind cyclic codes. Some
important decoding techniques for these codes are treated in Section 3.6. These include the Meggitt and error-trapping decoders.
After introducing some algebra in Section 3.7, in the next three sections that follow, we treat the most important and practical
of all cyclic codes, the Bose-Chaudhuri-Hocquenghem (BCH) codes and Reed-Solomon codes. The treatment includes the MasseyBerlekamp algorithm for decoding these codes. In Section 3.11, we turn to coding
for burst error control, which has been successfully applied to storage media such as magnetic tapes and compact disc. Automatic-repeat-request (ARQ) schemes find wide applicability in computer networks and these schemes are treated in the last section.

In NAND Flash memory featuring multi-level cells (MLC), the width of threshold voltage distributions about their nominal values affects the permissible number of levels and thus storage capacity. Unfortunately, inter-cell coupling causes a cell's charge to affect its neighbors' sensed threshold voltage, resulting in an apparent broadening of these distributions. We present a novel approach, whereby the data written to Flash is constrained, e.g., by forbidding certain adjacent-cell level combinations, so as to limit the maximum voltage shift and thus narrow the distributions. To this end, we present a new family of constrained codes. Our technique can serve for capacity enhancement (more levels) or for improving endurance, retention and bit error rate (wider guard bands between adjacent levels). It may also be combined with various programming order techniques that mitigate the inter-cell coupling effects and with decoding techniques that compensate for them.

We explore a novel data representation scheme for multi-level flash memory cells, in which a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The only allowed charge-placement mechanism is a "push-to-the-top" operation which takes a single cell of the set and makes it the top-charged cell. The resulting scheme eliminates the need for discrete cell levels, as well as overshoot errors, when programming cells.
We present unrestricted Gray codes spanning all possible n-cell states and using only "push-to-the-top" operations, and also construct balanced Gray codes. We also investigate optimal rewriting schemes for translating arbitrary input alphabet into n-cell states which minimize the number of programming operations.

Memories whose storage cells transit irreversibly between states have been common since the start of the data storage technology. In recent years, flash memories and other non-volatile memories based on floating-gate cells have become a very important family of such memories. We model them by the Write Asymmetric Memory (WAM), a memory where each cell is in one of q states – state 0, 1, ... , q-1 – and can only transit from a lower state to a higher state. Data stored in a WAM can be rewritten by shifting the cells to higher states. Since the state transition is irreversible, the number of times of rewriting is limited. When multiple variables are stored in a WAM, we study codes, which we call floating codes, that maximize the total number of times the variables can be written and rewritten.
In this paper, we present several families of floating codes
that either are optimal, or approach optimality as the codes get longer. We also present bounds to the performance of general floating codes. The results show that floating codes can integrate the rewriting capabilities of different variables to a surprisingly high degree.

Predetermined fixed thresholds are commonly used in nonvolatile memories for reading binary sequences, but they usually result in significant asymmetric errors after a long duration, due to voltage or resistance drift. This motivates us to construct error-correcting schemes with dynamic reading thresholds, so that the asymmetric component of errors are minimized. In this paper, we discuss how to select dynamic reading thresholds without knowing cell level distributions, and present several error-correcting schemes. Analysis based on Gaussian noise models reveals that bit error probabilities can be significantly reduced by using dynamic thresholds instead of fixed thresholds, hence leading to a higher information rate.

Several physical effects that limit the reliability and
performance of Multilevel Flash Memories induce errors that
have low magnitudes and are dominantly asymmetric. This paper studies block codes for asymmetric limited-magnitude errors over q-ary channels. We propose code constructions and bounds for such channels when the number of errors is bounded by t and the error magnitudes are bounded by ࡁ. The constructions utilize known codes for symmetric errors, over small alphabets, to protect large-alphabet symbols from asymmetric limited-magnitude errors. The encoding and decoding of these codes are performed over the small alphabet whose size depends only on the maximum error magnitude and is independent of the alphabet size of the outer code. Moreover, the size of the codes is shown
to exceed the sizes of known codes (for related error models), and asymptotic rate-optimality results are proved. Extensions of the construction are proposed to accommodate variations on the error model and to include systematic codes as a benefit to practical implementation.

Constrained codes are a key component in digital recording devices
that have become ubiquitous in computer data storage and electronic
entertainment applications. This paper surveys the theory and practice
of constrained coding, tracing the evolution of the subject from its
origins in Shannon's classic 1948 paper to present-day applications in
high-density digital recorders. Open problems and future research
directions are also addressed

This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Constrained codes are a kev component in the digital recording devices that have become ubiquitous in computer data storage and electronic entertainment applications. This paper surveys the theory and practice of constrained coding, tracing the evolution of the subject from its origins in Shannon's classic 1948 paper to present-day applications in high-density digital recorders. Open problems and future research directions are also addressed.

Storage media such as digital optical disks, PROMS, or paper tape consist of a number of ”write-once” bit positions (wits); each wit initially contains a ”0” that may later be irreversibly overwritten with a ”1”. It is demonstrated that such ”write-once memories” (woms) can be ”rewritten” to a surprising degree. For example, only 3 wits suffice to represent any 2-bit value in a way that can later be updated to represent any other 2- bit value. For large k, 1·29····k wits suffice to represent a k- bit value in a way that can be similarly updated. Most surprising, allowing t writes of a k-bit value requires only t+o(t) wits, for any fixed k. For fixed t, approximately k·t/log(t) wits are required as k→∞. An n-wit WOM is shown to have a ”capacity” (i.e., k·t whenn writing a k-bit value t times) of up to n·log(n) bits.

In this work, the model introduced by Gabrys is extended to account for the presence of unreliable memory cells. Leveraging data analysis on errors taking place in a TLC Flash device, we show that memory cells can be broadly categorized into reliable and unreliable cells, where the latter are much more likely to be in error. Our approach programs unreliable cells only in a limited capacity. In particular, we suggest a coding scheme, using generalized tensor product codes, that programs the unreliable cells only at certain voltage levels that are less likely to result in errors. We present simulation results illustrating an improvement of up to a half order of magnitude in page error rates compared to existing codes.

This paper provides a comprehensive analysis of nonbinary low-density parity check (LDPC) codes built out of protographs. We consider both random and constrained edge-weight labeling, and refer to the former as the unconstrained nonbinary protograph-based LDPC codes (U-NBPB codes) and to the latter as the constrained nonbinary protograph-based LDPC codes (C-NBPB codes). Equipped with combinatorial definitions extended to the nonbinary domain, ensemble enumerators of codewords, trapping sets, stopping sets, and pseudocodewords are calculated. The exact enumerators are presented in the finite-length regime, and the corresponding growth rates are calculated in the asymptotic regime. An EXIT chart tool for computing the iterative decoding thresholds of protograph-based LDPC codes is presented, followed by several examples of finite-length U-NBPB and C-NBPB codes with high performance. Throughout this paper, we provide accompanying examples, which demonstrate the advantage of nonbinary protograph-based LDPC codes over their binary counterparts and over random constructions. The results presented in this paper advance the analytical toolbox of nonbinary graph-based codes.

In non-volatile memories, reading stored data is typically done through the use of predetermined fixed thresholds. However, due to problems commonly affecting such memories, including voltage drift, overwriting, and inter-cell coupling, fixed threshold usage often results in significant asymmetric errors. To combat these problems, Zhou, Jiang, and Bruck recently introduced the notion of dynamic thresholds and applied them to the reading of binary sequences. In this paper, we explore the use of dynamic thresholds for multi-level cell (MLC) memories. We provide a general scheme to compute and apply dynamic thresholds and derive performance bounds. We show that the proposed scheme compares favorably with the optimal thresholding scheme. Finally, we develop limited-magnitude error-correcting codes tailored to take advantage of dynamic thresholds.

Flash memory is a promising new storage technology. Supported by empirical data collected from a Flash memory device, we propose a class of codes that exploits the asymmetric nature of the error patterns in a Flash device using tensor product operations. We call these codes graded bit-error-correcting codes. As demonstrated on the data collected from a Flash chip, these codes significantly delay the onset of errors and therefore have the potential to prolong the lifetime of the memory device.

In recent years, flash-based SSDs have grown enormously both in capacity and popularity. In highperformance enterprise storage applications, accelerating adoption of SSDs is predicated on the ability of manufacturers to deliver performance that far exceeds disks while closing the gap in cost per gigabyte. However, while flash density continues to improve, other metrics such as a reliability, endurance, and performance are all declining. As a result, building larger-capacity flashbased SSDs that are reliable enough to be useful in enterprise settings and high-performance enough to justify their cost will become challenging. In this work, we present our empirical data collected from 45 flash chips from 6 manufacturers and examine the performance trends for these raw flash devices as flash scales down in feature size. We use this analysis to predict the performance and cost characteristics of future SSDs. We show that future gains in density will come at significant drops in performance and reliability. As a result, SSD manufacturers and users will face a tough choice in trading off between cost, performance, capacity and reliability.

Codes for rank modulation have been recently proposed as a means of protecting flash memory devices from errors. We study basic coding theoretic problems for such codes, representing them as subsets of the set of permutations of n elements equipped with the Kendall tau distance. We derive several lower and upper bounds on the size of codes. These bounds enable us to establish the exact scaling of the size of optimal codes for large values of n. We also show the existence of codes whose size is within a constant factor of the sphere packing bound for any fixed number of errors.

Binary low density parity check (LDPC) codes have been shown to have near Shannon limit performance when decoded using a probabilistic decoding algorithm. The analogous codes defined over finite fields GF(q) of order q>2 show significantly improved performance. We present the results of Monte Carlo simulations of the decoding of infinite LDPC codes which can be used to obtain good constructions for finite codes. We also present empirical results for the Gaussian channel including a rate 1/4 code with bit error probability of 10<sup>-4</sup> at E<sub>b </sub>/N<sub>0</sub>=-0.05 dB

A low-density parity-check code is a code specified by a parity-check matrix with the following properties: each column contains a small fixed number j geq 3 of l's and each row contains a small fixed number k > j of l's. The typical minimum distance of these codes increases linearly with block length for a fixed rate and fixed j . When used with maximum likelihood decoding on a sufficiently quiet binary-input symmetric channel, the typical probability of decoding error decreases exponentially with block length for a fixed rate and fixed j . A simple but nonoptimum decoding scheme operating directly from the channel a posteriori probabilities is described. Both the equipment complexity and the data-handling capacity in bits per second of this decoder increase approximately linearly with block length. For j > 3 and a sufficiently low rate, the probability of error using this decoder on a binary symmetric channel is shown to decrease at least exponentially with a root of the block length. Some experimental results show that the actual probability of decoding error is much smaller than this theoretical bound.

A class of codes is described having check matrices which are the tensor product of the check matrices of known nonbinary codes and binary codes. The error-correction, error-detection, and error-location capabilities of these codes are specified in terms of the properties of the component codes. The construction procedure allows for a class of codes with a wide variety of redundancies and error-control capabilities. Examples are given of codes from this class which correct random bursts of errors and bursts of bursts of errors.

Binary Low Density Parity Check (LDPC) codes have been shown to have near Shannon limit performance when decoded using a probabilistic decoding algorithm. The analogous codes defined over finite fields GF (q) of order q ? 2 show significantly improved performance. We present the results of Monte Carlo simulations of the decoding of infinite LDPC Codes which can be used to obtain good constructions for finite Codes. Our empirical results for the Gaussian channel include a rate 1/4 code with bit error probability of 10 Gamma4 at E b =N 0 = Gamma0:05dB. 1 Introduction We consider a class of error correcting codes first described by Gallager in 1962 [1]. These recently rediscovered low density parity check (LDPC) codes are defined in terms of a sparse parity check matrix and are known to be asymptotically good for all channels with symmetric stationary ergodic noise [2, 3]. Practical decoding of these codes is possible using an approximate belief propagation algorithm and near Shanno...

- S Lin
- D J Costello

S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood
Cliffs, NJ: Pearson Prentice Hall, 2004.

Introduction to Flash memory

- R Bez
- E Camerlanghi
- A Modelli
- A Visconti

R. Bez, E. Camerlanghi, A. Modelli, and A. Visconti, "Introduction to
Flash memory," Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.