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SPADIC - a Self-Triggered Detector Readout ASIC with Multi-Channel Amplification and Digitization
Abstract
The intention of this dissertation was the development of a multi-channel mixedsignal
detector readout ASIC. This paper describes the whole design process that starts
with the vague requirement for a readout chip for some CBM/FAIR sub-detector and that
ends with the latest and actually realized system on a chip solution called SPADIC, which
is mainly intended to read out the future CBM-TRD. This work comprises the design from
scratch of 6 ASIC prototypes and 10 PCB readout setups as well as the development of
various software and firmware components, the characterization of the designed ASICs, the
development of the SPADIC concept, the design of the SPADIC website, and not at least the
collaboration with the TRD physicists with the achieved goal to read out signals of chamber
prototypes using different SPADICs during CERN beam-times or in the laboratory. Besides
the descriptions of the most important chip details and the corresponding theoretical
analyses, an overall introduction into detectors and detector physics – written on a level
for engineers – is given in this paper in order to embed this technical work into its physical
context. The effective output of this dissertation is the self-triggered 32-channel charge
pulse amplification and digitization chip SPADIC 1.0.
... In the CBM experiment mainly mixed-signal ASICs are used. The digital logic is either implemented with standard cell libraries or, like in the SPADIC, a home made standard cell library is used where separated substrate contacts are possible which allows for a better isolation between bulk material and digital signal transitions [13]. But always at least a full-custom physical layer implementation is required for the I/O interface where also digital elements are developed individually to reach speed and drive strength. ...
... Other physical hardening and mitigation techniques are only applied to a particular full custom core, implemented in a CBMnet design, or for ASIC devices, e. g. the Universal Core Library (UCL), developed by the Chair of Circuit Design, Heidelberg University, has been used. This is a special home-made standard cell library, providing, amongst others, the unusual feature of separated substrate contacts [13]. Regarding SEUs, the protocol implementation of the digital part has been developed using several techniques. ...
... In case no more data was received for more than 50 ms, a manual reset of the device had to be done. The results are presented in fig. 4. 13. It can be recognized, that even for errors happening only in the data path (a), the version 2 has a heavily decreased data throughput. ...
Modern High Energy Physics experiments (HEP) explore the fundamental nature of matter in more depth than ever before and thereby benefit greatly from the advances in the field of communication technology. The huge data volumes generated by the increasingly precise detector setups pose severe problems for the Data Acquisition Systems (DAQ), which are used to process and store this information. In addition, detector setups and their read-out electronics need to be synchronized precisely to allow a later correlation of experiment events accurately in time. Moreover, the substantial presence of charged particles from accelerator-generated beams results in strong ionizing radiation levels, which has a severe impact on the electronic systems. This thesis recommends an architecture for unified network protocol IP cores with custom developed physical interfaces for the use of reliable data acquisition systems in strong radiation environments. Special configured serial bidirectional point-to-point interconnects are proposed to realize high speed data transmission, slow control access, synchronization and global clock distribution on unified links to reduce costs and to gain compact and efficient read-out setups. Special features are the developed radiation hardened functional units against single and multiple bit upsets, and the common interface for statistical error and diagnosis information, which integrates well into the protocol capabilities and eases the error handling in large experiment setups. Many innovative designs for several custom FPGA and ASIC platforms have been implemented and are described in detail. Special focus is placed on the physical layers and network interface elements from high-speed serial LVDS interconnects up to 20 Gb/s SSTL links in state-of-the-art process technology. The developed IP cores are fully tested by an adapted verification environment for electronic design automation tools and also by live application. They are available in a global repository allowing a broad usage within further HEP experiments.
... 2.2.5). These markers carry the uppermost bits of the time information in order to reduce the size of the message timestamps [39,40,38]. Another example are time over threshold measurements creating separate messages for leading and trailing edge of a signal [40]. ...
... The TRD-1D utilizes the SPADIC as the front-end ASIC, which combines analogue preamplifier, signal shaper, 9-bit ADC and digital message building in one chip [80,39]. ...
The data acquisition and processing concept of CBM is a novel and mandatory part
of the programme since the anticipated signatures cannot be extracted by means of a
conventional, triggered acquisition system. The Online Systems (Part I) Technical Design
Report contains the description of the hardware and FPGA design which forms the basis
of the CBM data processing chain. Its acceptance is crucial for reaching the overall goals
and is therefore pushed forward despite the lack of some information which is caused by
the unacceptable Russian attack of Ukraine and the resulting sanctions instituted. The
suspension of membership in the CBM collaboration of Russian institutes was endorsed
by the CBM Collaboration Board on May 18, 2022. Besides the superconducting dipole
magnet, CBM lost its centrality and event plane defining device, the Projectile Spectator
Detector (PSD), and the Beam Fragmentation Time-Zero Counter (BFTC) which had been
designed to deliver the event time for the highest interaction rates. The collaboration is
currently engaged in discussing and agreeing replacements. However, for the purpose of
advancing the Online Systems, in the current document we still use the original PSD and
BFTC numbers and their original geometries, with the reasonable assumption that the
replacement systems will have some similar properties in terms of data rate and volume.
The architecture of the proposed system is certainly flexible enough to accommodate
changes in the payload data structures and rates.
In continuous readout systems of particle physics experiments, the provision of a common clock and time reference and the distribution of critical low latency messages to the processing and fronted layers of the readout are crucial tasks. In the context of the Compressed Baryonic Matter (CBM) experiment, a versatile small form factor Timing and Fast-Control (TFC) interfacing FPGA Mezzanine Card (FMC) was developed, offering bidirectional twisted-pair (TP) links for the communication between TFC nodes. Also a versatile clocking including voltage controlled oscillators and a connection to the telecommunication clock lines of mTCA crates are available. Being designed for both TFC Master and Slaves, the card allows rapid system developments without additional Slave hardware circuits. Measurements show that it is possible to transmit over cable lengths of 25 m at a rate of 240 Mbit/s for all data channels simultaneously. A TFC Master-Slave system using two of these cards can be synchronized with a precision of ±10 ps to an user-defined phase setpoint.
Feature extraction is a data pre-processing stage of the Transition Radiation Detector (TRD) data-acquisition chain (DAQ) as part of the Compressed Baryonic Matter (CBM) experiment. The feature extraction stage delivers event-filtered and bandwidth-reduced data to the First Level Event Selector (FLES). The feature extraction stage implements multiple processing algorithms in order to find and extract regions of interest within time series signals. Algorithms such as peak-finding, signal integration, center of gravity and time-over threshold were implemented for online analysis. On the other hand, a local clustering algorithm allows to find cluster members and to implement even further data reduction algorithms. A feature extraction framework for automatic firmware generation has been tested for the CBM-TRD data acquisition chain. The framework allows the generation of Field Programmable Gate Array (FPGA) designs that implement feature extraction algorithms. Such designs are FPGA-platform independent and are described by a file written in a Domain Specific Language (DSL). The result of using the mentioned feature extraction framework for the TRD feature extraction stage is presented and discussed.
This biennial Review summarizes much of particle physics. Using data from previous editions, plus 2158 new measurements from 551 papers, we list, evaluate, and average measured properties of gauge bosons, leptons, quarks, mesons, and baryons. We also summarize searches for hypothetical particles such as Higgs bosons, heavy neutrinos, and supersymmetric particles. All the particle properties and search limits are listed in Summary Tables. We also give numerous tables, figures, formulae, and reviews of topics such as the Standard Model, particle detectors, probability, and statistics. Among the 108 reviews are many that are new or heavily revised including those on neutrino mass, mixing, and oscillations, QCD, top quark, CKM quark-mixing matrix, V-ud & V-us, V-cb & V-ub, fragmentation functions, particle detectors for accelerator and non-accelerator physics, magnetic monopoles, cosmological parameters, and big bang cosmology.
For detectors of the CBM experiment, high-rate, low-power and low-noise readout ASICs are needed. Since the Poisson distributed collisions between the nuclei are not correlated to a global trigger signal, the readout ASICs for both detectors as well as the data acquisition system itself must be self-triggered. The n-XYTER chip was developed for neutron exper-iments and nowadays it is also used for early prototyp-ing of the CBM detectors [1]. The performance of such a self-triggered front-end electronics has been studied last year [2]. The SPADIC chip [3] has been designed for the readout of the CBM transition radiation detectors. n-XYTER and SPADIC chips Their main difference is in the data storing and order-ing mechanism. The n-XYTER chip applies a Token Ring while the SPADIC chip uses an ordering FIFO to aggregate data from all channels into a single output. The Token Ring loops over all channels and if there is any data in a chan-nel FIFO the it reads it in and continues in the next period from next channel. Data do not come out time ordered and time re-sorting is needed at a later stage. This disadvantage is supposed to be eliminated by an ordering FIFO in the SPADIC chip. When a channel carries a signal it is (if pos-sible) stored in the channel FIFO and at the same moment there is an input information sent to the ordering FIFO. The FIFO is checked at each time period and the channels are read-out according to the information from this particular FIFO. Such a reading can lead to unexpected higher losses in the SPADIC chip and its performance has to be simu-lated therefore.
Using simple parametrizations of the thermodynamic freeze-out parameters extracted from the data over a wide beam-energy range, we reexpress the hadronic freeze-out line in terms of the underlying dynamic quantities, the net baryon density ρB and the energy density ɛ, which are subject to local conservation laws. This analysis reveals that ρB exhibits a maximum as the collision energy is decreased. This maximum freeze-out density has μ=400–500 MeV, which is above the critical value, and it is reached for a fixed-target bombarding energy of 20–30 GeV/nucleon.
For the readout of the TRD sub-detector of the planned fixed-target CBM experiment at FAIR/GSI (Darmstadt, Germany), a new self-triggered amplification and digitization mixed-signal chip is being developed. The final ASIC will have 32-64 channels each composed of a low noise and power charge preamplifier, a 7-9 Bit pipeline ADC running at about 25 MSamples/s and some digital data processing units carrying out detector specific tasks such as ion-tail cancellation and baseline correction. A token ring network will act as a balancing arbiter between the channels and the output serializer. The latest 180 nm test-chip has 26 preamplifier/shaper channels and 8 ADCs. For control signal generation and output decoding two synthesized blocks have also been integrated. By connecting both preamplifier and ADC, digital snap-shots of injected test-pulses have been recorded successfully, showing the proper oscilloscope-like operation of the whole mixed-signal data chain from analog amplification to digital output encoding.
We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn.
One of the most remarkable results to emerge from heavy-ion collisions over
the past two decades is the striking regularity shown by particle yields at all
energies. This has led to several very successful proposals describing particle
yields over a very wide range of beam energies, reaching from 1 A GeV up to 200
A GeV, using only one or two parameters. A systematic comparison of these
proposals is presented here. The conditions of fixed energy per particle,
baryon+anti-baryon density, normalized entropy density as well as percolation
model are investigated. The results are compared with the most recent chemical
freeze-out parameters obtained in the thermal-statistical analysis of particle
yields. The sensitivity and dependence of the results on parameters is analyzed
and discussed. It is shown that in the energy range above the top AGS energy,
within present accuracies, all chemical freeze-out criteria give a fairly good
description of the particle yields. However, the low energy heavy-ion data
favor the constant energy per particle as a unified condition of chemical
particle freeze-out. This condition also shows the weakest sensitivity on model
assumptions and parameters.
For the charge readout of the TRD sub-detector of the upcoming fixed-target experiment CBM at FAIR/GSI, a dedicated 32-channel mixed-signal readout ASIC is being developed in 180 nm. The first full-blown version called SPADIC 1.0 was submitted end of 2011 and is currently being tested in the laboratory. The SPADIC ASIC is a complete readout system from analog input charge to digital output protocol and hereby provides an oscilloscope-like readout scheme. Each channel consists of an amplifier (CSA, 800eENC), a continuously running pipeline ADC (8 bit effective, 25 MSamples/s), a digital filter (4-stage IIR), a hit detection logic (self-triggered), a message building mechanism, and finally an output buffer. The messages in the output buffers are arbitrated to one message stream, which subsequently is transmitted via a complex protocol serially over two 500 Mbitfs LVDS links out of the chip. The list of additional features is long, making the SPADIC ASIC a flexible solution for various detector applications.
The compressed baryonic matter (CBM) experiment will be one of the major scientific activities at the future Facility for Antiproton and Ion Research (FAIR) in Darmstadt. The goal of the CBM research program is to explore the QCD phase diagram in the region of high-baryon densities using high-energy nucleus-nucleus collisions. This includes the study of the equation-of-state of nuclear matter at high densities, and the search for the deconfinement and chiral phase transitions. The CBM detector is designed to measure both bulk observables with large acceptance and rare diagnostic probes such as charmed particles and vector mesons decaying into lepton pairs. The layout and the physics performance of the proposed CBM experimental facility will be discussed.
A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation
Transition Radiation Detectors (TRD) have the attractive feature of being able to separate particles by their gamma factor. Replacing the xenon based gaseous detectors by modern silicon detectors is complicated by the large energy losses of charged particles in 300–700μm of silicon. A silicon active pixel detector—DEPFET—has features which allows another detection technique to be used, in order to overcome the existing limitation on separating transition radiation photons with an energy loss from a charged particle in the same pixel. The tests of DEPFET with fiber radiator have been carried out at CERN SPS and DESY beams. The first results of test-beam measurements and Monte Carlo simulation are presented.
We present a new CMOS preamplifier and shaper, optimized for charge measurements with detectors of 0.1–1 pF capacitance. A self-adaptive biasing scheme with nonlinear pole-zero cancellation allows us to use an MOS device operated in the triode region as the DC feedback element while eliminating nonlinearity and sensitivity to supply, temperature, and process variations and accepting up to several μA leakage current. The circuit is continuously sensitive and requires no external adjustments to set the feedback resistance. Secondary sources of noise are minimized subject to a power dissipation constraint.Implemented in a 1.2 μm CMOS process, the preamplifier achieves an ENC of 35 e− + 58 e−/pF at 23 μs shaping time at a power consumption of about 3.2 mW. The integrated preamp/shaper has 50 ns shaping time and the ENC is 120 e−. It has 0.3% nonlinearity over an input dynamic range of 0–5 fC.
This paper gives tables of material properties needed for the evaluation of the collision stopping power for electrons and positrons according to the Bethe theory. The key quantity is the mean excitation energy of the medium, which has been derived for many materials by a critical analysis of experimental data. Also given are the density-effect parameters of the theory of Sternheimer and Peierls. The material properties are given for the elements and for 180 compounds and mixtures, and the rules are described by which they could be obtained for other materials. Tables are also given of auxiliary quantities which depend only on the kinetic energy of the incident electron. These, together with the main tables, make possible the quick-and-easy evaluation of the collision stopping power.
GRISU test ASICs were irradiated with different types of heavy ions, fluences up to 10 12 ions/cm 2 and with aL ET in the range of 1 - 60 MeV cm 2 /mg. Cross section for SEU/SET were measured during the tests. Furthermore TID measurements were applied. Results on degradation and annealing are reported.
An 8-channel preamplifier-shaper circuit for use with detectors having a capacitance in the range 20–50pF has been designed in 1.2μ CMOS AMS technology. The shaper is designed so that the peaking time can be adjusted, by steps, in the range 200ns–2μs by simple digital control. The pole-zero cancellation circuit uses an original method of sensing the preamplifier feedback capacitor discharging current and producing an identical current to discharge the capacitance of the pole-zero cancellation circuit. The series noise resistance rs=415Ω has been measured (270Ω of which is the protection resistor). The input capacitance of the preamplifier is 10pF + the strays of the test box 10pF for a total of 20pF. The input PMOS transistor has a gm of 5mA/V (from simulation) at 210μA drain current. The cross-talk between channels is less than 1%.
Experimental and theoretical data for dielectric functions, x-ray absorption coefficients, and generalized oscillator strengths needed for a description of the energy-loss spectrum of fast charged particles in solid silicon are given. Theories used to calculate spectra of total energy loss ("straggling spectra") are described. The convolution method is used to calculate straggling functions for thin silicon absorbers. They are compared with those obtained from other theories (Landau). For relativistic particles (gamma>100), the Vavilov-Shulek theories give incorrect functions for absorbers of thicknesses t
Moleère's theory of multiple scattering of electrons and other charged particles is here derived in a mathematically simpler way. The differential scattering law enters the theory only through a single parameter, the screening angle χa′, Eq. (21). The angular distribution, except for the absolute scale of angles, depends again only on a single parameter b, Eq. (22). It is shown that b depends essentially only on the thickness of the scattering foil in g/cm2, and is nearly independent of Z.
At very high energies, the collisional energy loss of hadrons passing through matter is reduced relative to that of a point particle because of their extended electromagnetic structures. For fermions, spin and magnetic moment effects work in the opposite direction. Analytic and numerical results are given for pions, muons, and protons. The reductions are small, but increase with energy. At 1 TeV, for example, the reduction is 2.7–3.4 % for pions and 1.4–1.9 % for protons, depending on the material. The influence of form factors on the so-called z3 effect at high energies is also addressed.
This paper summarizes recent trends in the area of low-power A/D conversion. Survey data collected over the past eleven years indicates that the power efficiency of ADCs has improved on average by a factor of two every two years. A closer inspection on the impact of technology scaling is presented to explain the observed trend in the context of shrinking supply voltages and increasing device speed. Finally, a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.
The current-mode ADC chip-prototype for the readout of DEPFET particle pixel-detectors with high spatial resolution is presented. The planned application of these DEPFET detectors are vertex detectors for ILC and Belle II. The chip has 72 ADC channels. Every channel processes the input signals using two cyclic ADCs that operate in parallel. The cyclic ADCs are based on current-mode memory cells. The measured signal to noise ratio of one ADC is about 660 (fast ADC variant: 520) and its conversion time is 320 ns (fast ADC variant: 160 ns) in the case of 8-bit resolution. Redundant signed-digit cyclic conversion is used for automated digital error correction. One ADC-core occupies only 40 ¿m à 55 ¿m, its static power consumption is 0.96 mW. Besides the two ADCs, every channel contains a regulated cascode and two additional current-mode memory cells that allow double-sampling of the input signal. Due to the need for high radiation tolerance, the chip has been implemented in a 180 nm CMOS technology using enclosed NMOS gate layouts. Novel radiation-hard circuits have been used. The chip has also been used to read out a small DEPFET test matrix.
We present an evaluative front-end realization of N-XYTER, the first data-driven ASIC dedicated to high rate imaging neutron detection. This ASIC development supplements the development of a suite of solid converter based neutron detectors within the EU-FP6 NMI3 project DETNI. They target future high intensity research applications at modern neutron sources. The neutron detectors under development, one of which being a silicon strip detector, will be able to perform 2D imaging with simultaneous time-of-flight measurement at neutron detection rates of up to 100 MHz. The ASIC realized in 0.35 μm CMOS technology has a 50 μm inter-channel pitch and is capable of both time and amplitude measurement of arbitrary polarity charge-pulses delivered by the detectors. Design and experimental characterization of this ASIC are presented.
We present the electron/pion identification performance measured with prototypes for ALICE TRD. Measured spectra of energy deposit of pions and electrons as well as their average values are presented and compared to calculations. Various radiators are investigated over the momentum range of 1–. The time signature of TR is exploited in a bidimensional likelihood method.
Scaling laws for the analog front end and related problems are discussed for detectors in the range from microstrips to pixel detectors. Design strategies for fast- and low-power building blocks (charge-sensitive preamplifier, shaper, discriminator and analog storage) are looked into. Merging of functions for minimal transistor counts, local analog storage versus digital-only output (trade-offs and limitations) and precision of and matching between readout elements are also discussed.
This is a condensed handbook, or an extended glossary, written in encyclopedic format, covering subjects relating to particle detectors, the underlying physics, and the analysis of their data. It intends to be both introduction for newcomers and reference for physicists working in the field. This BriefBook has been prepared by R K Bock, at CERN, Geneva, and A Vasilescu, at IFA, Bucuresti.
A technique is described whereby binary numbers of either sign may be multiplied together by a uniform process which is independent
of any foreknowledge of the signs of these numbers.
Energy losses of 2 and 8 GeV/c positive and negative electrons, pions and protons transmitted through 32–1040 μm thick germanium and silicon targets are measured using the targets as semiconductor detectors. The measured energy-loss distributions are well-reproduced by calculations when the binding of the target electrons is taken into account. In particular, the increasing width, up to twice as large as the width of the Landau distribution, and the decreasing most probable energy loss as a function of decreasing target thickness, agree with calculations. The same two quantities increase as a function of the relativistic βγ for βγ ≳ 4 until a saturation is reached for very large values of βγ. The constancy of the Fermi plateau, the saturation value of the most probable energy loss, is confirmed to the one percent level for the considered βγ values and thicknesses.
High-energy collisions between heavy nuclei have in the past 20 years provided multiple indications of a deconfined phase of matter that exists at phenomenally high temperatures and pressures. This 'quark-gluon plasma' is thought to have permeated the first microseconds of the Universe. Experiments at the Large Hadron Collider should consolidate the evidence for this exotic medium's existence, and allow its properties to be characterized.
A Transition Radiation Detector (TRD) has been designed to improve
the electron identification and trigger capability of the ALICE
experiment at the Large Hadron Collider (LHC) at CERN. We present
results from tests of a prototype of the TRD concerning pion rejection
for different methods of analysis over a momentum range from 0.9 to 2.4
GeV/c. We investigate the performance of different radiator types,
composed of foils, fibres and foams
It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, ¿sec, and quotients in 3 ¿sec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.
A method is developed for representing any communication system geometrically. Messages and the corresponding signals are points in two "function spaces," and the modulation process is a mapping of one space into the other. Using this representation, a number of results in communication theory are deduced concerning expansion and compression of bandwidth and the threshold effect. Formulas are found for the maxmum rate of transmission of binary digits over a system when the signal is perturbed by various types of noise. Some of the properties of "ideal" systems which transmit at this maxmum rate are discussed. The equivalent number of binary digits per second for certain information sources is calculated.
Although generally used in parallel multipliers, Booth encoding is shown to be obsolete due to the improvements in bit compression trees. It was found that a simple row of 4:2 compressors reduces the number of partial products to one half, which is the essential function of the Booth encoding technique. With a single row of 4:2 compressors this reduction is achieved in less time and with fewer gates used.
Analog-to-digital converters (ADCs) are ubiquitous, critical
components of software radio and other signal processing systems. This
paper surveys the state-of-the-art of ADCs, including experimental
converters and commercially available parts. The distribution of
resolution versus sampling rate provides insight into ADC performance
limitations. At sampling rates below 2 million samples per second
(Gs/s), resolution appears to be limited by thermal noise. At sampling
rates ranging from ~2 Ms/s to ~4 giga samples per second (Gs/s),
resolution falls off by ~1 bit for every doubling of the sampling rate.
This behavior may be attributed to uncertainty in the sampling instant
due to aperture jitter. For ADCs operating at multi-Gs/s rates, the
speed of the device technology is also a limiting factor due to
comparator ambiguity. Many ADC architectures and integrated circuit
technologies have been proposed and implemented to push back these
limits. The trend toward single-chip ADCs brings lower power
dissipation. However, technological progress as measured by the product
of the ADC resolution (bits) times the sampling rate is slow. Average
improvement is only ~1.5 bits for any given sampling frequency over the
last six-eight years
This paper presents a method and an algorithm for generation of a
parallel multiplier, which is optimized for speed. This method is
applicable to any multiplier size and adaptable to any technology for
which speed parameters are known. Most importantly, it is easy to
incorporate this method in silicon compilation or logic synthesis tools.
The parallel multiplier produced by the proposed method outperforms
other schemes used for comparison in our experiment. It uses the minimal
number of cells in the partial product reduction tree. These findings
are tested on design examples simulated in 1 μ CMOS ASIC technology
This "position paper" collects the scientific arguments behind the CERN Press Release of February 10, 2000, which announced evidence for the creation of a new state of matter in Pb-Pb collisions at the CERN SPS. The data on which this paper is based were presented in a special seminar at CERN on the same day, a recording of which can be accessed at http://www.cern.ch/CERN/Announcements/2000/NewStateMatter/ .
2.2. The Analog Pendant to an IIR Filter
- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adc Interface
ADC Interface....................................... 95
6.2. Digital Filter........................................ 96
6.2.1. Structure of IIR Filters............................. 97
6.2.2. The Analog Pendant to an IIR Filter..................... 98
6.2.3. Principle of Ion-Tail Cancellation....................... 99
6.2.4. Internal Resolution............................... 101
6.2.5. Realization of the Multipliers......................... 102
6.2.6. Other Design Aspects.............................. 103
3.2. Hit Detection and (Neighbor-)Trigger Concept
- Hit Detector
- . . . . . . . . . . . . . . . . . . . . . . Builder
- . . . Time-Stamp
Hit Detector and Message Builder........................... 104
6.3.1. Overall Block Diagram............................. 104
6.3.2. Hit Detection and (Neighbor-)Trigger Concept............... 105
6.3.3. (Multi-)Hit Handling, Selection Mask, and Time-Stamp......... 107
6.3.4. Lost Hits...................................... 108
6.3.5. Meta Data, Message Types, and Message Format............. 109
6.3.6. Hit Control and Message Builder....................... 111
6.3.7. Data Wrapper................................... 112
129 7.1.1. Digital Back End of SPADIC 0.3
- Readout . . . . . . . . . . . . . . . . . . . . System
The Latest SPADIC 0.3 Readout System........................ 129
7.1.1. Digital Back End of SPADIC 0.3........................ 130
7.1.2. FPGA Firmware.................................. 131
7.1.3. Software...................................... 131
7.1.4. Selected Results................................. 133
- Bel P Dillenseger
- A Arend
- H Appelshäuser
- M Hartig
T. Bel P. Dillenseger A. Arend, H. Appelshäuser and M. Hartig, Test of the Frankfurt
CBM TRD prototypes at the CERN-PS, GSI Scientific Report 2011 (2012), 48.
- D Emschermann
- C Bergmann
- A Andronic
- J P Wessels
D. Emschermann C. Bergmann, A. Andronic and J. P. Wessels, Test of Münster CBM
TRD prototypes at the CERN PS/T9 beam line, GSI Scientific Report 2011 (2012), 47.
The high-acceptance dielectron spectrometer HADES
The HADES Collaboration, The high-acceptance dielectron spectrometer HADES, The
European Physical Journal A 41 (2009), 243-277.
Charakterisierung und Signalanalyse von TRD-Prototypen fuer das CBM-Experiment
- P Dillenseger
P. Dillenseger, Charakterisierung und Signalanalyse von TRD-Prototypen fuer das CBM-Experiment, Master thesis, Institut für Kernphysik, Frankfurt University, 2012.
BTR_Accelerator and Scientific Infrastructure
- I Augustin
I. Augustin et al., BTR_Accelerator and Scientific Infrastructure, FAIR Baseline Technical
Report (2006).
The CBM Physics Book -Compressed Baryonic Matter in Laboratory Experiments
- Bengt Friman
- Claudia Hoehne
- Joern Knoll
- Stefan Leupold
- Joergen Randrup
- Ralf Rapp
- Peter Senger
Bengt Friman, Claudia Hoehne, Joern Knoll, Stefan Leupold, Joergen Randrup, Ralf
Rapp, and Peter Senger, The CBM Physics Book -Compressed Baryonic Matter in Laboratory Experiments, Lecture Notes in Physics, Springer, 2011.
Design Tips for the Front-End PCB
- Ivan Rusanov
- Gsi
Ivan Rusanov, GSI, Design Tips for the Front-End PCB, private communication, 2011.
Entwurf und Simulation eines digitalen Tail-Cancellation-Filters, Diploma thesis
- M Krieger
M. Krieger, Entwurf und Simulation eines digitalen Tail-Cancellation-Filters, Diploma
thesis, Lehrstuhl für Schaltungstechnik und Simulation, Universität Heidelberg, 2011.
Unified Synchronized Data Acquisition Networks, Dissertation
- F Lemke
F. Lemke, Unified Synchronized Data Acquisition Networks, Dissertation, Mannheim
University, 2012.
- J Lindhard
- M Scharff
- H E Schiøtt
J. Lindhard, M. Scharff, and H. E. Schiøtt, Kgl. Danske Videnskab. Selskab, Mat.-Fys.
Medd. 33 No. 14. (1963).