Development, Characterization and Operation of the DCDB, the Front-End Readout Chip for the Pixel Vertex Detector of the Future BELLE-II Experiment

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The BELLE-II detector is the upgrade of its predecessor named BELLE at KEK research centre in Tsukuba, Japan, which was successfully used in the past to find evidence for CP violating decays. The upgraded SuperKEKB accelerator is specified to produce a luminosity of 8*10^35 cm^-2 s^-1. Consequently, the BELLE-II detector and particularly the innermost pixel vertex detector (PXD) suffers from enormous occupancy due to background events. Coping with this harsh environment while providing the required physics performance results in tough specifications for the front-end readout electronics. The PXD pixel detector system is based on the DEPFET technology. DEPFET transistors combine particle detection and signal amplification within one device. The DCDB chip is developed to sample and digitize signals from these transistors while complying with the specifications of BELLE-II. The presented work illustrates the chip’s features and describes its implementation process. The device is comprehensively characterized using an individually developed test environment. The obtained results are presented. The DCDB’s ability to serve as a readout device for particle physics applications is demonstrated by its successful operation within a DEPFET detector prototype system. Highlights are a decay spectrum measurement using Cd-109 and the successful operation in a beam test experiment at CERN.

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... The DEPFET pixels are organized in columns that stretch along the length of the sensor. Each column is read out by a single channel of the DCD chip (Drain Current Digitizer [18,19,20,21]) locate at the end-of-ladder. The DCD analog input stage keeps the column line potential constant and compensates for variations in the DEPFET pedestal currents. ...
... provides an adequate rule of thumb for not-too-large values of the current. Measurements of the DCDB noise yield 80 nA for a capacitative load of 80 pF, that corresponds to a full-length DEPFET ladder [21,24]. The response of complete read-out modules built around DEPFET sensors from the PXD5 and PXD6 production has been characterized in beams of charged particles from accelerators at CERN and DESY [15,16,25,26]. ...
... The drain current signals from 256 columns of pixels are processed and digitized by the DCD (Drain Current Digitizer [22], [23], [24], [25]) chip. The analog input stage keeps the column line potential constant (necessary to achieve fast The DCD is implemented in UMC 0.18 µm CMOS technology using special radiation hard design techniques (e.g. ...
... The analog stage of the DCD is most important for the detector performance. The analog response has been characterized in detail [25], [27] on the test system of Figure 7 where a DCD2 and SWITCHER are connected to a full-size DEPFET sensor. ...
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The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 $\mathrm{\mathbf{\mu m}}$. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling and services. In this paper the status of DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear $\mathbf{e^+ e^-}$ collider.
The DEPFET sensor with signal compression (DSSC) project develops amegapixel X-ray camera dedicated for ultra-fast imaging at 4.5MHz frame rate at the European X-ray free electron laser facility in Hamburg. Further requirements are single photon resolution for so X-rays and a high dynamic range. The system concept includes a hybrid pixel detector, utilizing a non-linear DEPFET sensor. A dedicated readout ASIC allows full parallel readout of a 64 x 64 sensor pixel matrix by in-pixel filtering, immediate analog-to-digital conversion and storage. This thesis presents the ASIC working principle, architecture and the design of a test environment as well as test results of the electronics. Possible improvements of the circuits are highlighted. Measurements on sensor and ASIC assemblies are shown verifying the low noise and high dynamic range properties. The implementation of large scale tests for Known Good Die selection is reported. An introduction to free electron lasers and photon detection principles is included to put the DSSC system into the scientific context.
Full-text available
DEPFET pixels ofier a unique possibility for a high resolution pixel vertex detector as the innermost component of the tracking system in the TESLA detector. DEPFET pixels excel in comparison to other pixel detectors in the simultaneous achievement of high spatial, energy and time resolution even at room temperature operation. In the DEPFET pixel scheme the signal charge is not shifted out but is stored in the pixel until readout. Multiple readout is possible. The detector itself can be made very thin and does consume very little power. In this note the concept to use the DEPFET technology for the TESLA vertex detector is discussed. Possible design options for a DEPFET based vertex detector are presented and the progress of the R&D program which is presently carried out to meet the requirements at TESLA is described. In particular the advancements in sensor optimization and in the development of a fast readout scheme are discussed.
Full-text available
The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of < 100 ns. One of the major parts in the front-end electronics chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible. A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose. Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern. The chip was realized on a 3.2mm × 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module. Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented.
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This paper describes the first use of a Radiation Hardened by Design (DARE: Design Against Radiation Effects) library for the UMC 180 nm CMOS six-layer metal technology in a telecom application specific integrated circuit (ASIC). An innovative adapted "design for test" approach has been used to allow the evaluation of the behavior of this ASIC under radiation. Radiation tests results and conclusions on future use of this library are also presented.
Beam test results of the radiation tolerance study of chemical vapour deposition (CVD) diamond against different particle species and energies is presented. We also present beam test results on the independence of signal size on incident particle rate in charged particle detectors based on un-irradiated and irradiated poly-crystalline CVD diamond over a range of particle fluxes from 2 kHz/cm² to 10 MHz/cm². The pulse height of the sensors was measured with readout electronics with a peaking time of 6 ns. In addition functionality of poly-crystalline CVD diamond 3D devices was demonstrated in beam tests and 3D diamond detectors are shown to be a promising technology for applications in future high luminosity experiments.
The paper is based on the data of the 2009 DEPFET beam test at CERN SPS. The beam test used beams of pions and electrons with energies between 40 and 120GeV, and the sensors tested were prototypes with thickness of 450μm and pixel pitch between 20 and 32μm. Intrinsic resolutions of the detectors are calculated by disentangling the contributions of measurement errors and multiple scattering in tracking residuals. Properties of the intrinsic resolution estimates and factors that influence them are discussed. For the DEPFET detectors in the beam test, the calculation yields intrinsic resolutions of ≈1μm, with a typical accuracy of 0.1μm. Bias scan, angle scan, and energy scan are used as example studies to show that the intrinsic resolutions are a useful tool in studies of detector properties. With sufficiently precise telescopes, detailed resolution maps can be constructed and used to study and optimize detector performance.
We present the result of a search for charge asymmetry in B{sup {+-}}J/K{sup {+-}} decays using 772x10 BB pairs collected at the (4S) resonance by the Belle detector at the KEKB asymmetric-energy e{sup +}e collider. The CP-violating charge asymmetry is measured to be A{sub CP}(B{sup +}J/K{sup +})=[-0.76{+-}0.50 (stat){+-}0.22 (syst)]%.
The future super flavor factory SuperKEKB with its detector system Belle II offers precision physics measurements to verify the Standard Model or probe undiscovered phenomena beyond its limits. A two layer vertex pixel detector is built based on the DEPFET technology. The Depleted Field Effect Transistor (DEPFET) pixel structure is an advanced type of silicon semiconductor detector, which provides simultaneously position sensitive detector capabilities and internal amplification. Fast and low noise readout of large area DEPFET sensors with row rates of 10MHz is required. A new readout chip, the Drain Current Digitizer (DCD2), is available, which allows parallel readout of multiple channels with on-chip signal digitization. For the full characterization of this ASIC a FPGA based readout system has been designed, which also allows the operation of a prototype system including a DEPFET sensor. In this thesis, detailed measurements of the standalone performance of the DCD2 and the full system are presented; a limit on the possible readout speed of a large DEPFET sensor is established, and a switch from the slower double sampling readout scheme to a faster single sampling scheme is motivated.
This article gives an overview of the front-end electronics development for the DEPFET pixel vertex detector at the Super KEK-B experiment (BELLE II). The planned upgrade of the KEK-B factory will lead to a peak luminosity of 8×1035cm-2s-1. This increase in luminosity (×50 compared to the existing experiment) will make high demands on the performance of the vertex detector. The proposed two layer vertex detector consists of ‘all-silicon’ modules: the read-out and control ASICs will be bump bonded on the rigid edges of the DEPFET substrate whereas in the region of the active pixel matrix the substrate will be thinned down to 50μm. The front-end electronics is subdivided in three different ASIC types: one chip will provide up to 20V output swing for the control voltages of the DEPFET matrix (SWITCHER), the current signals are being digitized by a multichannel ADC chip (DCD) and the processing of the digital data and module control functionality is implemented in a data handling chip (DHP). An overview of the module concept and the status of the developments including results of current prototype chips will be given.
Dimuon production is studied in 400-GeV proton-nucleus collisions. A strong enhancement is observed at 9.5 GeV mass in a sample of 9000 dimuon events with a mass mmu+mu->5 GeV.
The DEPFET structure consists of a field effect transistor integrated on high-resistivity silicon, which can be used as a radiation detector. Due to several features (e.g. very low noise at room temperature, information storage capability and a thin, homogeneous entrance window), the DEPFET concept is useful for various applications. In order to apply a DEPFET pixel detector in autoradiography, 64×64 matrices with a pixel size of 50μm×50μm were built. Using several ASIC chips for the readout control and signal processing, a complete sensor system allows a row-by-row detector readout with almost continuous sensitivity. First results on the device homogenity, the quantum efficiency and the very promising noise performance are presented.
The DEPFET pixel detector offers first stage in-pixel amplification by incorporating a field effect transistor in the high resistivity silicon substrate. In this concept, a very small input capacitance can be realized thus allowing for low noise measurements. This makes DEPFET sensors a favorable technology for tracking in particle physics. Therefore a system with a DEPFET pixel matrix was developed to test DEPFET performance for an application as a vertex detector for the Belle II experiment. The system features a current based, row-wise readout of a DEPFET pixel matrix with a designated readout chip, steering chips for matrix control, a FPGA based data acquisition board, and a dedicated software package. The system was successfully operated in both test beam and lab environment. In 2009 new DEPFET matrices have been characterized in a 120GeV pion beam at the CERN SPS. The current status of the DEPFET system and test beam results are presented.
The DEPFET prototype system for the ILC is the first device under test using the EUDET JRA1 pixel telescope. This memo summarizes the experiences gath- ered during the 2008 CERN PS test beam period. In this presentation the current status of the integration of DEPFET into the EUDET Telescope frame work will be presented.
Using the precision vertex detectors of the Mark 2 at the SLC, an impact parameter tag was developed to select a sample of hadronic Z{degree} decays enriched in its fraction of bottom quark events. The nominal tagging method requires that there be at least three tracks whose impact parameters are inconsistent with the track having originated at the electron-position interaction point. A tagging efficiency for b{bar b} events of 50% with a enriched sample purity of 85% was achieved. This impact parameter tag was used to measure the fraction hadronic Z{degree} decays which produce b{bar b} events, F{sub b}. It is found that F{sub b} = 0.232{sub {minus}0.045}{sup +0.053} (stat) {sub {minus}0.021}{sup +0.025} (syst). This result is consistent with those found using other tagging methods as well as the Standard Model prediction of 0.217. The b{bar b}-enriched event sample was also used to measure the difference between the average charged multiplicity of b{bar b} events and that of all hadronic Z{degree} decays, {delta}{bar n}{sub b} = 2.11 {plus minus} 1.82(stat) {plus minus} 0.57(syst). Using previous measurements of the total hadronic charged multiplicity, the corresponding total multiplicity for b{bar b} events is {bar n}{sub b}=23.05 {plus minus} 1.82 (stat) {plus minus} 0.60 (syst). Subtracting the contribution to the multiplicity from B hadron decays yields the multiplicity of the b{bar b} non-leading system, {bar n}{sub nl} = 12.04 {plus minus} 1.82 (stat) {plus minus} 0.63(syst). Comparing this non-leading multiplicity to the total hadronic multiplicity data at lower energy supports the hypothesis that the non-leading particle production is independent of the flavor of the initial quarks.
Conference Paper
We propose a new detector system capable to fulfil the requirements of the future XFEL in Hamburg. The instrument will be able to record X-ray images with a maximum frame rate of 5MHz and to achieve a high dynamic range. The system is based on a pixel-silicon sensor with a new designed non-linear-DEPFET as a central amplifier structure. The detector chip is bump-bonded to a set of mixed signal readout ASICs that provide full parallel readout. The signals coming from the detector, after having been processed by an analog filter, are immediately digitized by a series of 8-ENOB ADCs and locally stored in a custom designed memory also integrated in the ASICs designed in the 130nm CMOS technology. During the time gap of 99ms of the XFEL machine, the digital data are sent off the focal plane to a DAQ electronics that acts as an interface to the back-end of the whole instrument. The pixel sensor has been designed so as to combine high energy resolution at low signal charge with high dynamic range. This has been motivated by the desire to be able to be sensitive to single low energy photons and, at the same time, to measure at other positions of the detector signals corresponding to up to 10<sup>4</sup> photons of 1keV. In order to fit this dynamic range into a reasonable output signal swing, achieving at the same time single photon resolution, a strongly non linear characteristics is required. The new proposed DEPFET provides the required dynamic range compression at the sensor level, considerably facilitating the task of the electronics. At the same time the DEPFET charge handling capacitance is enormously increased with respect to standard DEPFETs. The Pixel matrix will have a format of 1024×1024 with a pixel size of 200×200 µm<sup>2</sup>.
The current-mode ADC chip-prototype for the readout of DEPFET particle pixel-detectors with high spatial resolution is presented. The planned application of these DEPFET detectors are vertex detectors for ILC and Belle II. The chip has 72 ADC channels. Every channel processes the input signals using two cyclic ADCs that operate in parallel. The cyclic ADCs are based on current-mode memory cells. The measured signal to noise ratio of one ADC is about 660 (fast ADC variant: 520) and its conversion time is 320 ns (fast ADC variant: 160 ns) in the case of 8-bit resolution. Redundant signed-digit cyclic conversion is used for automated digital error correction. One ADC-core occupies only 40 ¿m × 55 ¿m, its static power consumption is 0.96 mW. Besides the two ADCs, every channel contains a regulated cascode and two additional current-mode memory cells that allow double-sampling of the input signal. Due to the need for high radiation tolerance, the chip has been implemented in a 180 nm CMOS technology using enclosed NMOS gate layouts. Novel radiation-hard circuits have been used. The chip has also been used to read out a small DEPFET test matrix.
A new kind of silicon pixel detector with integrated amplification has been built and tested. Each pixel consists of a p-channel JFET located on a fully depleted substrate. The pixel size can be customized by using a drift-chamber-like transport mechanism in each pixel. The homogeneity of the signal response of a small matrix was investigated with a laser diode. The measured rise time and gain of the device are analyzed with a simple small signal model.
We will in this paper discuss a novel concept for a ring imaging Cherenkov detector. It measures the time of propagation of the Cherenkov photons in a quartz radiator. The photon detectors are micro-channel-plate photo-multipliers with GaAsP photo-cathodes. The performance has been estimated to give a separation better than 3.5σ between K and π at . This detector, together with a compact focusing system to correct the chromatic effect, will have an even better resolution. We will show that it can achieve more than 4.2σ separation between K and π at . This detector is well suited for experiments at the Super B factory.
A new generation of MOS-type DEPFET active pixel sensors in double metal/double poly technology with ∼25 μm pixel size has been developed to meet the requirements of the vertex detector at the International Linear Collider (ILC). The paper presents the design and technology of the new linear MOS-type DEPFET sensors including a module concept and results of a feasibility study on how to build ultra-thin fully depleted sensors. One of the major challenges at the ILC is the dominant e+e− pair background from beam–beam interactions. The resulting high occupancy in the first layer of the vertex detector can be reduced by an extremely fast read out of the pixel arrays but the pair-produced electrons will also damage the sensor by ionization. Like all MOS devices, the DEPFET is inherently susceptible to ionizing radiation. The predominant effect of this kind of irradiation is the shift of the threshold voltage to more negative values due to the build up of positive oxide charges. The paper presents the first results of the irradiation of such devices with hard X-rays and gamma rays from a 60Co source up to 1 Mrad(Si) under various biasing conditions.
In the DEPFET pixel concept the detected incident radiation is directly sensed and amplified by a JFET integrated in every pixel cell. While the DEPFET detector principle has already been demonstrated previously on single pixel structures, we present here the first successful operation of a large 32×32 DEPFET pixel matrix as an imaging device. The matrix has been exposed to 60 keV gamma rays of a source and has been scanned using an IR laser. The principle of operation as well as the charge collection in the structure and possible improvements are discussed.
The anticipated physics program at an high energy e+e- linear collider places special emphasis on the accuracy in extrapolating charged particle tracks to their production vertex to tag heavy quarks and leptons. This paper reviews physics motivations and performance requirements, sensor R&D directions and current results of the studies for a vertex tracker at a future linear collider.
A new detector-amplification principle proposed by Kemmer and Lutz in 1986 has been experimentally verified. Outstanding features of this device are the built-in amplification, the signal charge storage capability and the possibility of repeated non-destructive readout. The device was used for detection of X-rays from a 241Am and from Am and from an 55Fe source. Very low noise figures (σ=30 electrons corresponding to an energy resolution of FWHM = 250 eV at 6 keV energy) have been obtained at room temperature. Various applications of the structure either as detector or as purely electronic element are possible. One of the most intriguing is the use as a pixel detector with random access non-destructive readout. This device may be operated at very low power, as only reading (of one single pixel at a time), not storing, consumes power. Further options of the device are fast clearing, gating and variation of the pixel size during readout. The latter property can be used to drastically increase the readout speed compared to more standard two dimensional devices as e.g. CCD detectors, as one may restrict the high density readout to regions of interest determined beforehand by a coarse scan of the whole detector. An alternative use of the device is as an analog or digital memory, or as a simple transistor with drastically reduced parasitic capacitances. Possible further developments are the combination with a novel three dimensional analog storage device which may either be used as a detector with built-in storage of several charge images or as a three dimensional analog memory.
Some recent developments in “standard” detectors such as silicon strip detectors are described and a proposal for further improvement is made. In view of future applications in high rate environments we propose completely new detector-amplification structures for two dimensional measurement with gating and fast clearing possibilities. One of them allows local storage of several charge images in sequence and delayed selective readout.
In a framework of the renormalizable theory of weak interaction, problems of CP-violation are studied. It is concluded that no realistic models of CP-violation exist in the quartet scheme without introducing any other new fields. Some possible models of CP-violation are also discussed.
The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique. Report / Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory, ISSN 1455-8440; 33
It is shown that a function is computable by an on-the-fly algorithm processing data in the most significant digit first fashion with a finite number of registers if and only if it is computable by a right subsequential finite state machine processing deterministically data in the least significant digit first fashion. Some applications to complex radix number systems are given
Field effect transistors embedded into a depleted silicon bulk (DEPFETs) can be used as the first amplifying element for the detection of small signal charges deposited in the bulk by ionizing particles, X-ray photons or visible light. Very good noise performance at room temperature due to the low capacitance of the collecting electrode has been demonstrated. Regular two dimensional arrangements of DEPFETs can be read out by turning on individual rows and reading currents or voltages in the columns. Such arrangements allow the fast, low power readout of larger arrays with the possibility of random access to selected pixels. In this paper, different readout concepts are discussed as they are required for arrays with incomplete or complete clear and for readout at the source or the drain. Examples of VLSI chips for the steering of the gate and clear rows and for reading out the columns are presented. Comment: 8 pages, 9 figures, submitted to Nucl. Instr. and Methods as proceedings of the 9th European Symposium on Semiconductor Detectors, Elmau, June 23-27, 2002
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