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Driving, conditioning and signal acquisition
Prototype ASIC for Large Format NIR/SWIR
Detector Array
B.Dupont,Peng Gao, B.Dierickx,
G.Verbruggen, S.Gielis, R.Valvekens,
Scientific Detector Workshop
October 10, 2013, Florence
2013 10 07 ASIC for LF NIR/SWIR detector array 1
status
•Development in two phases:
–Prototype ASIC (2013)
–Final product design (2014-2015)
–Device is just back from foundry:
–Tests will go on until jan 2014
2013 10 07 2 ASIC for LF NIR/SWIR detector array
Outline
•Motivation and technical challenges
•Design for Radiation hardness and Cryogenic
temperature
•Circuit design and simulation
•Test setup
•Conclusions
2013 10 07 3 ASIC for LF NIR/SWIR detector array
Outline
•Motivation and technical challenges
•Design for Radiation hardness and Cryogenic
temperature
•Circuit design and simulation
•Test setup
•Conclusions
2013 10 07 4 ASIC for LF NIR/SWIR detector array
A signal conditionning ASIC
2013 10 07 5
This development aims at providing the community with
a signal conditioning ASIC
• Tailored to imagers (especially IR sensor)
• Versatile
• With a wide operating temperature range
• Taking in consideration multiple IR detector manufacturers
specificities
• Able to drive multi-sensor systems
ASIC for LF NIR/SWIR detector array
Why an ASIC ?
2013 10 07 6
[Z.Zhao.SDA’05]
Data acquisition and control system for IR imagers
Digital domain
Digital control core
Memory & Clock
Data Communication
Analog domain
Signal conditioning
Analog to digital converter
Regulated power supply
Bias voltage/current references
ASIC for LF NIR/SWIR detector array
A true mixed mode ASIC
2013 10 07 7 ASIC for LF NIR/SWIR detector array
Challenging specifications
2013 10 07 8
Analog domain
Function No. specifications
LDO 4 1.3-3.4 [V], 100mA max. supply current
Analog inputs 16
Preamplifier / CDS /
Offset cancellation 4 5 gains, 25uV RMS noise
8 bits Offset removal
16-bit ADC 4 Successive approximation with bits calibration
Target DNL < 1,5 LSB
ROIC bias and
Reference voltages 16 10 bits, rail to rail operation
ROIC health monitoring 4 Resistors / differential voltage monitoring
16 bits
Internal reference 1 1.2V Bandgap
Temperature sensor 1
ASIC for LF NIR/SWIR detector array
Challenging specifications
2013 10 07 9
Digital domain
Master clock 0 – 200 MHz
System level protocol 2 – 200 Mbit/s Space Wire
ROIC digital control 32
Scheduler time granularity 10M updates/s
Sequence nesting depth 8
ROIC monitoring and trigger inputs 8
ROIC programming channel 1 SPI
ASIC for LF NIR/SWIR detector array
Environmental constraints
2013 10 07 10
Challenging design for:
• Cryogenic temperature (77K)
• … but not only: operates from 77K to room temperature
• Radiation tolerance in space (designed up to 1Mrad TID,
60MeVcm2 /mg SEU)
• High reliability
• Scalalibility
ASIC for LF NIR/SWIR detector array
Outline
•Motivation and technical challenges
•Design for Radiation hardness and Cryogenic
temperature
•Circuit design and simulation
•Test setup
•Conclusions and future work
2013 10 07 11 ASIC for LF NIR/SWIR detector array
Radiation hardness
Radiation hardness is a concern for:
•Synthetized digital logic
•Analog custom designed cells
2013 10 07 12 ASIC for LF NIR/SWIR detector array
Radiation hardness: digital design
The project uses DARE Library
•Developed by IMEC
•Designed up to Mrad, used in flight models
•DARE180 (UMC 0.18um 1P6M CMOS)
•Radiation Hard Standard Cells, SRAM, I/O cells, PLL
•Intrinsic protection against Latch up and TID
•Flip-flop protected against SEU
•Allows custom mixed-signal design
2013 10 07 13 ASIC for LF NIR/SWIR detector array
Radiation hardness: digital design
Beyond library, circuit topology is rad hard:
•Redundancy
•Hamming Codes
•Parity check
•Safe FSMs
•Watchdog Timers
2013 10 07 14 ASIC for LF NIR/SWIR detector array
Radiation hardness: analog design
DARE has a limited subset of analog component.
Caeleste uses its own radhard cells
•Analog and High Voltage logic standard cells
•Full custom tactical cells
Prevention for:
•Single Event
•Total dose
2013 10 07 15
Layout using Caeleste’s standard library
(left) and the same in the fully radiation
hard library (right)
ASIC for LF NIR/SWIR detector array
Design for low temperature
Analog and digital flow require different approach on
modeling and design strategy for cryogenic temperature:
•Synthetized digital logic:
–Validation of key blocks (such as SRAM)
–A derating of speed, power, etc. of the library
•Analog custom design:
–Active and passive component
2013 10 07 16 ASIC for LF NIR/SWIR detector array
Cryogenic digital design
The DARE library has never been used at 77K
The logic becomes faster. However one must take care of
set-up and hold time violation.
The library models have be adapted, based on a model
characterized at 218K
Other components like SRAM are also to be validated still
2013 10 07 17 ASIC for LF NIR/SWIR detector array
Cryogenic analog design
•MOSFET modeling
–Vth: increase
–Mobility: increase
–MOS switch: low Ron
•Careful choice of passive components
–Highly doped non silicide poly Resistor for stability
–MIM capacitors
2013 10 07 18 ASIC for LF NIR/SWIR detector array
Outline
•Motivation and technical challenges
•Design for Radiation hardness and Cryogenic
temperature
•Circuit design and simulation
•Test setup
•Conclusions
2013 10 07 19 ASIC for LF NIR/SWIR detector array
Analog section
2013 10 07 20 ASIC for LF NIR/SWIR detector array
Analog section
2013 10 07 21 ASIC for LF NIR/SWIR detector array
LDO
•LDO
–Programmable output
–Stability: PM>60°
–Output current 0-100mA
•Bandgap
–1.2V
–77K-300K
2013 10 07 22 ASIC for LF NIR/SWIR detector array
LDO: tunning range
Fine / coarse
Tuning
Extended
Range:
1,3…4,2V
2013 10 07 23 ASIC for LF NIR/SWIR detector array
LDO: stability
2013 10 07 24 ASIC for LF NIR/SWIR detector array
ADC
•16-bit, 50-200kHz, fully differential SAR ADC
–Feedback DAC 11 MSBs capacitive and 5 LSBs resistive
–Low offset comparator: auto zero
•A calibration scheme is available
2013 10 07 25 ASIC for LF NIR/SWIR detector array
ADC: model driven design
2013 10 07 26
Effect of mismatch
calibration on DNL
ASIC for LF NIR/SWIR detector array
ADC: design verification
2013 10 07 27
Full analog simulation:
Effect of calibration on linearity
ASIC for LF NIR/SWIR detector array
Digital design
2013 10 07 28 ASIC for LF NIR/SWIR detector array
Digital design
2013 10 07 29 ASIC for LF NIR/SWIR detector array
Outline
•Motivation and technical challenges
•Design for Radiation hardness and Cryogenic
temperature
•Circuit design and simulation
•Test setup
•Conclusions and future work
2013 10 07 30 ASIC for LF NIR/SWIR detector array
Test setup
2013 10 07 31 ASIC for LF NIR/SWIR detector array
Digital Controller
Analog test
board
Precision
DAC board
ASIC
COB
Base plate
Unified design for:
Room temperature board
Cryogenic temperature
Outline
•Motivation and technical challenges
•Design for Radiation hardness and Cryogenic
temperature
•Circuit design and simulation
•Test and measurements
•Conclusions and future work
2013 10 07 32 ASIC for LF NIR/SWIR detector array
Conclusions
2013 10 07 33
•Fully custom design high performance mixed signal
ASIC
•From cryogenic(77K) to room temperature
•Radiation hard for TD and SE
•Highly flexible for ROICs
•Highly programmable sequencer
•Wide programmability and large dynamic ranges in
analog circuits
•Beyond IR imagers
ASIC for LF NIR/SWIR detector array
Next steps ?
2013 10 07 34
•Testing!
•Larger Asic with multiple channels (32 to 64)
•Faster ADCs are under development (up to
12MSamples /s with reduced resolution)
•More discussion with instrument builders and IR sensor
manufacturers for further enhancements
•Irradiation testing and deeper temperature testing
ASIC for LF NIR/SWIR detector array
Thank you!
2013 10 07 35 ASIC for LF NIR/SWIR detector array