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Performance Analysis of Verilog Directed Testbench vs Constrained Random SystemVerilog Testbench
Extremely low power, low voltage complete on-chip low drop-out voltage regulator (LDO) is presented. The LDO receives an unregulated supply of 0.5–1 V and regulates it to 0.4 V nominal output utilizing a 0.1 V on-chip reference voltage. A load capacitor of just 1pf is assumed to be present at LDO output. Designed voltage reference and complete LDO were simulated in 180 nm CMOS technology with variation in supply voltage and temperature. The maximum power dissipation of the complete LDO was found to be approximately 3nW and maximum line and load regulations were observed to be 6.62 mV/V and 8.08 mV/mA, respectively.
Synchronous serial interfaces are widely used to provide economical board level interfaces between different devices such as microcontrollers, DACs ADCs and other. Many IC manufacturers produce components that are compatible with SPI and Microwire/plus. The SPI Master core is compatible with both protocols as master with some additional functionality. At the hosts side,the core acts like a Wishbone compliant slave device. The SPI master core consists of three parts, Serial interface, clock generator and Wishbone interface. The SPI core has five 32-bit registers through the Wishbone compatible interface. The serial interface consists of slave select lines, serial clock lines, as well as input and output data lines. All transfers are full duplex transfers of a programmable number of bits per transfer(upto 64 bits).It has 8 slave select lines but only one is selected at a time. We design the SPI Master-Slave core design using system verilog and do functional verification for our design in modelsim.
Constrained random simulation has been widely adopted in contemporary hardware verification flows. In this methodology, a set of user-specified declarative constraints describe valid input stimuli for the design under test (DUT). A constraint solver produces the simulation input vectors; their generation is interleaved with the actual simulation of the design for these vectors. Besides its distribution, the solver's performance is one of the most critical characteristics that determines the overall verification efficiency. There are no general approaches to hardware acceleration for solving declarative constraints. Current setups for hardware acceleration-based verification combine a software constraint solver running on a general-purpose processor with the hardware-accelerated DUT. This approach suffers from a major efficiency bottleneck caused by the significant performance mismatch between the solver executed in software and the DUT running on an accelerator. In this paper, we present a hardware constraint solver that uses a set of parallel solving units executing Markov chain Monte Carlo sampling. We propose to combine this solver and the DUT on the same device and run both entities hardware-accelerated in order to eliminate the performance mismatch. We discuss the details of the solver architecture and its implementation and report comprehensive results on performance and distribution characteristics as well as experience obtained from our case study where we used our solver to verify a real-world hardware design.
Don't Forget the Little Things That Can Make Verification Easier
- Stuart Sutherland
Stuart Sutherland, "Don't Forget the Little Things That
Can Make Verification Easier," Verification Horizons,
Mentor Graphics
An Efficient Method for Using Transaction Level Assertions in a Class Based Verification Environment
- B R Sudhishnaveen
- Yagainharish Raghavendra
SudhishNaveen, BR Raghavendra, YagainHarish, "An
Efficient Method for Using Transaction Level Assertions
in a Class Based Verification Environment,"
International Symposium on Electronic System
Design,pp.72-76, 2011
SPI Master Core Specification
- Srot Simon
Srot Simon, " SPI Master Core Specification,"Rev. 0.6,
March 15, 2004