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Research Article
A Discrete Event System Approach to Online Testing of
Speed Independent Circuits
P. K. Biswal, K. Mishra, S. Biswas, and H. K. Kapoor
Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India
Correspondence should be addressed to S. Biswas; santoshbiswas@yahoo.com
Received November ; Revised March ; Accepted March
Academic Editor: Marcelo Lubaszewski
Copyright © P. K. Biswal et al. is is an open access article distributed under the Creative Commons Attribution License,
which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
With the increase in so failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some
techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that
veries the correctness of the protocol. is checker involves Mutex blocks making its area overhead quite high. In this paper, we
have adapted the eory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of
speed independent asynchronous circuits. e scheme involves development of a state based model of the circuit, under normal
and various stuck-at fault conditions, and nally designing state estimators termed as detectors. e detectors monitor the circuit
online and determine whether it is functioning in normal/failure mode. e main advantages are nonintrusiveness and low area
overheads compared to similar schemes reported in the literature.
1. Introduction
With the advancement of VLSI technology for circuit design,
there is a need to monitor the operations of circuits for
detecting faults []. ese needs have increased dramatically
in recent times because, with the widespread use of deep
submicrontechnology,thereisariseintheprobabilityof
development of faults during operation. Performing tests
before operation of a circuit and assuming continued fault-
free behaviour may decrease the reliability of operation. In
other words, there is a need for online testing (OLT) of
VLSI circuits, whereupon they are designed to verify, during
normal operation, whether their output response conforms to
the correct behaviour.
MostofthecircuitsusedinVLSIdesignsaresyn-
chronous. Compared to synchronous circuits, asynchronous
designs oer great advantages such as no clock skew problem,
low power consumption, and average case performances
rather than the worst case performances. Testing asyn-
chronous circuits as compared to synchronous circuits is
considered dicult due to the absence of the global clock [].
OLT has been studied for the last two decades and can be
broadly classied into the following main categories:
(i) Self-checking design.
(ii) Signature monitoring in FSMs.
(iii) Duplication.
(iv) Online BIST.
e approach of self-checking design consists of encoding
the circuit outputs using some error detecting code and
then checking some code invariant property (e.g., Parity) [–
]. Some examples are Parity codes [], m-out-of-n codes
[],andsoforth.eareaoverheadformakingcircuits
self-checkable is usually not high. ese techniques, termed
as “intrusive OLT methodologies,” require some special
properties in the circuit structure to limit the scope of fault
propagation. ese properties can be achieved by resynthesis
and redesign of the original circuit, which may aect the
critical paths in the circuit.
Signature monitoring techniques for OLT [,]work
by studying the state sequences of the circuit FSM model
Hindawi Publishing Corporation
VLSI Design
Volume 2015, Article ID 651785, 16 pages
http://dx.doi.org/10.1155/2015/651785
VLSI Design
during its operation. ese schemes detect faults that lead to
illegal paths in the control ow graph, that is, paths having
transitions which do not exist in the specied FSM. To make
the runtime signature of the fault-free circuit FSM dierent
from the one with fault, a signature invariant property is
forcedduringFSMsynthesis,makingthetechniqueintrusive.
Further, the state explosion problem in FSM models makes
the application of this scheme dicult for practical circuits.
Duplication based OLT technique works by simply
replicating the original circuit and comparing the output
responses []; a fault is detected if the outputs do not
match. e major advantage of duplication based scheme is
nonintrusivity; however, area overhead is more than double.
To address this issue, partial duplication technique is applied
[,]. is scheme rst generates a complete set of test
vectors for all the faults possible, using Automatic Test Pattern
Generation (ATPG) algorithms. Aer that, a subset of faults
areselected(basedonrequiredcoverage)andasubsetoftest
vectors (based on tolerable latency) for the selected faults are
taken and synthesized into a circuit which is used for OLT. It
may be noted that ATPG algorithms are optimized to gener-
ate the minimum number of test vectors that detect all faults.
As the scheme applies ATPG algorithms in a reverse philos-
ophy, it becomes prohibitively complex for large circuits.
e technique of designing circuits with additional on-
chip logic, which can be used to test proper operation of
the circuit before it starts, is called o-line BIST. O-line
BIST resources are now being used for online testing [–
]. is technique utilizes the idle time of various parts of
the circuit to perform online BIST. Idle times are reducing in
circuits because of pipelining and parallelism techniques and
so online BIST scheme is of limited utility.
Motivation of the Work.Fromtheabovediscussionwemay
state that an ecient approach for OLT should have the
following metrics:
(i) e OLT scheme should be nonintrusive. is is
the most important constraint as designers meet
requirements, like frequency, area, power, and so
forth, of the circuit to produce an ecient design and
do not want the test engineers to change them.
(ii) e OLT technique should support well accepted fault
models.
(iii) e scheme should be computationally ecient so
that it can handle reasonably large circuits.
Mostofthepaperscitedintheabovediscussionarefor
OLT of synchronous circuits and only a few of them [,,]
are applicable to asynchronous circuits. Now, we elaborate on
these three works on OLT of asynchronous circuits and derive
motivation of the present work.
Traditionally, double redundancy methods were used for
OLT of asynchronous designs []. In this scheme, two copies
of the same circuit work in parallel and the online tester
checks whether they generate the same output. is scheme
results in more than % area and power overheads. Further,
both being the same circuit, they are susceptible to similar
nature of failures. e schemes reported in [,]basically
work by checking whether the output of the asynchronous
circuit maintains a predened protocol (i.e., there is no
premature or late occurrence of transitions). e checker
circuit is implemented using David cells (DCs), Mutual
Exclusion (Mutex) elements, C-elements, and logic gates.
e checker circuit has two modes: operation-normal mode
andself-testmode.Innormalmode,thecheckerisusedto
detect whether there is any violation in the protocol being
executed by the CUT. On the other hand, in self-test mode,
the checker is used to detect faults that may occur within the
checker itself. Mutex elements (component of asynchronous
arbiter) were used to grant exclusive access to the shared
DCs between dierent modes of operation. e area overhead
of the Mutex blocks is high, even compared to the original
circuit. So, area overhead of the online tester in this case
wouldbemuchhigherthanthatoftheoriginalcircuitand
even the redundancy based methods. Further, this tester only
checks the protocol and so fault coverage or detection latency
cannot be guaranteed.
Discrete event system (DES) model based methods are
usedforfailuredetectionforawiderangeofapplications
because of the simplicity of the model as well as the associated
algorithms []. A DES is characterized by a discrete state
space and some event driven dynamics. Finite state machine
(FSM) based model is a simple example of a DES. In the state
based DES model, the model is partitioned according to the
failure or normal condition. e failure detection problem
consists in determining, in nite time aer occurrence of the
failure, whether the system is traversing through normal or
failure subsystem. A fault is detectable by virtue of certain
transitions (in the failure states) which are called fault detect-
ing transitions (FD-transitions). FD-transition is a transition
of the faulty subsystem, for which there is no corresponding
equivalent transition in the normal subsystem. Using the FD-
transitions, a DES fault detector is designed, which is a kind of
state estimator of the system. For OLT of circuits, the detector
is synthesized as a circuit which is executed concurrently with
the circuit under test (CUT). Biswas et al. in [,]have
developed an OLT scheme for synchronous circuits using the
FSM based DES theory, which satises most of the metrics
mentioned above for an ecient online tester design. In this
paper, we aim at using the theory of failure detection of DES
models for OLT of SI circuits.
Just like synchronous circuits, the basic FSM framework
is also used to model asynchronous circuits with slight
modication. In case of synchronous circuits, state changes
intheFSMoccuronlyattheactiveedgeoftheregister
clock, irrespective of the time of change of the inputs. On
theotherhand,inasynchronouscircuits,statechangescan
occur immediately aer transition in the inputs. FSM used
to model asynchronous circuit is called AFSM []. An
alternative to AFSM is burst-mode (BM) state machines [].
AFSMandBMstatemachinearesimilarfromthemodeling
perspective; however, in case of BM state machine transitions
are labeled with signal changes rather than their explicit
values, which is the case in AFSMs. AFSMs and BM state
machines assume that rst inputs change followed by outputs
andnallynewstateisreached.Duetothestrictsequence
of signal changes, all asynchronous protocols cannot be
VLSI Design
modeled using AFSMs or BM state machines. Extended
BM state machines address this modeling issue by allowing
some inputs in a burst to change monotonically along a
sequence of bursts rather than in a particular burst. Petri
net(PN)iswidelyacceptedmodelingframeworkforhighly
concurrent systems []. PN models a system using interface
behaviors which are represented by allowed sequence of
transitions or traces. e view of an asynchronous circuit as a
concurrent system makes PN based models more appropriate
than AFSMs and BM state machines for their analysis and
synthesis. ere are several variants of PNs among which
signal transition graph (STG) is generally used to model
asynchronous circuits. e major reason is that the STG
interprets transitions as signal transitions and species circuit
behavior by dening casual relations among these signal
transitions [].
In this paper, we aim at using the theory of failure
detection of DES model for OLT of SI asynchronous circuits.
Several modications are made in the DES framework used
for synchronous circuits [,]whenappliedforSIcircuits.
e modications are as follows:
(i) We rst model SI circuits along with their faults as
STGs and then translate them into state graphs. State
graphs are similar to FSM based DES models from
which FD-transitions can be determined.
(ii) In case of synchronous circuits, the fault detector
is an FSM which detects the occurrence of FD-
transitions. A synchronous circuit can be synthesized
in a straightforward way from the FSM specication
[,] that performs online testing. Why the same
design cannot be synthesized as an asynchronous
circuit will be discussed in this paper. As the use
of synchronous circuit for OLT of asynchronous
modules is not desirable, we propose a new technique
for detector design which can be synthesized as a SI
circuit. e detector is designed as state graph model
whichisliveandhascompletestatecoding(CSC);
these properties ensures its synthesizability as a SI
circuit.
e paper is organized as follows. In Section ,wepresent
some denitions and formalisms of the DES framework.
Section illustrates DES modeling for a speed independent
circuit under normal and stuck-at faults. In Section ,the
DES detector for the SI asynchronous circuit is designed.
Synthesizing the DES detector as online tester circuit is also
discussed in the same section. Section presents experi-
mental results regarding area overhead and fault coverage of
the DES detector based online tester. Also, comparison of
area overhead of the proposed approach with other similar
schemes is reported. Finally, we conclude in Section .
2. DES Modeling Framework:
Definitions and Formalisms
Adiscrete event system (DES) model is dened as =
,, I,0where ={V1,V2,....,V𝑛}(Incaseofmodeling
SI circuits as DES, the state variables are values of the I/O
signals. So, in this work, we will interchangeably use the
terms signal and variable.) is a nite set of discrete variables
assuming values from the set {0,1}, called the domains of
the variables, is a nite set of states, Iis a nite set of
transitions, and 0 ⊆ is the set of initial states. A state
is a mapping of each variable to one of the elements of the
domain of the variable. A transition ∈Ifrom a state to
another state +is an ordered pair ,+,whereis denoted
by () and +is denoted as ().
2.1. Failure Modeling. e failure of the system is modeled by
dividing the DES model into submodels and each submodel is
used to model the system under normal or failure conditions.
To dierentiate between the submodels, each state is
assigned a failure label by a status variable with its domain
being equal to { ∪ 1∪
2∪⋅⋅⋅∪
𝑑},whereis normal
status, 𝑖,1≤≤,isfailurestatus,andis the number of
possible faults.
Denition 1 (normal -state). A -state is normal if () =
{}. e set of all normal states is denoted by 𝑁.
Denition 2 (𝑖--state). A -state is failure state or
synonymously an 𝑖-state, if 𝑖∈ ().esetofall𝑖-states
is denoted by 𝐹𝑖.
Denition 3 (normal -transition). A -transition ,+is
called a normal -transition if ,+∈
𝑁.
Denition 4 (𝑖--transition). A -transition ,+is
called an 𝑖--transition if ,+∈
𝐹𝑖.
Denition 5 (equivalent states). Two states and are said to
be equivalent, denoted by ,if|𝑉=|
𝑉and () = ().
Inotherwords,twostatesaresaidtobeequivalentifthey
have the same values for state variables and dierent value for
status variable.
A transition ,+,where() =
+(),iscalledafailure
transition indicating the rst occurrence of some failure in
the system. Since failures are assumed to be permanent,there
is no transition from any state in 𝐹𝑖to any state in 𝑁or
from any state in 𝐹𝑖to any state in 𝐹𝑗.
Denition 6 (equivalent transitions). Two transitions 1=
1,+
1and 2=
2,+
2are equivalent, denoted by 12,
if 12,+
1+
2andtheymustassociatewiththesamesignal
change.
Suppose that there is a transition in failure DES model
for which there is no corresponding equivalent transition
in normal DES model, then that transition is called failure
detecting transition (FD-transition). e failure is detected
when the system traverses through the FD-transition. us,
we can dene FD-transition as follows.
Denition 7 (FD-transition). A 𝑖--transition of faulty DES
model =
,+is an FD-transition, if there is no -
transition =,
+in the normal DES model such that
.
VLSI Design
e motivation of failure detection using DES model is to
nd out such FD-transitions and design DES detector using
these transitions. In the next section, we discuss how to model
SI circuits using DES.
3. DES Model of a Speed Independent Circuit:
Normal and Faulty
As already discussed, the rst step to design a DES based
online tester is to obtain the normal and faulty state based
model of the CUT. However, the traditional state based DES
paradigm cannot be directly used for modeling SI circuits. So
in this case we will start with signal transition graph (STG),
which is a type of Petri net based DES, to specify fault-free
and faulty conditions. e STGs will be converted into state
graphs(similartoFSMs)usingtheconceptpresentedin[].
We rst discuss fault modelling at the STG level using
an example and concepts from []. In addition to the
models (i.e., faults in transistors of the C-elements) given in
[], we have also modeled stuck-at faults on all wires (i.e.,
input/output of gates).
3.1. Fault Modeling. e SI asynchronous CUT example
being considered to illustrate the proposed scheme is shown
in Figure (taken from []). Traditionally, synchronous
circuits consist of blocks of combinational logic connected
with clocked latches or registers, while, in case of SI circuit
designs, we basically have logic gates as building blocks with
C-elements, which act as storage elements. Transistor level
diagram of C-element is shown in Figure ; logic function of
the C-element can be described by the Boolean equation =
++,whereisthenextstateandis the old state
value [,]. e output of C-element becomes logically
high (low) when both the inputs are logically high (low);
otherwise it keeps its previous logic value. ere are two
types of C-elements used in SI circuits: static C-element and
dynamic C-element. e static version of C-element promises
that the information inside it can be stored for unbounded
periods. However, dynamic versions of C-element provide
gains in terms of area, power, and delay [–]. Since the
circuits having high operating speed, low area, and power
consumption are preferred in modern days, we have chosen
SI circuits with dynamic C-elements instead of static ones.
Figure shows the STG for the CUT being considered.
Rising (falling) transitions on signals, indicated by + (−), are
shown in the STG. e dark circles along the arcs are called
tokens. e token indicates one of possibly a set of signals that
enable transition to re. If all input arcs for a signal transition
have tokens then that signal transition is said to be enabled.
For example, when signal in goes high (denoted by in+)and
out goes high (denoted by out+), only then out +transition
can take place. Upon ring out +, a token is placed on each
of its outgoing arcs, thus enabling in−.Notethatout −is
enabled aer out+and in +.
In this paper, we have considered SI circuits that contain
C-elements (we assumed dynamic version) and logic gates.
For the logic gates, the most popular fault model is the
stuck-at fault model, which is at the gate level. However,
C1
C2
5
6
10
11
12
13
4
2
1
38
7
9
B
A
B
A
Rin
Ain
Aout
Rout
F : Example of speed independent asynchronous CUT.
n1
p1
p2
n2
n3
p3
A
B
C
V
dd
F : Transistor diagram of dynamic C-element.
for the C-elements stuck-on and stuck-o faults for each
transistor are an accepted fault model []. So we have chosen
a mixed gate/transistor level description for modeling the
faults. To illustrate fault modeling at both C-elements and
basic gates, we consider the circuit example from []which
is shown in Figure .
3.1.1. STG Based Modeling. In this work, we model single
stuck-at faults in the gates and transistors (for the C-
elements) and map them to STGs of the circuit. For the
analysis, the signals attached to the inputs and of the C-
elements are also indicated in the gate level circuit diagram
of Figure . Now, we consider some of these faults (one at
a time), analyze their eects, and nally modify the STG to
model the faults.
VLSI Design
Aout−
Rin+
Rin−
Aout+
Rout−
Ain−
Rout+
Ain+
F : Signal transition graph of sample circuit.
Consider the C-element C of Figure and refer to
transistor level circuit of Figure . e C-element C has out
and in as inputs and out as output. If the transistor 1 has
a stuck-on fault, this leads to error in the circuit that it needs
to wait for only 2 to be enabled to generate output. When 2
turns on, then a path to ground via 1 and 2gets established,
which makes 3 on and 3 o, making C high. So C has to
wait only for 2 (i.e., in+which corresponds to input of
C to become ) to turn on and change the output. In other
words, it has to wait for only in +(and not also for out+,
which is the requirement under normal condition) before it
can generate out+.us,thefaultin1 leads to premature
ring of the out+transition. We represent this by including
atokenonthearcconnectingout +to out+. Availability of
this token will enable out+to re as soon as in+arrives,
without waiting for out+. is token is denoted by a “”
shown on the arc in Figure .
Now, consider C-element C producing output out,with
transistor 1 having stuck-on fault. As 1 is on, the gate has to
wait for 2 to turn on before it can change the output. When
2 turns on (by virtue of =0) then there is no path to
ground as 2 is o, which makes 3 o and 3 on, making C
low. Here, C has to wait for the input =0to generate out−.
Referring to Figure ,forto become , we need either out
tobecome(thesameasin becoming ) or in to become
. us, as soon as we have either out+or in+,out−would
re. It may be noted that, under normal condition, for out−
to re, we also require =0,whichmandatesbothout+and
in+. is failure condition is indicated in the STG by adding
a“”totheinputarcsofout−,whichisshowninFigure .
To elabor ate, Figure (a) (Figure (b))showsthatout−can
be red as soon as in+(out +) res and does not wait for
out+(in +).
As the third fault, let C have stuck-on fault at 2.e
stuck-on fault at 2 enforces the circuit to wait only for 1 to
Aout−
Rin+
Rin−
Aout+
Rout−
Ain−
Rout+
Ain+
1
F:STGlevelmodelofstuck-onfault1 of C [].
be enabled for generating output out+.As1 is connected to
input ,whichislogicalORingofout−and in −, transition
out+can re aer out−or in −(without requiring to
wait for in+). is premature ring of transition out +is
indicated in the STG by adding a “” to in+,whichisshown
in Figure .
For the gates, stuck-at- and stuck-at- faults are consid-
ered at their inputs and output nets. Let Line of the AND
gate from Figure have a stuck-at- fault. is makes Line
stuck-at- fault. As Line is connected to the input of the
C-element C, we have transistor 2 on and transistor 2 o.
Note that as 2 is always o, there is no path to the ground. So
the output out can never become because 3can never turn
on. In other words, we will never have the out +transition.
isisindicatedbyaddinga“”ontheoutputarcsofout+
in Figure .
If Line gets stuck at , this will lead to Lines and being
stuck at , further leading to Line being stuck at . As Line
isconnectedtotheinputoftheC-element,wewillhave
the fault manifestation similar to the case of Line stuck at .
Now, we consider a stuck-at- fault at Line . As this line is
connected to the input of the C-element C, it will lead to
output out neverbecoming.eeectisshownbyadding
a“”totheoutputarcsofout+in Figure .
Now, we consider an example of a redundant fault; that
is,nologicaldierenceisobservedintheoperationofthe
circuitaerfault.Aninstanceofsuchafaultis1 stuck-on
fault in C. is fault enforces the circuit to wait only for 2
to be enabled (i.e., to be ) for generating output out+.As
2 is connected to input , which is logical ANDing of in+,
out−,andin −,out+can re only aer three transitions,
namely, in +and out−and in −re. It may be noted that
out−and in −also imply that input (connected to 1)of
C is , which in turn implies condition for 1.Asfaultand
normal condition both imply 1 to be on, stuck-on fault at 1
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1
Aout−
Rin+
Rin−
Aout+
Rout−
Ain−
Rout+
Ain+
(a) 𝑅out−does not wait for 𝐴out+
1
Aout−
Rin+
Rin−
Aout+
Rout−
Ain−
Rout+
Ain+
(b) 𝑅out−does not wait for 𝐴in+
F : STG level model of stuck-on fault in 1 of C [].
1
Aout−
Rin+
Rin−
Aout+
Rout−
Ain−
Rout+
Ain+
F:STGlevelmodelofstuck-onfault2 of C [].
of C does not generate any behavioral dierence. Obviously,
such faults cannot be detected and under the single stuck-at
fault assumption do not cause signicant reliability issues.
For the fault model considered, the total number of faults
in a SI circuit having dynamic C-elements is equal to
times the number of C-elements (each C-element consists
of transistors and each transistor can have stuck-on and
stuck-o faults) plus twice the number of I/O lines of the
gates (each line has either stuck-at- or stuck-at- fault).
0
0
Aout−
Rin+
Rin−
Aout+
Rout−
Ain−
Rout+
Ain+
F : STG level model of stuck-at- fault in Line .
Sothenumberoffaultsincaseofthecircuitconsideredin
Figure is not too small and listing them all would make a
tabular representation long. So a partial list of faults and their
eectsontheSTGisgiveninTa b l e .
3.1.2. State Graph Based Fault Modeling and FD-Transitions.
As already discussed, the rst step of DES based OLT
design is to generate the normal and faulty models. For SI
circuits, rst the STGs under normal and faulty conditions are
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00
Aout−
Rin+
Rin−
Aout+
Rout−
Ain−
Rout+
Ain+
F : STG level model of stuck-at- fault in Line .
obtained and then converted into state based models. In this
subsection, we explain the concept using the example circuit
of Figure under normal condition and two faults, namely,
stuck-on fault in 1 of C and stuck-on fault in 1 of C.
e state based DES model for the normal circuit is
shown in Figure .Itmaybenotedthatinthecircuitthere
are I/O signals, namely, in,out ,in ,andout .Inthe
DES model corresponding to each signal, there is a discrete
variable: V1=
in,V2=
out,V3=
in,V4=
out
which assumes values from the set {0,1}. e set of states
are 0 to 13 and 0 is the initial state. State mappings and
transitions are shown in Figure ; for example, state 0 maps
variables in,out,in,out to 1,1,0,0.Instates0 and
1 mappings are 1,1,0,0and 1,1,0,1,respectively.So
transition from 0 to 1 changes out from to ; this is
indicated by transition out+.Now,ifwelookattheSTGfor
the normal circuit in Figure we note that out +can re if
in+and out +have a token (i.e., in =1and out =1). In
state 0 as in =1and out =1,out+can re. Similarly, the
wholeDEScanbeconstructed.
e state based DES model for the circuit under 1 stuck-
on fault in C is shown in Figure . e set of states are
0to 13 and 0is the initial state. e transitions
andstatemappingareshowninthegure.Asdiscussedin
the previous subsection, 1 stuck-on fault in C results in
premature ring of out +(i.e., it need not wait for out+
and can re only if in +holds).Ifweobservethefailure
DES model in Figure ,wenotethattherearetwodotted
transitions, which correspond to the failure condition, that is,
premature ring of out +. One dotted transition is between
11 and 6.Itmaybenotedthatin11 we have in =1,
out =0,in =1,andout =0,whereeventhough
out+is not enabled, because in+is enabled, out+res. A
similar premature ring of out +occurs between 13 and
T:ApartiallistoffaultsandtheireectsonSTG.
Fault type Eect of fault on the transitions
Tra n sist o r 1 stuck-on fault
for C
out+ can only be red aer in +,
out−,andin−(the same as
normal condition)
Tra n sist o r 2 stuck-on fault
for C
out+ can be red aer either out−
or in−
Tra n sist o r 1 stuck-on fault
for C
out−can be red aer either out+
or in+
Tra n sist o r 2 stuck-on fault
for C
out−can only be red aer out+
and in+
Tra n sist o r 1 stuck-on fault
for C out+ can be red aer in+
Tra n sist o r 2 stuck-on fault
for C out+ can be red aer out+
Tra n sist o r 1 stuck-on fault
for C out−can be red aer in−
Tra n sist o r 2 stuck-on fault
for C out−can be red aer out−
Tra n sist o r 1 stuck-o fault
for C All arcs from out +arealways
Tra n sist o r 2 stuck-o fault
for C All arcs from out +arealways
Tra n sist o r 1 stuck-o fault
for C All arcs from out −are always
Tra n sist o r 2 stuck-o fault
for C All arcs from out −are always
Tra n sist o r 1 stuck-o fault
for C All arcs from out +arealways
Tra n sist o r 2 stuck-o fault
for C All arcs from out +arealways
Tra n sist o r 1 stuck-o fault
for C All arcs from out −are always
Tra n sist o r 2 stuck-o fault
for C All arcs from out −are always
Tra n sist o r 3 stuck-on fault
for C
Tra n sist o r 3 stuck-o fault
for C
All arcs from out +arealways
Tra n sist o r 3 stuck-on fault
for C
Tra n sist o r 3 stuck-o fault
for C
All arcs from out −are always
Tra n sist o r 3 stuck-on fault
for C
Tra n sist o r 3 stuck-o fault
for C
All arcs from out −are always
Tra n sist o r 3 stuck-on fault
for C
Tra n sist o r 3 stuck-o fault
for C
All arcs from out +arealways
Stuck-at- fault at Line or
Line or Line
Stuck-at- fault at Line or
Line
Stuck-at- fault at Line or
Line
All arcs from out +arealways
VLSI Design
T : C on t i nued.
Fault type Eect of fault on the transitions
Stuck-at- fault at Line
and Line All arcs from out +arealways
Stuck-at- fault at Line or
Line
Stuck-at- fault at Line or
Line
Stuck-at- fault at Line or
Line
All arcs from out −are always
Stuck-at- fault at Line All arcs from out +arealwaysand
all arcs from out +arealways
Stuck-at- fault at Line All arcs from out −are always and
all arcs from out −are always
Stuck-at- at Line All arcs from out −are always and
all arcs from out +arealways
Stuck-at- fault at Line All arcs from out+arealwaysand
all arcs from out −are always
Stuck-at- fault at Line
or Line All arcs from out +arealways
Stuck-at- fault at Line or
Line All arcs from out −are always
1010
1011
0001
1101
0101
1110
1111
0111
0011
0010
1000
0000
1001
X0
1100
X1
X4
X2
X5 X6
X7 X8
X10
X9
X11 X12
X13
X3
Aout−
Aout−
Rin+
Rin+
Rin−
Rin−
Rin−
Rin−
Aout+
Aout+
Rout−
Rout−
Ain−
Ain−
Ain−
Ain−
Rout+
Ain+
Ain+
Ain+
F : DES model for normal circuit (STG of Figure ).
8.So,forthefault1 stuck-on fault in C, there are two
FD-transitions, namely, 11,6 and 13,8.
e state based DES model for the circuit under 1 stuck-
on fault in C is shown in Figure . e set of states are 0to
13 and 0is the initial state. As discussed in the previous
subsection, 1 stuck-on fault in C results in premature ring
of out−triggered by either in+or out+. is is captured
bythedottedtransitions 2, 11 and 1, 8 in
failure DES model in Figure . e transition 2,11
represents ring of out−by in+in spite of out+not being
1010
1011
0001
1101
0101
1110
1111
0111
0011
0010
1000
0000
1001
1100
X1X2
X0
X3
X4
X5X6
X7X8
X9X10
X11 X12
X13
Aout−
Aout−
Rin+
Rin+
Rin−
Rin−
Rin−
Rin−
Aout+
Aout+
Aout+
Aout+
Rout−
Rout−
Ain−
Ain−
Ain−
Ain−
Rout+
Ain+
Ain+
Ain+
F : DES model for circuit with 1 stuck-on fault in C (STG
of Figure ).
1010
1011
0001
1101
0101
1110
1111
0111
0011
0010
1000
0000
1001
1100
X1
X0
X2
X3
X4
X5X 6
X7X 8
X9X 10
X11 X 12
X13
Aout−
Aout−
Rin+
Rin+
Rin−
Rin−
Rin−
Rin−
Aout+
Aout+
Rout−
Rout−
Rout−
Rout−
Ain−
Ain−
Ain−
Ain−
Rout+
Ain+
Ain+
Ain+
F : DES model for circuit with 1 stuck-on fault in C (STGs
of Figure ).
enabled and the transition 1, 8 represents ring of
out−by out +in spite of in+not being enabled. us, for
this fault there are two FD-transitions, namely, 2, 11
and 1, 8.
e set of FD-transitions is shown in Table .
VLSI Design
T : FD-transitions.
FD-transitions Start
state
Final
state Eect
Premature re of out+
before in+(byin−)
Premature re of out+
before in+(byin−)
Premature re of out −
before out+(byin +)
Premature re of out +
before out+(byin+)
Premature re of out+
before out+(byin+)
Premature re of out −
before out−(by in−)
Premature re of out−
before out−(by in−)
Premature re of out −
before in−(by out−)
Premature re of out−
before in−(by out−)
Premature re of out −
before in+(byout +)
In the next section, we will discuss the procedure for
design of the DES detector from FD-transitions and its
synthesis as a SI circuit.
4. DES Detector Based Online Tester
A DES detector is basically a state estimator which predicts
whether the Circuit Under Test (CUT) traverses through
normal or faulty states/transitions. Broadly speaking, the
detector is constructed using transitions which can manifest
the fault eects. In other words, such a transition is a faulty
transition for which there is no corresponding equivalent
normal transition. As already mentioned, we call such transi-
tions failure detecting transitions (i.e., FD-transitions). In the
circuit under consideration, comparing the normal (Figure )
and 1 stuck-on fault at C DES models (Figure ), we may
note that there are two transitions (dotted) 11,6 and
13,8 which manifest the fault eect. Corresponding
to these transitions, there are no equivalent transitions in the
normal model. ese two transitions are FD-transitions for
thefaultandareusedinDESdetectorconstruction.
If the CUT is a synchronous circuit then obviously the
online tester is also a synchronous circuit that can be designed
from the FD-transitions using straightforward FSM synthesis
philosophy [,]. e detector FSM has three classes of
states, namely, initial, intermediate, and nal. e detector
measures the I/O signals of the CUT (i.e., variables) to
determine whether the following happens.
On startup the detector is in its initial state and it
checks whether the CUT is in the initial state of any FD-
transition. For example, if we consider only two faults in
the circuit under consideration, stuck-on fault in 1 of C
and stuck-on fault in 1 of C, then the FD-transition set
is {11,6,13, 8, 2, 11}.Sointheinitial
state the detector checks whether the signals in ,out,in ,
and out are 1,0,1,and0or , , , and or , , , and . If so,
the detector moves to an intermediate state (in the next clock
edge) corresponding to the value matched. For each of the
FD-transitions, there is a corresponding intermediate state
in the detector. For example, if in,out,in,andout are
measured to be , , , and in the initial state of the detector,
the detector moves to the intermediate state corresponding
to FD-transition 11,6.However,ifthesignalsdonot
match initial state of any FD-transition the detector loops in
the initial state. In the intermediate state whether the values
of the signals of the CUT match with the nal state of the
corresponding FD-transition is checked; if so, the fault is
detected and the detector moves to the nal state and is
deadlocked there. Otherwise, it moves to the initial state.
Continuing with the example, if the values of in,out,in ,
and out are,,,andfromtheintermediatestate,FD-
transition 11, 6 is detected (i.e., stuck-on fault in 1 of
C) and detector moves to nal state in the next clock edge.
Otherwise, if in,out,in,andout are , , , and then
CUT is normal and the detector moves to the initial state.
e above mentioned philosophy of constructing the
detector and then synthesizing it into a synchronous system
is widely used in the DES theory [] and has been applied for
OLT of synchronous circuits [,]. Obviously, if the CUT is
an asynchronous circuit and so must be the detector circuit.
However, it may be noted that the same philosophy cannot be
directly used in the case of SI circuits. e reason is that the
FSM of the detector designed above has liveness issue in the
nalstateandhascompletestatecoding(CSC)violationsin
the intermediate states.
Now we propose a new technique for detector design
which can be synthesized as a SI circuit. e detector is
designed as state graph model which is live and has complete
state encoding, that ensures its synthesizability as a SI circuit.
Before formalizing the algorithm for the design of the state
graph of the detector, we rst introduce the basic philosophy
of its working using the examples from the previous section.
An FD-transition in SI circuit design paradigm can be
stated as, “under failure, a signal canchangeinthepresence
of signals 1,2,...,,(1≤)whichisnotpossible
under normal condition.” For example, in the case of 1 of
C stuck-on fault, 11,6 is an FD-transition which
changes signal out from to (i.e., out+) and the other
signals are in =1,out =0,andin =1(Figure ). It
may be noted that in normal condition for changing out
from to we need in =1,out =1,andin =0
(Figure ). Comparing with the faulty condition we may state
that, “under 1 of C stuck-on fault, signal out can change
from to in presence of signals in =1,out =0,and
in =1which is not possible under normal condition.” So,
to detect whether FD-transition 11,6 has occurred,
the detector needs to tap lines out,in ,andout (in is not
required to be monitored as its value is same under normal
and faulty case) of the CUT and determine whether out+
has red and at that time whether out =0or in =1or
both; if so, a status output line is made . For optimization
VLSI Design
of the detector in terms of number of states, tap lines, and
so forth, without loss of fault detection capability, we may
consider checking out +in presence of either out =0or
in =1but not both. If we consider the other FD-transition
13,8 for the fault, it can be detected by checking
whether out+has red and at that time whether out =0;
in and in are not required to be monitored as their values
are the same under normal and faulty case. So, it may be
stated that to detect the fault by FD-transitions 11,6
and 13,8 we need to check whether out +has red
and at that time whether out =0. e design and ow of the
detector for these two FD-transitions are as follows:
(1) e state encoding tuple is out,out,.e
initial state of the detector 0is encoded as 100.e
rst two bits represent the complement of out =
0and out =1, that is, complement of value of
out in state 11 and complement of change of out
by the FD-transition. e third bit represents
output of the detector which is until FD-transition
is detected.
(2) e detector waits for signal out to become and
if so it moves to state 1say, which is encoded as
000.However,fromstate0,ifout becomes , FD-
transition cannot be detected because this is normal
situation (state 0 in Figure )whereout+res
when out =1; detector moves to state 5having
encoding 110.Whenout becomes in state 5,the
detector moves back to 0from where it again waits
to detect whether the FD-transition occurs.
(3) From state 1the following may happen:
(a)If out becomes , then FD-transition cannot be
detected and so the detector moves back to 0.
(b)If out becomes , then FD-transition and hence
fault are detected. e detector moves to state 2
having encoding 010. Following that detector
makes output high and moves to state 3
with encoding 011.
Once line is , that is, fault is detected
online, the system should switch to an alterna-
tive backup circuit, as under the single stuck-at
fault model faults are assumed to be permanent
[]. By that logic, the detector should stop or
loop in 3indenitely; however, it would lead to
deadlock and is nonsynthesizable as a SI circuit.
To avoid this deadlock, a simple modication
is made in the detector state graph without
aecting the fault detection performance. We
wait at state 3for any signal to change (i.e., out
from to or out from to ) and we move to
state 4;letusselectout for this purpose. State
encoding of 4is 111.Fromstate4we have a
transition to state 3on change of out from to
.
Figure illustrates the state graph for detecting 1 stuck-
onfaultatCbyFD-transitions11, 6 and 13, 8.
100 000 010 111
011
110
d0d1d2d3d4
d5
Status+
Aout−
Aout+
Aout+
Rout−
Rout−
Rout+
Rout+
State encoding tuple ⟨Rout,Aout, status⟩
F : State graph for detecting FD-transitions 11, 6 and
13,8.
In similar way we can design detectors for the other FD-
transitions shown in Table .However,itmaybenotedthat
dierent circuits may be required for the other FD-transitions
because merging all FD-transitions in a single detector state
graph will lead to CSC problems. As shown in the example
above, some FD-transitions can be merged into a single state
graph maintaining CSC. Figures – illustrate the SGs for all
the FD-transitions shown in Tab l e . Also, the FD-transitions
which could be merged are mentioned in the gures.
Before discussing the algorithm for generating the detec-
tor for a set of FD-transitions we introduce the notion of
compatible FD-transitions.
Denition 8 (compatible FD-transitions). Two FD-transi-
tions 1=
1,1+and 2=
2,2+are compati-
ble if the following holds:
(i) If 1 is the signal change by 1and 2 is the signal
change by 2,then1 isthesameas2.Inother
words, signal change by both FD-transitions is the
same.
(ii) Let 1⊆(for FD-transition 1=
1,1+)be
the set of variables whose values at 1are dierent
compared to state(s) ,where is any state under
normal condition (normal DES) from which 1 is the
signal change. Similarly, the set 2⊆is calculated
for FD-transition 2=
2,2+.en,1∩
2 =. In other words, there exists at least one
signal(i.e.,avariable)whosevalueisthesamein
initial state of both FD-transitions and that is dierent
compared to the initial state(s) of the corresponding
transition(s) under normal condition.
For example, consider two FD-transitions 11,6
(=
1,say)and13, 8 (=
2, say). We calculate 1
for 1as follows. e value of variables at initial state 11
is {in =1,
out =0,
in =1,
out =0}.esignal
change for =
1is out+.Wegettwostates(0 = {in =
1,out =1,
in =0,
out =0}and 2 = {in =1,
out =
1,in =1,
out =0}) in normal condition from which the
signal change out+occurs. us, 1={
out(= 0)} because
out istheonlyvariablethatisdierentin11 compared to
normal states 0 and 2.Similarly,wecalculate2for 2
as 2={
out(= 0)}.Since1∩2 =={
out(= 0)},thus,
these two transitions are compatible and can be merged (as
shown in state graph of Figure ).
Algorithm 9. Algorithm for construction of detectors given
the set of FD-transitions.
VLSI Design
100 000 010 111
011
110
d0d1d2d3d4
d5
Status+Rin +
Rin+
Rin−
Rin−
Rout−
Rout+
Rout+
State encoding tuple ⟨Rin,R
out,status⟩
F : State graph for detecting FD-transitions–Sl. numbers
and of Tabl e .
110 010 000 101
001
100
d0d1d2d3d4
d5
Status+
Aout−
Aout−
Aout+
Aout+
Rout−
Rout−
Rout+
State encoding tuple ⟨Aout ,R
out,status⟩
F : State graph for detecting FD-transition–Sl. numbers of
Tabl e .
010 110 100 001
101
000
d0d1d2d3d4
d5
Status+
Aout −
Aout −Aout +
Rout −
Rout −
Rout +
Rout +
State encoding tuple ⟨Rout,A
out,status⟩
F : State graph for detecting FD-transitions–Sl. numbers
and of Tabl e .
010 110 100 001
101
000
d0d1d2d3d4
d5
Status+
Aout−
Aout−
Rin+
Rin+
Rin−
Rin−
Aout+
State encoding tuple ⟨Rin,Aout,status⟩
F : State graph for detecting FD-transitions–Sl. numbers
and of Tabl e .
Input.IFD is set of FD-transitions.
Output. Detectors for determining occurrence of FD-transi-
tions are as follows:
() Partition IFD into equivalence classes. Let I1FD,
I2FD,...,IFD be the sets generated.
() For each of these sets (IFD,(1 ≤ ≤ )), generate a
detector state graph using Step (3) to Step (10).
() is the signal changed by ∈IFD and is any
signal whose value is the same in initial states of all
∈IFD.Further,signalis dierent in the initial
state of the corresponding normal transition which
also makes the same change in .
() Let state encoding of the detector be the tuple
,,.
() Create the initial state 0. e values of the variables
in 0are as follows: (i) in the tuple for 0is com-
plement of the value of the variable in (),
∈IFD, (ii) in the tuple for 0is complement of
the value of the variable aer its change by ∈IFD,
and (iii) in 0is .
() Create state 1, with transition from 0to 1labeled
as + (−)ifvalueofin 0is (). Also, create
a transition from 1to 0labeled with inverse of
the signal change as in transition from 0to 1.
Accordingly, encode state 1.
() Create state 2, with transition from 1to 2labeled as
+ (−)ifvalueofin 1is (1). Accordingly, encode
state 2.
() Create state 3, with transition from 2to 3labeled
as +. Accordingly, encode state 3.
() Create state 4, with transition from 3to 4labeled
as + (−) if transition from 0to 1is − (+). Add
a transition from 4to 3with inverse of the signal
change as in transition from 3to 4. Accordingly,
encode state 4.
() Create state 5, with transition from 0to 5labeled
as + (−) if transition from 1to 2is + (−). Add
a transition from 5to 0with inverse of the signal
change as in transition from 0to 5. Accordingly,
encode state 4.
4.1. Circuit Synthesis for DES Detector. It is clear f rom the
construction of the state graphs of detectors that they have
complete state coding [,]andarelive.Sotheycanbe
synthesized as SI circuits using C-elements and logic gates by
applying standard asynchronous circuit synthesis procedures
[,].
Figure illustrates some snapshots regarding the steps
of synthesizing the state graph of the detector shown in
Figure using CAD tool Petrify []; Figure (a) is the
description of the state graph that is input to Petrify,
Figure (b) illustrates the output of Petrify showing CSC
and no liveness issues, and Figure (c) shows the equations
obtained from Petrify. e circuit schematic (of the DES
detector) that is synthesized for this state is shown in
Figure .
Now, we explain some details of the Petrify equations.
is a keyword of Petrify to represent all I/O
signals of the corresponding state graph. is the
keyword to represent the output signals of the state graph.
Each subsequent line (denoted by [0,1]...)representsagate
of the circuit in terms of the function it implements. In case
of the circuit of Figure , = out,out,
and = .eequations[0] =
out
out
and [1] = 0 represent the logic expressions of the internal
Gate and Gate , respectively. e equation [] =
[1]([0] + ) + [0] represents the output of the
circuit.
In similar way, all state graphs for the FD-transitions have
been synthesized into dierent circuits. en, the nal DES
detector circuit for CUT is constructed by simply ORing
VLSI Design
(a) State graph (b) Output of Petrify
(c) Output equations of Petrify
F : Screenshot showing the synthesis of DES detector from state graph using Petrify.
C
Logic 0
Status
1
2
3
4
5
6
7
Aout
Rout
F : DES detector circuit for state graph shown in Figure .
the outputs of these circuits. e output of the detector circuit
becomes high when output of at least one individual detector
becomes high, thereby detecting the fault.
5. Experimental Evaluation
To validate the ecacy of the scheme, we analyze the area
overheadratiooftheonlinetestercircuittothatofthecircuit
under test. Further, we also compare the overhead with other
techniques reported in the literature. In our experiments,
we have considered some standard SI benchmark circuits
[]. Further, for comparison, we have also implemented our
scheme on the circuits used in [].
e algorithm discussed in previous section is used to
design a CAD tool OLT-ASYN which generates detectors for
OLT given an asynchronous circuit specication. e design
procedure includes the following steps.
(i) First, the behavior description of the SI circuit is
represented using STG.
(ii) e STG representation of the SI circuit is converted
into its corresponding state graph using Petrify.
(iii) Using Petrify, the state graphs are implemented as SI
circuits using generalized C-element.
(iv) s-a- and s-a- faults are inserted in all the nets of the
gates and stuck-on and stuck-o faults are inserted in
the transistors of the C-elements of the circuit (one at
a time) and the corresponding faulty state graphs are
generated.
(v) FD-transitions are generated for all the faults using
the DES theory.
(vi) Using Algorithm state graphs of the detector(s) are
generated.
(vii) e state graphs are implemented as SI circuits using
generalized C-element implementation using Petrify.
Area overhead ratio of the online tester circuit to that of
the circuit under test is computed using the formula
Area overhead ratio
=Combined area of the Detector circuits
Area of the CUT .()
Area of gates and C-elements are considered in terms of
number of transistors used in their CMOS implementation.
VLSI Design
T : Fault coverage, area overhead ratio, and execution time for the online detector designed using the proposed approach.
CUT Number of gates Number of faults Fault coverage (%) Area overhead Execution (sec)∗
Circuit . .
Circuit . .
Circuit . .
Davidcells[] . .
Davidcells[] .
chu . .
alloc-outbound . .
sbuf-read-ctl . .
sbuf-send-ctl . .
ram-read-sbuf . .
∗Executed in AMD Phenom IIX Processor with GB RAM in Linux OS.
For example, a two-input NAND gate has four transistors
(two PMOS and two NMOS). Fault coverage is calculated as
ratio of number of faults detected by the tester to the total
number of faults.
Table shows the number of gates, number of faults,
fault coverage, area overhead ratio, and execution time of
theproposedapproachforthedierentSIcircuitsbeing
considered.
e rst three circuits in the table are simple examples
whosegateleveldesignsareshowninFigures,,and
.efourthandhcircuitshavebeenusedin[]. e
others are standard asynchronous benchmarks []whichare
complexintermsofarea,states,andsignalcomparedtorst
vecircuitsinthetable.
Broadlyspeaking,itcanbeobservedfromTa b l e that
area overhead decreases with the increase of the size of the
circuit. In [], Drineas and Makris have identied that the
area overhead ratio for partial replication based OLT for
stuck-at faults is approximately +1/,whereis the fraction
of test patterns incorporated in detector design (=1when
all FD-transitions are incorporated in detector design) and
is the number of state bits required for circuit representation
(i.e., proportion to circuit size). In this work, we have taken all
possible FD-transitions and the obtained area overhead ratio
acts (approximately) in accordance with the fact mentioned
above.
From the discussion in the last section regarding design
of the detector from the FD-transitions, it may appear that a
large number of such detectors may be required for complex
circuits. In the worst case, the number of detectors may be
equal to the number of FD-transitions. Further, in case of
large circuits as the number of nets and C-elements are high
the number of FD-transitions may be proportionally large.
However, interestingly, the experiments illustrated reverse
trends. Large circuits have larger number of possible stuck-at
faults; however, many of them are mapped to similar eects
andhencethesameFD-transitions;thiscanbeobservedfrom
Table for the running example. Further, using the principle
of compatible of FD-transitions, it was found that multiple
FD-transitions fall in the same clusters thereby resulting in
the fact that a single detector suces for more than one FD-
transition. To conclude, it was observed that a few detectors
a1
r1
a2
r2
F : Circuit .
c
Cc
a
b
F : Circuit .
are actually required to cover all the faults. To the best of
our knowledge, such facts regarding OLT of asynchronous
circuits were not reported in the literature.
It may be noted that percentage of fault coverage is more
than%inaverage.enumberoffaultsthatcouldnotbe
detectedwasfoundtoberedundant.
5.1. Mutex Approach to Testing. Now, we will discuss, in brief,
the Mutex approach for online testing proposed in []and
compare its area overhead ratio with our scheme. In [], the
scheme is demonstrated on the following specication of a
handshaking protocol:
+ → + → − → −. ()
Online testing is performed using checkers which verify that
sequencing of the signals as per the protocol is maintained;
VLSI Design
C
C
a
b
c
d
a
bc
d
F : Circuit .
that is, there is no premature or late ring of signals, no
signal is stuck-at-/stuck-at- fault, and so forth. All the
protocol signals are used as the input for the checker. e
checker has two functionalities, namely, self-checking and
online testing of the handshaking protocol. e signal “mode”
decides this selection. e block diagram of the checker is
given in Figure . A part of the checker circuit is shown in
Figure whichwillbeusedtopresentthebasicworkingof
thechecker.efullcircuitdiagramandfunctionalitycan
be found in []. As shown in Figure ,therearetwoMutex
components; one is used for the arbitration between − and
−, while the other is used to arbitrate between +,
11+,and11+; the details of the signals 11+ and
11+ are given below.
e initial state is (both req and ack are high). is
is guaranteed by the previous state. In the previous cycle of
operation, + occurs before +,whichsets11 = 1,
thus providing the appropriate initial condition for the given
cycle. e next signal change should be − (as per the
handshaking protocol). So, once − occurs, 11 signal is
set to (le Mutex), as signal is still high. As a result, the
checker goes to next state indicating no errors. If there is
an error in the protocol under test, then − precedes −,
and 11 is set to . is moves the checker along the fault
branch.
When the mode signal is set to logic , the three-input
arbiter (right Mutex in Figure ) is used to arbitrate +,
11+,and11+.isMutexisusedforself-testingofthe
checker.
e asynchronous circuit under test (which realizes the
above handshaking protocol) is implemented using David
cells []. e partial checker circuit illustrated in Figure
basically tests the handshake protocol between a pair of
David cells and performs self-checking. Along with the
partial circuit shown in Figure ,therearefourDavidcells
(not shown), which together test the handshaking protocol
(between a pair of David cells) and self-testing of the checker.
Among the two Mutex blocks and four David cells, half of
themareusedforhandshakingprotocolandtheotherhalfis
used for self-testing. e logic gates are shared resources for
both types of testing. In [], both the circuit under test and
Checker
req ack
Mode
Error
F : Block diagram of the checker.
Mutex
Mutex
Mode
Te r ro r
req
ack
gr11
ga11
ga11e
F : A part of the checker circuit [].
the checker circuity are implemented using David cells, using
the ow of converting a Petri net model to asynchronous
circuitsbasedonDavidcells[].
5.2. Comparison with the Mutex Approach. e proposed
DES based approach for online testing does not involve self-
testing of the detector. So, for comparison of area overhead
oftheproposedschemewith[], we require only half of
the resources used in []. Table shows area overhead ratio
of the checker (for online testing only) for two circuits
implementing handshaking protocols involving two and four
David cells, respectively. e table also reports the number
of David cells, Mutex elements, and logic gates involved in
the checker (for online testing). From Tables and (fourth
and h circuit), we can deduce that the area overhead
requirement for the Mutex method is higher compared to
that of the purposed scheme. e advantages of the proposed
method over the Mutex approach are as follows:
()eareaoverheadfortheonlinetestercircuitisless
as compared to that of the Mutex approach by about
%.
() ere is exibility to trade o area overhead, by
reducing fault coverage depending upon the testa-
bility requirements. Such exibility is not easy to be
achieved by the Mutex approach. It may be noted that
the proposed scheme veries that there are no stuck-
at faults while the Mutex approach veries a protocol.
Inparticular,itchecksforthecorrectsequencing
of the outputs. Fault coverage can be easily traded
o with area overhead in our approach, while it is
dicult to achieve something like “partial verication
of protocol,” avoiding checking certain incomplete
output sequences.
VLSI Design
T : Area ratio for the Mutex approach.
CUT Circuits for OLT
Area overhead
ratio for Mutex
method
David
cells
David cells + Mutex elements +
gates .
David
cells
David cells + Mutex elements +
gates .
() In the detector of the proposed scheme, there is no
dependency on Mutex elements. e Mutex element
itself can undergo a metastable state which needs to be
handled by the metastability detector, adding to area
overhead.
Inthiswork,wecouldnotcomparefaultcoverageof
our approach with the Mutex approach. e Mutex approach
veries online whether the output of the CUT follows the
specied handshaking protocol. So, the Mutex approach
basically follows functional testing. e scheme proposed
in our paper works on structural testing and hence fault
coverage can be given, while it is not possible for functional
testing.
It may be noted that the circuits considered in the Mutex-
based OLT scheme []weresimple.Forcomparisonwith
our scheme, we have done manual implementation of Mutex-
based tester design on those circuits.
6. Conclusion
In the present paper, a method for the online testing of SI
circuits has been proposed. We start by obtaining the STG
of the SI circuit under test using the tool Petrify. Aer that,
eects of stuck-at faults were modeled in the STGs. e
normal and faulty STGs were transformed into state graphs
and a DES detector was designed. e detector is capable
of determining, online, whether any of the modeled stuck-
at faults have occurred in the circuit. Finally, the detector
is synthesized as a SI circuit with C-elements which is to
be placed on chip. Several circuits were considered as case
study and area overhead ratio of the detector was studied
for these circuits. Results illustrated that area requirement
of the detector of the proposed scheme is less than that of
the Mutex approach []byabout%ontheaverage.Apart
from this, there are several other advantages of the proposed
approach, namely, independence of circuit functionality,
nonintrusiveness, liveness, and CSC of the detector to ensure
synthesizability and so forth.
e present scheme is applicable only for SI circuits
with dynamic implementation of C-elements. As a further
direction of research, this technique can be extended for other
types of asynchronous circuits like Delay Insensitive (DI)
circuits. It is required to verify whether this proposed DES
based OLT scheme can be directly applied for DI circuits or
some modications would be needed.
Also, in case of SI circuits, the present scheme can be
extended for static C-elements. OLT of static C-elements
may be comparatively more complex than that of dynamic
C-element because the dynamic C-element comprises less
number of transistors than that of static C-element. Addi-
tionally, in the present work, it is found that transistor stuck-
o or stuck-on faults lead to premature/nonoccurrence of a
transition in the STG. Whether similar fault manifestation
remains for static C-elements or there is a change needs to
be veried. Clearly further research is required to solve these
issues.
Conflict of Interests
e authors declare that there is no conict of interests
regarding the publication of this paper.
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