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Effort at Constructing Big Data Sensor Networks for Monitoring Greenhouse Gas Emission


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Global warming is an important environment issue rapidly becoming a part of popular culture. Scientists are 95–100% certain that it is primarily caused by increasing concentrations of greenhouse gases produced by human activities. Policies dealing with global warming depend on accurate and precise monitoring of the emissions of greenhouse gases. However, most greenhouse gas emissions management comes from bottom-up reporting, in which a company reports its energy use and other resource consumption metrics and maps out its carbon footprint. This is not a sufficient good way. A big data network of sensors has been constructed by us in Neimenggu province of China, which will gather huge amount of more accurate information on the dynamics of greenhouse gases in local areas and measure changes over time. Application specific instruction set processor is integrated in those sensor devices, to perform preliminary process of collected data. In this work, we have presented our efforts at constructing the big data sensor network for monitoring the greenhouse gases emission and mainly focused on building the ASIP’s retargetable compiler framework designed and dedicated for our sensor network.
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Research Article
Effort at Constructing Big Data Sensor Networks for
Monitoring Greenhouse Gas Emission
Haijing Tang,1Xu Yang,1and Yanjun Zhang2
1School of Soware, Beijing Institute of Technology, Beijing 100081, China
2School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China
Correspondence should be addressed to Xu Yang;
Received  March ; Accepted  June ; Published  July 
Academic Editor: Jes´
us Carretero
Copyright ©  Haijing Tang et al. is is an open access article distributed under the Creative Commons Attribution License,
which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Global warming is an important environment issue rapidly becoming a part of popular culture. Scientists are –% certain
that it is primarily caused by increasing concentrations of greenhouse gases produced by human activities. Policies dealing with
global warming depend on accurate and precise monitoring of the emissions of greenhouse gases. However, most greenhouse
gas emissions management comes from bottom-up reporting, in which a company reports its energy use and other resource
consumption metrics and maps out its carbon footprint. is is not a sucient good way. A big data network of sensors has been
constructed by us in Neimenggu province of China, which will gather huge amount of more accurate information on the dynamics
of greenhouse gases in local areas and measure changes over time. Application specic instruction set processor is integrated in
those sensor devices, to perform preliminary process of collected data. In this work, we have presented our eorts at constructing
the big data sensor network for monitoring the greenhouse gases emission and mainly focused on building the ASIP’s retargetable
compiler framework designed and dedicated for our sensor network.
1. Introduction
Since the early th century, Earths mean surface tem-
perature has increased by about .C(.
F), with about
two-thirdsoftheincreaseoccurringsince[]. Global
warming is an important environment issue which is rapidly
becoming a part of popular culture []. Warming of the
climate system is unequivocal, and scientists are –% cer-
tain that it is primarily caused by increasing concentrations
of greenhouse gases produced by human activities such as
the burning of fossil fuels and deforestation. ese ndings
are recognized by the national science academies of all major
industrialized nations.
Proposed policy responses to global warming include
mitigation by emissions reduction, adaptation to its eects,
and possible future geoengineering. Most countries are par-
ties to the United Nations Framework Convention on Climate
Change (UNFCCC), whose ultimate objective is to pre-
vent dangerous anthropogenic (i.e., human-induced) climate
Parties to the UNFCCC have adopted a range of policies
designed to reduce greenhouse gas emissions and to assist
in adaptation to global warming. ey have also agreed that
deep cuts in emissions are required and that future global
warming should be limited to below .C (.F) relative to
the preindustrial level. However, reports published in 
by the United Nations Environment Programme and the
International Energy Agency suggest that eorts as of the
early st century to reduce emissions may be inadequate to
meet the UNFCCC’s Ctarget.
China has been one of the earliest members of UNFCCC
idly and, even with policies adopted by China, are expected
to rise until at least . e emissions growth is driven
by Chinas rapid economic and industrial growth and its re-
liance on fossil fuels despite measures to raise the shares
of nonfossil energy sources. In response to the UNFCCC
process investigating the technical issues surrounding the
ability to reduce greenhouse gas emissions in developing
countries, over the past two decades, strong government
Hindawi Publishing Corporation
International Journal of Distributed Sensor Networks
Volume 2014, Article ID 619608, 7 pages
International Journal of Distributed Sensor Networks
directives and investments have dramatically reduced the
energy and greenhouse gas intensities of Chinas economy [].
Policies dealing with global warming depend on accurate
and precise monitoring of the emissions of greenhouse gases
[,]. However, most greenhouse gas emissions management
comes from bottom-up reporting, in which a company
reports its energy use and other resource consumption met-
good way to monitor the greenhouse gases emission.
So it is essential to construct a network of sensors to
monitor the emissions of greenhouse gases. us it can
provide another layer of top-down data that can conrm,
supplement, or contradict reporting from companies.
We have constructed a big data network of sensors in
Neimenggu province of China. is network of sensors will
gather huge amount of more accurate information on the
dynamics of greenhouse gases in local areas and measure
all of the greenhouse gas monitoring sensor equipment is
designed by us.
is network will help us to collect increasing amounts
of data from around the grasslands and forest in Neimenggu
province. Such a province level greenhouse gas network
would collect massive amounts of real-time emissions data
about atmospheric carbon dioxide and methane emissions
(greenhouse gases that are contributing to climate change)
from locations throughout Neimenggu. e data would
enable us to monitor specic areas that are contributing a
high amount of emissions and watch those areas over time for
growth or improvement and will enable us to further rene
our scientic studies on where greenhouse gases originate,
how they circulate around our atmosphere, and how they
move from one area to another.
e sensor stations will be linked via data connections
and the data will be processed preliminarily on those sensor
devices and then sent to the data center, so researchers
can use tools to further analyze the data and draw trends
and information from it. Application Specic Instruction
Set Processor (ASIP) is integrated in the sensor device, to
perform preliminary process of collected data.
the big data sensor network for monitoring the greenhouse
gases emission and mainly focused on building the ASIP’s
retargetable compiler framework designed and dedicated for
our sensor network, which is based on the open resource
compiler (ORC).
e following of this paper is organized as follows:
Section  will discuss some background content; in Section ,
the architecture of our ASIP is described, while the detail
of our retargetable compiler framework is presented in
Section ;Section  talks about related works, while experi-
mental result is shown in Section ;andnallytheconclusion
is given in Section .
2. Background
2.1. Application Specic Instruction Set Processor. An Applica-
tion Specic Instruction Set Processor (ASIP) is a processor
designed for one particular application, or a set of specic
applications. An ASIP exploits characteristics of various
pieces of hardware to meet the desired performance, cost,
and power requirements of specic applications. ASIPs are
a balanced solution between two extremes: Application Spe-
cic Integrated Circuits (ASICs) and General Programmable
Processors [].SinceanASICisspecicallydesignedfor
one behavior, it is dicult to make any change at a later stage.
In such a situation, the ASIPs oer the required exibility at
lower cost than General Programmable Processors [].
According to Liem et al. [], generally, ASIP design can
be divided into ve main steps as follows (Figure  []).
() Application Analysis. Applications are analyzed to get
the desired characteristics/requirements which can
guide the hardware synthesis as well as instruction
set generation. Analyzed information is stored in
some suitable intermediate format for usage in the
subsequent steps.
() Architectural Design Space Exploration. Performance
of possible architectures is estimated, using output
of step  as well as the given design constraints,
and suitable architecture satisfying performance and
power constraints and having minimum hardware
cost is selected.
() Instruction Set Generation. Instruction set is gen-
erated for that particular application and for the
architecture selected. is will be used during the
code synthesis and hardware synthesis steps.
() Code Synthesis. Compiler generator or retargetable
code generator is used to synthesis code for the
particular application or for a set of applications.
() Hardware Synthesis. Hardware is synthesized using
the ASIP architectural template and instruction set
architecture starting from a description in VHDL/
VERILOG using standard tools.
2.2. Open Resource Compiler (ORC). Open resource com-
piler is developed initially for Itanium architecture. It uses
WHIRL as intermediate language, and the using of WHIRL
enables ORC to support dierent high-level languages and
ASIP targets. e frontend of ORC translates dierent kinds
of high-level language into WHIRL and the backend of
ORC processes WHIRL to generate target codes. e using
of WHIRL and the architecture of ORC make it possible
that only the backend of ORC needs to be retargeted when
porting ORC to an ASIP architecture. However, the backend
of ORC is still very sophisticated and is comprised of
several phases including code generator (CG) and some
optimization components, such as interprocedural analyzer
and optimizer (IPA), loop-nest optimizer (LNO), and global
scalar optimizer (WOPT).
Compilation can be viewed as a process of gradual
transition from the high-level language constructs to the low-
level machine instructions, so WHIRL has several levels, as
shown in Figure . e closer it is to the source high-level
language, the higher its level is. And the more it resembles the
International Journal of Distributed Sensor Networks
Application(s) and
design constraints
Application analysis
Architectural design
space exploration
Instruction set
Code synthesis Hardware synthesis
Object code Processor
F : Flow diagram of ASIP design methodology.
machine instructions, the lower its level is. When compiling
moves on, WHIRL is down in its level. In WHIRL, source
codes are organized as a tree, aer being processed by the
frontend of ORC. And every node of this tree is called an
op,” which represents an operation. Every op has some elds
that store the information of that op, such as operate code,
and operand. Several ops can be assembled into a “bb,” which
represents a basic block that is a combination of several
operations. Several “bbs” can be assembled into a “region,
ORC has some predened optimization levels, named
as O, O, O, and so on. O level is the lowest level.
Under this level, ORC only goes through the basic phases
when compiling source code, such as code selection, local
schedule, local register allocation, and code emission, and has
no optimization. In O and O levels, some optimizations
like LNO, IPA, and WOPT are included in the compilation
3. Architecture of the Designed ASIP
A Register-File Connected Clustered ASIP architecture has
been developed by us, to be used in our sensor devices. And
a retargetable compiler framework has been generated based
on ORC, to support this new ASIP architecture.
One example of this ASIP architecture is shown in
Figure . ere are eight function units, which are grouped
into four clusters. Each cluster has its own local register le
which is named A, B, C, and D, respectively []. And all
clusters share a global register le named G. Both the local
register le and the global register le contain  registers with
width of  bits []. In this architecture, each function unit
can only access its corresponding local register le through
its own access port. However, all the function units can access
the global register le, and so comes the name Register-File
Connected. And the two function units in the same cluster
can access the global register le by dierent access ports [].
ere are four types of function units in this architecture.
ey are arithmetic and logic unit (AL), arithmetic and
branch unit (AB), multiplication unit (MP), and load and
store unit (LS). Function unit AL can be used to perform
most of the arithmetic and logic operations; function unit AB
is mainly used to execute branch operations and it can also
perform some arithmetic operations; function unit MP can
only be used to perform multiplication operations; and the
main function of LS is to load/store data from/to memory. In
order to achieve high performance, each type of function unit
is duplicated in this architecture [].
e main goal of grouping these function units is to
reduce the communication between dierent clusters; that is,
it is required that the results of one function unit are mostly
consumed by the other function unit in the same cluster [].
4. The Retargetable Compiler Framework
ASIP cannot work well without compiler’s support and
compiler needs to know the necessary hardware information
to work well. However, ASIP architectures can be various. If
the designer has to develop compiler for each dierent ASIP
architecture, the work amount will be huge. So, retargetable
compiler is the inevitable choice.
ORC has some advantages to be a footstone of a retar-
getable compiler. In ORC, all the hardware information is
grouped in the machine description les, including oper-
ate code information, operate attribute information, reg-
ister information, operand information, and function unit
information. So, when porting ORC to dierent hardware
architecture, only the hardware information in the machine
description les needs to be changed.
We have modied the information about the function
units, the information about the registers, the information
about the operation, the information about the operand
types in this architecture, and some other information, in
the machine description les, to make ORC suit our ASIP
In the machine description les, the registers in our ASIP
architecture are classied into ve register subclasses under
the integer register class dened initially in ORC. Also, the
attributes of each kind of register have to be dened. For
example, we dened  registers of attribute “callee” and 
registers of attribute “caller” in both local register le and
global register le.
e ow of the backend of ORC under optimization
level O only is composed of the code generation part
which includes  main phases, which are code selection,
local schedule, local register allocation, and code emission,
International Journal of Distributed Sensor Networks
C/C++, Java,
F90, F77
Very high
Very low
Target code
standalone inliner
IPA, preopt, lno
Wopt, RVl1
Code generation
F : Framework of ORC.
In the code selection phase, WHIRL is converted into
operation list. And this operation list is scheduled in the local
schedule phase. Registers for all the operations are allocated
in local register allocation phase. Finally the assemble code is
e original code of code selection phase is modied
to add the operations from our ASIP architecture and the
algorithm of local schedule is also modied to improve the
utilities of local register les too.
For Itanium architecture, when performing register allo-
cation, at rst, ORC will select a register node. en the
register set that can be used to this node will be evaluated
and registers in the available set are searched one by one to
When a suitable register is found, it will be allocated to the
register node.
However, our ASIP architecture is dierent from Itanium
architecture. In Itanium architecture, every function unit can
access any register. While, in our ASIP architecture, each
function unit can only access its corresponding local register
le and the public global register le, which means that
it is necessary to know which function unit executes the
register node in the register allocation phase, in the original
ORC compiler, the function unit is not necessary information
when compiling, so a new eld needs to be added to note this
In the local schedule phase, this new added eld of
every op is assigned a number which represents its executing
function unit. In the register allocation phase, the registers
When dealing with the register allocation phase, there
are two more problems also needed to be considered. One
came out during the process of nding the can-use register
set for a register node. Because a “bb” is regarded as an atom
element for processing in the register allocation phase and
ORC, all ops involved in one register nodes live-range need to
be considered when allocating register for this register node.
Here, the live-range represents the range from the location
where a node is dened at the rst time to the location where
it is used for the last time.
However, considering the characteristic of our ASIP
architecture, this will limit the range of registers that can be
used to only global register le in most cases. So the ops are
considered only when they treated the register node as source
operand or destination operand when allocating register.
Another problem appeared when there were not enough
registers for allocation. In general, when register allocation
encounters this situation, compilers oen automatically spill
the value into memory. e spill method will also add one op
op to load it from memory before it is used in some time
later. However, in our situation, the information about the
executing function unit of the spill op, both the store one and
International Journal of Distributed Sensor Networks
Cluster A
Cluster C
Cluster B
Cluster D
F : Overview of the architecture.
mistake, and harm to the performance is done.
A new trace algorithm is improved to guide the trace
through the can-use register set to nd a free register that
can be allocated to a register node aer the can-use register
executes the register node, a start location for trace can be
given; then a trace can be carried on. is algorithm can
can-use register set for a target register node.
At last, the code of code emission is modied to get
assemble code in the format dened by our ASIP architecture,
so it can be used on our assembler.
5. Related Work
Clustering has become a common trend in processer design-
ing; there has already been a lot of work concerning the
compiling of clustered architectures.
Codina et al. [] have exploited a concept of virtual
cluster to assist the instruction scheduling for clustered
architecture. Aleta et al. [] have presented a graph-based
approach, which is named AGAMOS, to schedule loops on
clustered architectures, which can reduce the number of
intercluster communications. Arafath and Ajayan []have
implemented a modied list scheduling algorithm using the
amount of clock cycles followed by each instruction and
the number of successors of an instruction to prioritize the
instructions, to perform an integrated instruction partition-
ing and scheduling for clustered architectures.
Zalamea et al. [] have focused on integrating register
spill with instruction scheduling for clustered architecture, to
provide additional possibilities for obtaining high through-
put schedules with low spill code requirements. Huang
et al. []havepresentedaworst-case-execution-time-aware
rescheduling register allocation (WRRA) approach, for clus-
tered architecture. e novelty of this work is that the WCET
problem and the phase ordering problem of the clustered
architecture are taken into account jointly.
6. Experimental Result
As described earlier, our architecture has ve register les,
including four local register les and one global register le.
All function units can access the global register le, but they
can only access their corresponding local register le. And all
the register les have  registers with width of  bits [].
In order to see the inuence of register number on
the performance and to nd out the optimal proportion
between the local register les and global register les, some
experiments were done. First, the numbers of registers of
the global register le and local register le were changed,
keeping the total number of registers in our architecture
constant. en, the numbers of all the register les were
Figure . In situation A, all the register les have  registers.
In situation B, there are  registers in every local register les
and  registers in the global register le. In situation C, each
register le has  registers.
In this gure, 𝑦-axis represents the execution cycles
needed for processing the benchmark []. e data had been
pretreated to be clearly displayed in one picture. ere is
not much dierence between situation A and situation B
of local register les are lower than the global register le.
erefore the reduction of the number of local registers does
little inuence on the performance.
International Journal of Distributed Sensor Networks
r iir latnrm lmsr mult
F : Results of changing the numbers of registers.
But obviously the reduction of the number of global
registers has considerable impaction on the performance, as
compared to the situation C and the two others.
So, if the number of registers is increased, the perfor-
mance is improved, but the trend will atten out when the
number of registers becomes large.
7. Conclusion
In this paper, we have presented our eort at building a
retargetable compiler framework of an ASIP architecture
dedicated for construction of a big data sensor network for
monitoring the greenhouse gases emission. is retargetable
compiler framework is built based on ORC.
Some research has been done to nd out the inuence of
register number on the performance. e result shows that
the more the register number is, the higher the performance
can get. But when the register number grows larger, the
performance growth will atten out. And since the utilities
of local register les are less than the global register le,
the inuence of local register number is less than the global
register le.
Conflict of Interests
e authors declare that there is no conict of interests
regarding the publication of this paper.
is paper is supported by the National Natural Science
Foundation of China (no. ).
[] A. Carnesale and W. Chameides, Americas Climate Choices,e
National Academies Press, Washington, DC, USA, .
[] M. L. Deaton and J. J. Winebrake, “Greenhouse gases and global
warming,” in Dynamic Modeling of Environmental Systems,pp.
[] J.A.Leggett,J.S.Logan,andA.Mackey,Chinas Greenhouse
Gas Emissions and Mitigation Policies, Congressional Research
Service, Library of Congress, .
[] R.S.Eckaus,“Comparingtheeectsofgreenhousegasemis-
sions on global warming,e Energy Journal,vol.,no.,pp.
–, .
for estimating greenhouse gas emissions from deforestation in
developing countries,Environmental Science and Policy,vol.,
no. , pp. –, .
[] J. R. Goodman and W-C. Hsu, “Code scheduling and register
allocation in large basic blocks,” in Proceedings of the Inter-
national Conference on Supercomputing, pp. –, St.Malo,
France, July .
[] S. Novack and A. Nicolau, “Mutation scheduling: a unied
approach tocompiling for ne-grain parallelism,” in Proceedings
of the of 7th Workshop on Languages and Compilers for Parallel
Computing,vol.ofLecture Notes in Computer Science,pp.
–, .
W. W. H w u , “ I m p o r t a n c e o f p r e p a s s c o d e s c h e d u l i n g f o r
superscalar and superpipelined processors,” IEEE Transactions
on Computers,vol.,no.,pp.,.
[] C. Liem, T. May, and P. Paulin, “Instruction-set matching and
selection for DSP and ASIP code generation,” in Proceedings of
the European Design and Test Conference (EURODAC’94),pp.
–, Paris, France, March .
[] Y. J. Zhang, H. Hu, and Y. H. Sun, “A new register le access
architecture for soware pipelining in VLIW processors,” in
Proceedings of the ASP-DAC Asia and South Pacic Design
Automation Conference,vol.,pp.,January.
[] J. M. Codina, J. S´
anchez, and A. Gonz´
alez, “Virtual cluster
scheduling through the scheduling graph?” in Proceedings of the
International Symposium on Code Generation and Optimization
(CGO ’07),pp.,SanJose,Calif,USA,March.
[] A. Aleta, J. M. Codina, J. Sanchez, and A. Gonzalez, “Graphpar-
titioning based instruction scheduling for clustered processors,
in Proceedingsofthe34thACM/IEEEInternationalSymposium
on Microarchitecture (MICRO ’01), pp. –, December .
scheduling scheme for clustered VLIW architecture,” in Pro-
ceedings of the IEEE Recent Advances in Intelligent Computa-
tional Systems (RAICS ’11), pp. –, Trivandrum, India,
September .
[] J. Zalamea, J. Llosa, E. Ayguad´
e, and M. Valero, “Modulo
scheduling with integrated register spilling for clustered VLIW
architectures,” in Proceedings of the 34th Annual International
Symposium on Microarchitecture (MICRO-34 '01), pp. –,
Washington, DC, USA, December .
[] Y.Huang,M.Zhao,andC.J.Xue,“WCET-awarere-scheduling
register allocation for real-time embedded systems with clus-
tered VLIW architecture,” in Proceedings of the 13th ACM
SIGPLAN/SIGBED International Conference on Languages,
International Journal of Distributed Sensor Networks
Compilers, Tools and eory for Embedded Systems (LCTES ’12),
[] C. Lee and M. Stoodley, “UTDSP BenchMark Suite,” ,
... Most companies calculate their greenhouse gas emissions and carbon footprint by assessing their energy consumption and other resource consumption metrics. Using a network of sensors is a more reliable method of measuring and monitoring emissions (Tang, Yang, & Zhang, 2014). By installing sensors to measure emissions, identifying emission sources by emission type can be supported whilst the effectiveness of reduction measures can be more effectively evaluated (descriptive analytics; determination of environmental aspects/plan; regular measurements/check). ...
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Integrating more sustainability into business processes is becoming increasingly important for companies. At the same time, they aim to collect and analyze large amounts of data (big data) to improve these processes. The potentials of big data for corporate environmental protection are hardly dealt with in the scientific literature. The main contribution of this paper is to identify potential big data use cases for corporate environmental management by using the example of the German automotive industry. For this purpose, expert interviews were conducted with corporate environmental managers which were evaluated by using a qualitative content analysis. In order to balance this environmental perspective and enhance it with data analytical expertise, these use cases were assessed by data analytics experts through a mixed method approach, in a subsequent process. The presentation of the identified five use cases and their critical reflection through data analytics experts are the key results of this paper.
... Other studies collect environmental data via sensors. For example, sensor networks were used to monitor the spatio-temporal distribution of greenhouse gas emissions in China (Tang, Yang, & Zhang, 2014). There is also a study (Zhang, Chen, Chen, & Chen, 2016) that combined sensor data, satellite images, and meteorological data with social media for the analysis of urban waterlogging disasters (where drainage systems are unable to cope). ...
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Positive deviance is a growing approach in international development that identifies those within a population who are outperforming their peers in some way, eg, children in low‐income families who are well nourished when those around them are not. Analysing and then disseminating the behaviours and other factors underpinning positive deviance are demonstrably effective in delivering development results. However, positive deviance faces a number of challenges that are restricting its diffusion. In this paper, using a systematic literature review, we analyse the current state of positive deviance and the potential for big data to address the challenges facing positive deviance. From this, we evaluate the promise of “big data‐based positive deviance”: This would analyse typical sources of big data in developing countries—mobile phone records, social media, remote sensing data, etc—to identify both positive deviants and the factors underpinning their superior performance. While big data cannot solve all the challenges facing positive deviance as a development tool, they could reduce time, cost, and effort; identify positive deviants in new or better ways; and enable positive deviance to break out of its current preoccupation with public health into domains such as agriculture, education, and urban planning. In turn, positive deviance could provide a new and systematic basis for extracting real‐world development impacts from big data.
... H. W. Park, Yeo, Lee, and Jang (2014) develop a new network architecture for big data centers based on their experiences from Conseil Européen pour la Recherche Nucléaire (CERN) Large Hadron Collider (LHC) data service. H. Tang, Yang, and Zhang (2014) present a re-targetable compiler freamework with an Application-Specific Instruction Set Processor (ASIP) architecture based on an open resource complier, aiming at building a big data sensor network with the goal of monitoring greenhouse gas emissions. Q. Zhou, Xiao, Tang, and Rong (2014) construct a trusted architecture for capturing and transporting big data. ...
Big data has attracted much attention from academia and industry. But the discussion of big data is disparate, fragmented and distributed among different outlets. This paper conducts a systematic and extensive review on 186 journal publications about big data from 2011 to 2015 in the Science Citation Index (SCI) and the Social Science Citation Index (SSCI) database aiming to provide scholars and practitioners with a comprehensive overview and big picture about research on big data. The selected papers are grouped into 20 research categories. The contents of the paper(s) in each research category are summarized. Research directions for each category are outlined as well. The results in this study indicate that the selected papers were mainly published between 2013 and 2015 and focus on technological issues regarding big data. Diverse new approaches, methods, frameworks and systems are proposed for data collection, storage, transport, processing and analysis in the selected papers. Possible directions for future research on big data are discussed.
One-dimensional (1D) TiO2 nanorod array (TiNA) is used as the support for controllablly growing polypyrrole (PPy) on fluorine-doped tin oxide glasses as the electroactive material for supercapacitors (SCs). Ultraviolet (UV) light is applied during pyrrole electropolymerization on TiNA to provide photoholes for oxidation and improve charge-transfer between pyrrole and TiO2. The light condition and pyrrole monomer concentration for the electropolymerization play important roles on the deposition extent and the performance of the SC electrode. The specific capacitance (CF) value of 200.45 F/g was obtained for the PPy/TiNA-based SC electrode at a scan rate of 5 mV/s. The role of TiO2 is found to be significant in the electrode as the underlayer for the effective 1D electron transfer other than being the electroactive material for Faradic reactions. The CF retention of 72% is attained after 1,500 repeated charge/discharge processes at 2 A/g for the optimized PPy/TiNA-based SC electrode. The result provides new sight to use poor electrocapacitive material as the highway for electron transfer to enhance the SC electrochemical performance and verifies the position to place the nanomaterial in the electrode is of great importance to affect the SC performance.
Technical Report
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Background: Big Data is a relatively new field of research and technology, and literature reports a wide variety of concepts labeled with Big Data. The maturity of a research field can be measured in the number of publications containing empirical results. In this paper we present the current status of empirical research in Big Data. Method: We employed a systematic mapping method with which we mapped the collected research according to the labels Variety, Volume and Velocity. In addition, we addressed the application areas of Big Data. Results: We found that 151 of the assessed 1778 contributions contain a form of empirical result and can be mapped to one or more of the 3 V's and 59 address an application area. Conclusions: The share of publications containing empirical results is well below the average compared to computer science research as a whole. In order to mature the research on Big Data, we recommend applying empirical methods to strengthen the confidence in the reported results. Based on our trend analysis we consider Variety to be the most promising uncharted area in Big Data.
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We discuss the issues about the interdependency between code scheduling and register allocation. We present two methods as solutions: (1) an integrated code scheduling technique; and (2) a DAG-driven register allocator. The integrated code scheduling method combines two scheduling techniques—one to reduce pipeline delays and the other to minimize register usage—into a single phase. By keeping track of the number of available registers, the scheduler can choose the appropriate scheduling technique to schedule a better code sequence. The DAG-driven register allocator uses a dependency graph to assist in assigning registers; it introduces much less extra dependency than does an ordinary register allocator. For large basic blocks, both approaches were shown to generate more efficient code sequences than conventional techniques in the simulations.
Chapter Objectives— After you finish this chapter you should be able to: 1. Describe the greenhouse effect and the processes by which the earth balances energy flows, and how these flows affect global surface temperature. 2. Explain the important parameters within an earth energy balance model that lead to increased surface temperatures. 3. Explore and build a dynamic model that depicts the relationships among the many variables associated with earth’s energy balance system. 4. Using a systems model, evaluate how greenhouse gas emission control strategies may affect the variables associated with earth’s energy balance and ultimately its surface temperature.
Conference Paper
The availability of potentially high operation concurrency in various applications has led to the development of VLIW Processors. To reduce the complexity at hardware and power consumption, the instruction scheduling is done statically. The disadvantage of long wires in the VLIW architecture was overcome by clustering of the processors (Eg. TMS320c6000 series). In clustered VLIW processors, the execution units are grouped to different clusters and the register usage is restricted within the clusters except through the inter-cluster communication slots. So for such architectures, the instruction scheduling has become complex. This work proposes an integrated instruction partitioning and scheduling technique for clustered VLIW architectures. The scheduling algorithm is a modified list scheduling algorithm which uses the amount of clock cycles followed by each instruction and the number of successors of an instruction to prioritise the instructions. The partitioning phase assigns each instruction a cluster depending upon the cluster in which the parent instructions are scheduled. The method produces a better schedule when compared to the list scheduling technique.
Worst-Case Execution Time (WCET) is one of the most important metrics in real-time embedded system design. For embedded systems with clustered VLIW architecture, register allocation, instruction scheduling, and cluster assignment are three key activities to pursue code optimization which have profound impact on WCET. At the same time, these three activities exhibit a phase ordering problem: Independently performing register allocation, scheduling and cluster assignment could have a negative effect on the other phases, thereby generating sub-optimal compiled codes. In this paper, a compiler level optimization, namely WCET-aware Re-scheduling Register Allocation (WRRA), is proposed to achieve WCET minimization for real-time embedded systems with clustered VLIW architecture. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling and cluster assignment on the quality of generated code are taken into account for WCET minimization. These three compilation processes are integrated into a single phase to obtain a balanced result. The proposed technique is implemented in Trimaran 4.0. The experimental results show that the proposed technique can reduce WCET effectively, by 33% on average.
Trade-offs between code selection, register allocation, and instruction scheduling are inherently interdependent, especially when compiling for fine-grain parallel architectures. However, the conventional approach to compiling for such machines arbitrarily separates these phases so that decisions made during any one phase place unnecessary constraints on the remaining phases. Mutation Scheduling attempts to solve this problem by combining code selection, register allocation, and instruction scheduling into a unified framework in which trade-offs between the functional, register, and memory bandwidth resources of the target architecture are made on the fly in response to changing resource constraints and availability.
In response to the United Nations Framework Convention on Climate Change (UNFCCC) process investigating the technical issues surrounding the ability to reduce greenhouse gas (GHG) emissions from deforestation in developing countries, this paper reviews technical capabilities for monitoring deforestation and estimating emissions. Implementation of policies to reduce emissions from deforestation require effective deforestation monitoring systems that are reproducible, provide consistent results, meet standards for mapping accuracy, and can be implemented at the national level. Remotely sensed data supported by ground observations are key to effective monitoring. Capacity in developing countries for deforestation monitoring is well-advanced in a few countries and is a feasible goal in most others. Data sources exist to determine base periods in the 1990s as historical reference points. Forest degradation (e.g. from high impact logging and fragmentation) also contribute to greenhouse gas emissions but it is more technically challenging to measure than deforestation. Data on carbon stocks, which are needed to estimate emissions, cannot currently be observed directly over large areas with remote sensing. Guidelines for carbon accounting from deforestation exist and are available in approved Intergovernmental Panel on Climate Change (IPCC) reports and can be applied at national scales in the absence of forest inventory or other data. Key constraints for implementing programs to monitor greenhouse gas emissions from deforestation are international commitment of resources to increase capacity, coordination of observations to ensure pan-tropical coverage, access to free or low-cost data, and standard and consensual protocols for data interpretation and analysis.
Conference Paper
This paper presents an instruction scheduling and cluster assignment approach for clustered processors. The proposed technique makes use of a novel representation named the scheduling graph which describes all possible schedules. A powerful deduction process is applied to this graph, reducing at each step the set of possible schedules. In contrast to traditional list scheduling techniques, the proposed scheme tries to establish relations among instructions rather than assigning each instruction to a particular cycle. The main advantage is that wrong or poor schedules can be anticipated and discarded earlier. In addition, cluster assignment of instructions is performed using another novel concept called virtual clusters, which define sets of instructions that must execute in the same cluster. These clusters are managed during the deduction process to identify incompatibilities among instructions. The mapping of virtual to physical clusters is postponed until the scheduling of the instructions has finalized. The advantages this novel approach features include: (1) accurate scheduling information when assigning, and, (2) accurate information of the cluster assignment constraints imposed by scheduling decisions. We have implemented and evaluated the proposed scheme with superblocks extracted from Speclnt95 and MediaBench. The results show that this approach produces better schedules than the previous state-of-the-art. Speed-ups are up to 15%, with average speed-ups ranging from 2.5% (2-Clusters) to 9.5% (4-Clusters)
Policies dealing with global warming require a measure of the effects of the emissions of greenhouse gases that create different magnitudes of instantaneous radiative forcing and have different lifetimes. The Global Warming Potential (GWP), a physical index of the total radiative forcing due to an emission of a unit amount of a particular greenhouse gas has been proposed by the Intergovernmental Panel on Climate Change as a such a policy tool. In general, no such physical index will serve this purpose. Adding up physical measures of radiative forcing in different periods resulting from emissions at different times and places is, in an economic and policy sense, like adding apples and oranges. Discounting of radiative forcing in successive periods, as in done in some versions of the GWP, is only an arbitrary weighting. Reduction of radiative forcing effects in different future periods of greenhouse gas emissions that occur at different times and places can be expected to impose different economic costs. These opportunity cost valuations must be used to weight the effects of a greenhouse gas emission over its lifetime. That leads to the concept of the Emissions Opportunity Cost (EOC) of a greenhouse gas emission. While this is more difficult to measure, it is the essential guide to policy.
Conference Paper
This paper presents a novel architecture of register files that combines the local register files and the global register file for clustered VLIW (very long instruction word) processors. The communication between function units through global register file will be more efficient. The concept of associate register is introduced for this architecture. This makes it possible to write a result to two destination registers in one operation, which can efficiently speed up the software pipelining.
Conference Paper
This paper presents a novel scheme to schedule loops for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques followed by a scheduling phase that integrates register allocation and spill code generation. The graph partitioning scheme is shown to be very effective due to its global view of the whole code while the partition is generated. Results show a significant speedup when compared with previously proposed techniques. For some processor configuration the average speedup for the SPECfp95 is 23% with respect to the published scheme with the best performance. Besides, the proposed scheme is much faster (between 2-7 times, depending on the configuration).