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A mite based translinear fpaa and its practical implementation
Abstract
While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user. Ph.D. Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam; Committee Member: Hamblen, James; Committee Member: Minch, Bradley
... Thus it is possible to study different design tradeoffs at higher level of abstraction and on a physical implementation. In the recent years, design automation for circuit synthesis has made inroads in analog domain targeting field programmable analog arrays (FPAAs) for implementation [15]- [16]. FPAAs provide a quick and automatic means of prototyping low to medium frequency range analog applications. ...
The predominance of using digital electronic system implementations over the years has led to less to almost no emphasis on analog electronics education in computer engineering programs. With the high speed operations of digital circuits the analog effects are becoming more relevant. There is a constant demand for portable applications that require increased computational resources in a constant/reduced power operation; this requires consideration of alternative low power analog implementations. Therefore, it is essential for computer engineers to have a good understanding of analog electronics to be effective system designers. Professional engineering societies noted the lack of analog electronics education and have included it as a core component in the computer engineering curriculum recommendations. Therefore the computer engineering curriculum at Ohio Northern University is changed to include analog electronics as a required course. Unlike students enrolled in electrical engineering program, computer engineering students only take the first of the two course sequence in analog electronics. The material covered in the two courses of analog electronics sequence is reorganized using spiraling and spacing learning approaches. The paper summarizes some of the details of the proposed changes.
... GRASPER has features which grant the user various levels of control as to what components are used and how the circuit is mapped onto the FPAA IC [11] [12] [13] [14]. The RAT is a Matlab GUI which graphically shows the topology of how a circuit is routed on the FPAA switches [15]. New designs can be created or existing designs can be modified by pointing and clicking with the mouse. ...
Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This paper presents the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. This infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA IC, discrete ADC, DAC and amplifier ICs, a 32-Bit ARM based microcontroller for interfacing the FPAA with the user's computer, and Matlab and targeting software. The FPAA hardware communicates with Matlab over a USB connection. The USB connection also provides the hardware's power. The software tools include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. The hardware consists of two custom PCB designs which include a main board used to program and control an FPAA IC and an FPAA IC adaptor board used to interface a QFP packaged FPAA IC with the 100 pin ZIF socket on the main programming and control board.
... The RAT is a Matlab GUI which graphically shows the topology of how a circuit is routed on the FPAA switches [15]. New designs can be created or existing designs can be modified by pointing and clicking with the mouse. ...
Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This demonstration will present visitors with the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. A picture of the programming and control hardware that will be demonstrated is found in Figure la. Figure lb shows the software flow that will be demonstrated. The infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA integrated circuit (IC); discrete analog to digital converters (ADC), digital to analog converters (DAC) and amplifier ICs; a 32-Bit ARM based microcontroller (μC) for interfacing the FPAA with a laptop computer; and Matlab and targeting software. The FPAA hardware communicates with Matlab over a Universal Serial Bus (USB) connection. The USB connection also provides the hardware's power. The software tools in the demonstration include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. Figure 2 shows a block diagram of the Programming and Control board and demonstration setup.
Information technologies are an excellent opportunity for Active Learning and Project Based Learning in Electronics. The paper emphasizes on some improvements in teaching Analog Electronics in TU-Varna’s four year Electronics Engineering Bachelor course. A short research on Active Learning approaches is presented. Curriculum construction approach based on Spiral Learning Theme model is highlighted. An accent on FPAA/dpASPs as an effective tool in Analog Electronics education is commented. The Predict-Observe-Discuss-Synthesize teaching methodology is presented as a learning approach which provides highly interactive and at the same time productive lectures. An emphasis on student’s skills for successfully solving simulation tasks in a case study and design of analog circuits is performed. An example for PODS interactive lecture is developed.
While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. An FPAA built using Multiple Input Translinear Elements (MITEs) has been designed, fabricated in 0.35 μ m CMOS, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, RMS-to-DC converters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.
Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer high performance given tight constraints on power and chip area. Field programmable arrays utilizing floating-gate technology are one possible solution to analog design. It offers the advantages of analog processing with the additional advantage of reconfigurability, giving the designer the ability to test new analog designs without costly and time-consuming fabrication and test cycles. In this work, a new interface for FPAA's is demonstrated called Sim2spice, with which users can design signal processing systems in Matlab Simulink and compile them to SPICE circuit netlists. These netlists can be further compiled with a tool called GRASPER to a switch list for programming on an FPAA chip. Example library elements are shown, along with some compiled systems such as filters and vector-matrix multipliers. One particularly compelling application of reconfigurable analog design is the field of neuromorphic circuits, which aims to reproduce the basic functional characteristics of biological neurons and synapses in analog integrated circuit technology. Simulink libraries have been built to allow designers to build neuromorphic systems on several FPAAs that have been developed expressly for the purpose of building neurons and connecting them in networks with synapses. Several possible dynamically learning synapses have also been explored.
In this Letter, we propose a class of nonlinear dynamic translinear circuits as a viable tool for the rapid and systematic implementation of chaotic oscillators in analog integrated circuits. In this regard, our primary focus is on multiple-input translinear element (MITE) networks and their particular merits. We also describe, as an illustrative example, our monolithic implementation of the Lorenz equations, and report on results from a test chip fabricated in a 0.5 μm CMOS process through MOSIS. We also show that Chua's circuit can be implemented easily in our framework.
In this paper, we describe a structured methodology for synthesizing translinear analog signal-processing systems from high-level descriptions in the time domain. The circuits are implemented from elements called multiple-input translinear elements (MITEs). We illustrate the synthesis methodology with the simple example of an RMS-DC converter.
Evolvable Hardware (EHW) refers to HW design and self
reconfiguration using evolutionary/genetic mechanisms. The paper
presents an overview of some key concepts of EHW, describing also a set
of selected applications. A fine-grained Field Programmable Transistor
Array (FPTA) architecture for reconfigurable hardware is presented as an
example of an initial effort toward evolution-oriented devices.
Evolutionary experiments in simulations and with a FPTA chip in-the-loop
demonstrate automatic synthesis of electronic circuits. Unconventional
circuits, for which there are no textbook design guidelines, are
particularly appealing to evolvable hardware. To illustrate this
situation, one demonstrates here the evolution of circuits implementing
parametrical connectives for fuzzy logics. In addition to synthesizing
circuits for new functions, evolvable hardware can be used to preserve
existing functions and achieve fault-tolerance, determining circuit
configurations that circumvent the faults. In addition, we illustrate
with an example how evolution can recover functionality lost due to an
increase in temperature. In the particular case of space applications,
these characteristics are extremely important for enabling spacecraft to
survive harsh environments and to have long life
Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. Our FPAA clustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage and balance again. Experimental results demonstrate the effectiveness of our approach
In this paper, a novel implementation of optimal scalar quantizers using a programmable floating-gate flash analog to digital converter (ADC) is described. The optimal quantization levels for a given signal class are determined according to the Lloyd-Max algorithm. The optimal quantization decision levels are then programmed as the reference voltages for comparators in the floating-gate flash ADC. A test-bench involving the programmable flash ADC and an FPGA interface to a PC is designed. The proposed setup is tested for several signal classes including speech signals and Gaussian random signals. It is demonstrated that significant ADC performance gain, quantified in terms of the signal to noise ratio, may be obtained when optimal scalar quantization is implemented on the floating-gate flash ADC.
This paper proposed a low-voltage and low-power current-to-voltage converter with controllable transconductance. The proposed circuit uses a newly proposed approximation function to increase the dB-linear output range. In a 0.25 μm CMOS process, the simulations show a 58 dB output voltage range and a 46 dB with the linearity error less than ±0.5 dB. The average power dissipation is less than 0.8 mW at 1.5 V supply voltage. The proposed circuit can be used for the design of an extremely low-voltage and low-power variable gain amplifier (VGA) and automatic gain control (AGC).
This report describes a self-biased 5-transistor, 2-capacitor, adaptive logarithmic photoreceptor circuit. The photoreceptor uses its photocurrent, multiplied by a constant factor, to bias its forward amplifier. As a result, power consumption scales with illumination and takes on low values under typical illumination levels. This scaling enables solar powered operation, because power consumption scales with available power. As in earlier circuits, the photoreceptor has an adaptive logarithmic response: it has a bandpass characteristic with low gain for DC (including mismatch) and a higher gain for transient changes in contrast. The gain-bandwidth product is higher than for a passive architecture by a desired multiple. Stability criteria, sharing the bias among many photoreceptors, and measurements from a fabricated chip are shown.
Large networks composed of multiple input translinear elements (MITEs) have been typically limited by the mismatches between individual MITEs. This paper presents the methodology that allows for such systems to be feasible through the application of floating-gate programming techniques. We introduce designs for a programmable MITE, and demonstrate the ability to systematically reduce offsets through accurate programming of example circuits.
Current-voltage (I-V) and voltage-current (V-I) converters for use in current-mode analog integrated circuits are described. The proposed I-V converter has 2.4 decades of linear range, a THD of 0.82% and a bandwidth of 10 MHz. The V-I converter exhibits 5 decades of linear range with a 30 MHz bandwidth at a 1muA bias current and introduces no additional non-linearities. Both circuits have been implemented in a 0.5mum standard digital CMOS process
This paper proposes a simple method to realize an over-sampling pipelined analog-to-digital converter (ADC) with 1.5-bit bit-blocks. The ADC performs conversion by permuting internal capacitors in alternate clocks of the upper 1.5-bit bit-blocks in the analog domain, then averaging the data from bit-blocks in the digital domain. The behavioral simulation of a 14-bit ADC verified that this over-sampling pipelined ADC with 1.5-bit bit-blocks has more than 70 dB of spurious-free dynamic range (SFDR) for up to an 8 MHz input signal when each of the upper three bit-blocks has a gain error of +0.8 %. Using a S/H circuit in front improves the SFDR to 95 dB up to the signal frequency bandwidth of 25.6 MHz when the clock frequency is 102.4 MHz.
This paper reports on a rapid-prototyping platform for high-frequency continuous-time analog filters to be used in communication front-ends. A field programmable analog array (FPAA) is presented, which implements a unique hexagonal topology of 55 tunable OTAs for reconfigurable instantiation of Gm-C filters in a 0.13 mum CMOS technology. It is the first analog array to achieve a bandwidth, which allows processing of intermediate frequencies used in communication systems. In addition to the intuitive manual mapping of analog filters to the chip structure, a genetic algorithm with hardware in the loop is used for automated synthesis of transfer functions.
A new RAM-based, mixed-signal, multicontext dynamically reconfigurable Field Programmable Device with on-chip microprocessor is described. A completely integrated mixed-signal CAD and microprocessor programming environment is used to design and simulate electronic systems composed by microprocessor code and digital and analog hardware. The very flexible communication between the microprocessor, the configurable digital cells and the programmable analog blocks makes possible powerful integration, real-time emulation (internal signals and configuration are available to the microprocessor) and advanced run-time reconfiguration.
"A project report submitted in partial fulfillment of the requirements for the degree of Master of Science (Electrical and Computer Engineering) at the University of Wisconsin-Madison." Typescript. Thesis (M.S.)--University of Wisconsin--Madison, 1986. Includes bibliographical references.
Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP). David V. Anderson, Committee Member ; Dr. Paul Hasler, Committee Chair ; John B. Peatman, Committee Member ; Aaron D. Lanterman, Committee Member. Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
Translinear circuits are circuits in which the exponential relationship between the output current and input voltage of a circuit element is exploited to realize various algebraic or differential equations. This thesis is concerned with a subclass of translinear circuits, in which the basic translinear element, called a multiple-input translinear element (MITE), has an output current that is exponentially related to a weighted sum of its input voltages. MITE networks can be used for the implementation of the same class of functions as traditional translinear circuits. The implementation of algebraic or (algebraic) differential equations using MITEs can be reduced to the implementation of the product-of-power-law (POPL) relationships, in which an output is given by the product of inputs raised to different powers. Hence, the synthesis of POPL relationships, and their optimization with respect to the relevant cost functions, is very important in the theory of MITE networks. In this thesis, different constraints on the topology of POPL networks that result in desirable system behavior are explored and different methods of synthesis, subject to these constraints, are developed. The constraints are usually conditions on certain matrices of the network, which characterize the weights in the relevant MITEs. Some of these constraints are related to the uniqueness of the operating point of the network and the stability of the network. Conditions that satisfy these constraints are developed in this work. The cost functions to be minimized are the number of MITEs and the number of input gates in each MITE. A complete solution to POPL network synthesis is presented here that minimizes the number of MITEs first and then minimizes the number of input gates to each MITE. A procedure for synthesizing POPL relationships optimally when the number of gates is minimal, i.e., 2, has also been developed here for the single--output case. A MITE structure that produces the maximum number of functions with minimal reconfigurability is developed for use in MITE field--programmable analog arrays. The extension of these constraints to the synthesis of linear filters is also explored, the constraint here being that the filter network should have a unique operating point in the presence of nonidealities. Synthesis examples presented here include nonlinear functions like the arctangent and the gaussian function which find application in analog implementations of particle filters. Synthesis of dynamical systems is presented here using the examples of a Lorenz system and a sinusoidal oscillator. The procedures developed here provide a structured way to automate the synthesis of nonlinear algebraic functions and differential equations using MITEs. Ph.D. Committee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradley
In this paper, an oversampling sigma-delta analog-to-digital converter (ADC) has been designed and implemented in 1.5 mum n-well CMOS process using a 1st order modulator and a 2nd order cascaded integrator comb (CIC) decimation filter. The modulator, which is the analog part of the ADC, has been designed using floating gate MOSFETs, which offers a higher common mode range for analog signals. The decimation filter is a digital low pass filter and can be programmed to give 7-bit and 10-bit digital outputs depending upon the oversampling ratio of 16 and 64, respectively. The ADC can be operated up to a clock sampling frequency of 8 MHz
SRAM-based FPGA designs are extremely susceptible to single event upset (SEUs). Since the configuration memory defines which is the circuit an SRAM-based field programmable gate array (FPGA) implements, any change induced by SEUs in the configuration memory may modify drastically the implemented circuit. When such devices are used in safety-critical applications, fault tolerant techniques are needed able to mitigate the effects of SEUs in FPGA's configuration memory. In this paper we present a reliability-oriented place and route algorithm that is able to mitigate the effects of the considered upsets.
An improved CMOS voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the nonlinear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically the substrate-bias effect of the MOS transistor is treated more thoroughly in our design. Consequently, the nonlinearity of the large-signal transresistance of the converter, caused mainly by the body effect of a NMOS transistor in a previously published converter, is greatly minimized. The voltage-to-current converter is designed and fabricated in a 0.35 μm CMOS technology. The fabricated circuit occupies an area of 430 μm × 260 μm (≈12mm-2) and dissipates less than 2.2 mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 VP-P input voltage, the total harmonic distortion (THD) of the output current is less than 1.5%.
A novel field-programmable mixed-analog-digital array (FPMA) is proposed, which contains a field-programmable analog array, a field-programmable digital array, and a mixed-signal interface. This device is intended to be used for the rapid implementation of mixed-signal circuits. The resource and architectural requirements for this array are determined by analyzing a set of sample circuits. The mixed-signal interface is constructed from converter blocks that contain configurable A/D and D/A converters, which gives some flexibility in the specification of the interface. A 1.2 mm CMOS prototype IC has been designed to demonstrate the feasibility of FPMA technology.
The use of floating-gate elements on analog circuits has increased over the last few years. Floating-gate transistors are been used for analog multiplication, memory storage, on-chip bias, offset removals, etc. Complex systems, such as imagers and filter arrays, use thousands to millions of programmable floating-gate elements. The programming speed and precision of these elements plays a major role on the performance of these systems. In this paper we present a system approach that allows for automatic rapid programming of large arrays of floating-gates. We achieve this by optimizing all the time consuming tasks involved in the programming, such as current measurements and drain pulsing among others.
Multiple input translinear elements (MITE) networks can be used to implement a wide variety of static and dynamic functions. The basic product-of-power law MITE circuit is characterized by an input connectivity matrix and an output connectivity matrix. Given a desired product-of-power law function, we describe a synthesis procedure that generates the connectivity matrices. This multiple-input-multiple-output synthesis has distinct advantages over the existing multiple-input-single-output synthesis by requiring lesser (or at most the same) number of MITEs and by being suitable for automated synthesis. MITE networks in which all the MITEs do not have the same number of gates are transformed into MITE networks in which the number of gates are transformed into MITE networks in which the number of gates is the same by a procedure called completion. We describe a novel completion procedure for these product-of-power law circuits.
This paper presents an accurate method for programming analog values into an array of floating-gate pFETs. Channel hot-electron (CHE) injection is used to program the devices and the programming algorithm is based upon a representation of the physical injection equation. The programming accuracy is dependent upon the physical parameters fitting of this equation and the algorithm updates these physical parameters to correspond with the current region of operation. The control circuits used to access each element and program the array are contained on a custom programming board which interfaces to a computer via a serial connection.
The Lattice Semiconductor ispPAC series of programmable analog circuits are among the most recent commercially available programmable analog circuits. A brief overview of the existing members of the ispPAC family is presented, as are descriptions of applications for programmable analog integrated circuits. A discussion of some of the ways in which programmable analog integrated circuits can be used is also presented
We present a methodology for rapid prototyping of linear
time-invariant analog systems. The prototyping hardware is composed of
field-programmable analog arrays (FPAAs) to enable rapid evaluation and
validation of analog designs. Starting with a signal flow graph
description of the system, a library-based technology mapping phase
produces FPAA designs optimized for area. The technology mapper then
explores the design space by performing gain distribution. Technology
mapping is followed by the placement and routing phase that generated
the physical layout on the target single-segment array-based FPAA
architecture. We employ an integrated place and route approach in order
to guarantee routability and performance
Field-programmable gate arrays for prototyping digital circuits
are a widely endorsed approach for reducing time-to-market. Offering
similar advantages, a field-programmable analog array (FPAA) for
prototyping continuous-time analog circuits is reported here.
Conceptually, a FPAA consists of configurable analog blocks (CABs) and
interconnects. The function of each CAB and the connections among CABs
are determined by the contents of an on-chip shift register. Different
circuits can be instantiated using a FPAA by loading in different
configuration bits. This IC strategy offers simplified analog circuit
design with the advantages of instant prototyping, programmable
topology, programmable parameters, CAD compatibility, and testability
We describe a photoreceptor circuit that can be used in massively parallel analog VLSI silicon chips, in conjunction
with other local circuits, to perform initial analog visual
information processing. The receptor provides a continuous-time output that has low gain for static signals (including circuit mismatches), and high gain for transient signals that are centered around the adaptation point. The response is logarithmic, which makes the response to a fixed image contrast invariant to absolute light intensity. The 5-transistor receptor can be fabricated in an area of about 70 μm by 70 μm in a 2-μm single-poly CMOS technology. It has a dynamic range of 1-2 decades at a single adaptation level, and a total dynamic range of more than 6 decades. Several technical improvements in the circuit yield an additional 1-2 decades dynamic range over previous designs without sacrificing signal quality. The lower limit of the dynamic range, defined arbitrarily as the illuminance at which the bandwidth of the
receptor is 60 Hz, is at approximately 1 lux, which is the border between rod and cone vision and also the limit of current consumer video cameras. The receptor uses an adaptive element that is resistant to excess minority carrier diffusion. The continuous and logarithmic transduction process makes the bandwidth scale with intensity. As a result, the total A.C.
RMS receptor noise is constant, independent of intensity.
The spectral density of the noise is within a factor of two of pure photon shot noise and varies inversely with intensity. The connection between shot and thermal noise in a system governed by Boltzman statistics is beautifully illustrated.
In this paper, we discuss the process of synthesizing static and dynamic multiple-input translinear element (MITE) networks systematically from high-level descriptions given in the time domain, in terms of static polynomial constraints and algebraic differential equations. We provide several examples, illustrating the process for both static and dynamic system constraints. Although our examples will all involve MITE networks, the early steps of the synthesis process are equally applicable to the synthesis of static and dynamic translinear-loop circuits.
The very high integration levels reached by VLSI technologies for SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced by single event upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as triple modular redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique.
The design of a single-chip VLSI analog computer fabricated in a 0.25-μm CMOS process is described. It contains 80 integrators, 336 other linear and nonlinear analog functional blocks, switches for their interconnection, and circuitry to enable the system's programing and control. The IC is controlled, programmed and measured by a PC via a data acquisition card. This arrangement has been used to simulate ordinary differential equations (ODEs), partial differential equations, and stochastic differential equations with moderate accuracy, significantly faster than a modern workstation. Techniques for using the digital computer to refine the solution from the analog computer are presented. Solutions from the analog computer have been used to accelerate a digital computer's solution of the periodic steady state of an ODE by more than 10×. The IC occupies 1 cm2 and consumes 300 mW. An analysis has been done showing that the analog computer dissipates 0.02% to 1% of the energy of a general purpose digital microprocessor and about 2% to 20% of the energy of a digital signal processor, when solving the same differential equation.
A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm2 in 0.35-μm CMOS.
A programmable high-frequency operational transconductance
amplifier (OTA) is proposed and analyzed. A general configurable analog
block (CAB) is presented, which consists of the proposed programmable
OTA, programmable capacitor and MOSFET switches. Using the CABs, the
universal tunable and field programmable analog array (FPAA) can be
constructed, which can realize many signal-processing functions,
including filters. A tuning circuit is also discussed. The proposed OTA
has been simulated and fabricated in CMOS technology. The results show
that the OTA has the transconductance tunable/programmable in a wide
range of 700 times and the -3-dB bandwidth larger than 20 MHz. A
universal 5×8 CAB array has been fabricated. The chip has also
been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters
based on ladder simulation and biquad cascade
A new resistorless voltage-to-current converter utilizing only MOS
transistors to achieve voltage-to-current conversion with less than
±0.5% nonlinearity is described. The circuit uses MOS transistors
in linear and saturation regions to produce an output current linearly
related to the input voltage. The output current is proportional to the
carrier mobility tracking the process variations. This circuit is
suitable for submicron technologies where the availability of a linear
resistor with moderate sheet resistance is not guaranteed. The circuit
is fabricated using 0.6-μm n-well CMOS technology, consumes less than
200 μA, and occupies 200 mm2 of area
A 10-b 20-Msample/s analog-to-digital converter fabricated in a
0.9-μm CMOS technology is described. The converter uses a pipelined
nine-stage architecture with fully differential analog circuits and
achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a
full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm2
and dissipates 240 mW
Performance-driven simultaneous placement and routing for fpga’s,” Computer-Aided Design of Integrated Circuits and Systems
- S Nag
- R Rutenbar
S. Nag and R. Rutenbar, “Performance-driven simultaneous placement and routing for fpga’s,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans-actions on, vol. 17, no. 6, pp. 499–518, 1998.
Three-dimensional place and route for fp-gas,” Computer-Aided Design of Integrated Circuits and Systems
- C Ababei
- H Mogal
- K Bazargan
C. Ababei, H. Mogal, and K. Bazargan, “Three-dimensional place and route for fp-gas,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, no. 6, pp. 1132–1140, 2006.
Experimental investigations of floating-gate circuits for /spl delta/ - /spl sigma/ modulators,” in Circuits and Sys-tems, 2002. MWSCAS-2002
- A Pereira
- P Brady
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