W-Band Scalable Phased Arrays for Imaging and Communications

Article (PDF Available)inIEEE Communications Magazine 53(4):196-204 · April 2015with 1,840 Reads
DOI: 10.1109/MCOM.2015.7081095
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This article discusses the benefits and challenges associated with the design of multi-function scalable phased arrays at millimeter wave frequencies. First, applications for phased arrays with tens to hundreds of elements are discussed. Existing solutions for scaling silicon-based phased arrays from microwave to terahertz frequencies are reviewed. The challenges and tradeoffs associated with multiple integration options for W-band phased arrays are analyzed, with special consideration given to packaging and antenna performance. Finally, a solution based on SiGe ICs and organic packages for a 64-element dual-polarized 94 GHz phased array is described, along with associated measurement results.
IEEE Communications Magazine • April 2015
196 0163-6804/15/$25.00 © 2015 IEEE
Xiaoxiong Gu, Alberto
Valdes-Garcia, Bodhisatwa
Sadhu, Duixian Liu, and
Scott K. Reynolds are with
IBM Thomas J. Watson
Research Center.
Arun Natarajan was with
IBM Thomas J. Watson
Research Center. He is
now with Oregon State
W-band frequencies, which range from 75–110
GHz, have been garnering significant attention
recently, specifically in the areas of automotive
radar, backhaul communications, millimeter-
wave (mmWave) radar, and imaging. In the area
of communications and imaging, the availability
of a large bandwidth at these frequencies, as
well as the presence of a low-absorption atmo-
spheric window, makes W-band frequencies par-
ticularly attractive. A number of imaging and
point-to-point wireless link applications require
highly directional transceivers, the ability to
rapidly scan in two dimensions, and support for
dual-polarized operation to meet performance
needs. For such applications, phased-array-
antenna-based solutions, with their beamforming
and electronic beam-steering capabilities, higher
range, and higher signal-to-noise ratio (SNR),
are particularly suitable. Moreover, many of
these applications require significant beam con-
trol capability and functional versatility, while
demanding relatively little radiated power per
element. These requirements make silicon-based
implementations, which are inherently friendly
to multi-function integration, high degrees of
digital programmability, and built-in calibration,
particularly attractive [1].
While advanced complementary metal oxide
semiconductor (CMOS) nodes provide higher
density for digital integration, the effective cut-
off frequency fMAX (including wiring to device
terminals) and output power delivery capabilities
of CMOS devices are limited. In contrast, SiGe
BiCMOS technologies provide higher effective
fMAX and power handling capability, as well bet-
ter potential for further fMAX increase while still
providing CMOS technology for digital functions
[2]. However, for either advanced CMOS or
SiGe BiCMOS technology, the cost benefits of
silicon integrated circuit (IC) manufacture only
become compelling when production is scaled to
more than tens or hundreds of thousands of
units. This fact presents particular challenges for
low-volume phased array applications that
require large numbers of elements for high
directionality, translating to large, expensive ICs
if all elements are integrated on a single IC. In
addition, the maximum IC size has manufactura-
bility constrains. A modular approach consisting
of scalable phased arrays, in which an arbitrary
number of repeated unit cells operate in unison,
is therefore an attractive alternative from many
perspectives, including cost, yield, robustness,
and ease of testing.
In this article, we discuss the advantages and
challenges of designing such scalable, multi-func-
tional, W-band phased arrays in silicon. The next
section discusses the impact of scalability on W-
band communications. A review of existing scal-
able phased arrays is covered after that.
Trade-offs associated with various scalability
options are then discussed; measurement results
from a prototype scalable 64-element phased
array at 94GHz are presented in the following
section, and some concluding remarks are pre-
sented in the final section.
Millimeter-wave links are now an integral part of
the wireless backhaul infrastructure, particularly
at E-band frequencies (71–76 GHz, 81–86 GHz,
and 92–94 GHz) [3]. Note that these frequencies
are a subset of the W-band frequency range. E-
band links are currently implemented by a com-
This article discusses the benefits and chal-
lenges associated with the design of multi-func-
tion scalable phased arrays at millimeter wave
frequencies. First, applications for phased arrays
with tens to hundreds of elements are discussed.
Existing solutions for scaling silicon-based
phased arrays from microwave to terahertz fre-
quencies are reviewed. The challenges and trade-
offs associated with multiple integration options
for W-band phased arrays are analyzed, with
special consideration given to packaging and
antenna performance. Finally, a solution based
on SiGe ICs and organic packages for a 64-ele-
ment dual-polarized 94 GHz phased array is
described, along with associated measurement
Xiaoxiong Gu, Alberto Valdes-Garcia, Arun Natarajan, Bodhisatwa Sadhu, Duixian Liu,
and Scott K. Reynolds
W-Band Scalable Phased Arrays for
Imaging and Communications
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 196
IEEE Communications Magazine • April 2015 197
bination of single-element transceivers and
antennas with high gain (i.e., > 30 dB) and con-
sequently occupy large form factors. Mechanical
alignment is required for these antennas; as
such, links are established and maintained in a
single fixed direction, as shown in the top exam-
ple in Fig. 1a.
Monolithic phased arrays intended for indoor
applications at 60 GHz have already demonstrat-
ed links with data rates in excess of 5 Gb/s at
distances of ~10 m employing only 16 antennas
[1]. These and other similar results have moti-
vated research on highly integrated phased
arrays at higher frequencies and with a larger
number of elements.
Silicon-based scalable phased arrays at W-
band offer the possibility of attaining similar
coverage range as current fixed-beam solutions
with the additional advantage of dynamic steer-
ability, at the cost of complexity and power con-
sumption. Electronic steerability would not only
eliminate the need for mechanical alignment,
but would also open the possibility of dynamic
backhaul networking, as shown in the bottom
example in Fig. 1a. The scalability of a unit cell
array with a moderate number of elements is
key, since different links and usage scenarios
may require a different number of elements.
To illustrate the potential of a scalable phased
array at W-band, the table in Fig. 1b introduces
the link budget considerations for a 1 Gb/s link
formed with tiles of 64 antenna elements sup-
Figure 1. a) Illustration of two different types of mmWave backhaul link, with fixed high-gain antennas (top) and with a phased
array (bottom); b) summary table of measured transceiver IC performance [4] and assumptions for link budget calculation; c) esti-
mated range for a 1 Gb/s terrestrial data link at 74, 84, and 94 GHz, constructed using scalable phased arrays of various sizes. The
estimates assume QPSK (2b/symbol) in 800 MHz RF bandwidth, LDPC code (1369, 1260) with code rate R= 0.92, and BER =
10–7 with 5dB implementation loss and 0.4 dB/km atmospheric loss; d) calculated EIRP as a function of the number of tiles.
Number of tiles (packages with 64 antennas)
Calculated range (km)
10 15 20 25
Number of tiles (packages with 64 antennas)
(c) (d)
(a) (b)
Calculated array EIRP (dBm)
10 15 20 25
RX-mode RF front-end NF (incl. T/R switch) 8.2 dB
Carrier frequency (GHz) 74, 84, 94
Antenna gain (dBi) 2
TX output power (dBm) 0
RX NF (dB) 9.5
16-element transceiver ICs per tile (package) 4
Antenna elements per tile (package) 64
Symbol rate (GS/s) 0.55
Bits per symbol 2
Code rate 0.92
Source bit rate (Gb/s) 1.012
Atmospheric loss (dB/Km) 0.4
Required Eb/N0 (dB) 6
Link margin (dB) 5
Phase shifter range 360°
TX-mode overall IC saturated power output
(per output, including T/R sw.) 2 dBm
Phase shifter resolution <11.25°
RX-mode power consumption: 16 inputs for
alternate H or V reception 2.2 W
TX-mode power consumption with IF/BB input 2.7/2.9 W
Synthesizer phase noise (for output frequencies
from 73.9 to 83.5GHz) <-110 dBc/Hz @ 10 MHz offset
Fixed point-to-point backhaul link
94 GHz
84 GHz
74 GHz
Phased-array-based mmWave
link with dynamic electronic
beam steering
Building Building
Assumptions for link budget calculation
Summary of measured 16-element phased array transceiver IC performance at
94 GHz [4]
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 197
IEEE Communications Magazine • April 2015
ported by four 16-element phased array ICs.
This link budget calculation considers the mea-
sured phased array IC performance reported in
[4], which is also shown in Fig. 1b. It should be
noted that the NF and output power perfor-
mance used in the link budget calculation is
slightly worse (1.5–2 dB) than that reported for
an IC at room temperature to account for per-
formance degradation at higher temperatures.
Figure 1c shows the potential link range as a
function of the number of tiles for three differ-
ent E-band frequencies. It can be observed that
a 10+ km range is potentially achievable with a
4 ×4 array of 64-element tiles (1024 elements),
and such an array would occupy an area smaller
than 70 mm2. The calculated array equivalent
isotropic radiation power (EIRP) as a function
of the number of tiles is plotted in Fig. 1d.
Implementing a single multifunctional or recon-
figurable RX and/or TX element in an IC, which
is similar to approaches using discrete compo-
nents, is one possible approach that can be taken
to enable realization of scalable arrays [5, 6].
Such an approach provides high levels of flexibil-
ity by maximizing the granularities at which
arrays can be created, but fails to take advantage
of a key aspect of silicon technologies: the avail-
ability of multiple well-controlled interconnect
layers. The single-unit approach places the sig-
nificant complexity and cost burden associated
with routing large numbers of RF, IF, and/or
baseband signals on the PCB and packaging
instead of fully leveraging the wiring capabilities
of silicon to enable complex array realization.
The single-unit approach also leads to high
power consumption since impedance-matched
drivers are required on every IC. At low RF fre-
quencies (< 10 GHz), large antenna spacing is
offset by low packaging losses, making single-ele-
ment unit cells feasible. At these frequencies,
the interface to the antenna can also be consid-
ered independent of the IC unit cell due to the
relatively flexible packaging requirement. How-
ever, at mmWave frequencies (> 30 GHz), phys-
ically short antenna spacings (~l/2 < 5 mm),
packaging losses, and manufacturing challenges
with impedance-controlled multi-layer packaging
interconnects make multi-element unit ICs more
attractive. Trade-offs with respect to system
packaging and antenna integration are discussed
in detail in the next section.
In the case of the array TX (RX), a unit cell
that contains Nelements must distribute (com-
bine) the input signal to (from) each of the N
elements while providing variable phase-shift
and variable-gain functionality in each element.
The unit cell may or may not include frequency
translation. Note that intermediate frequency
(IF) signal distribution is preferable to RF signal
distribution in the package; however, frequency
translation implies that multiple unit cells need
to be phase locked. Therefore, in addition to the
IF signal, a frequency reference at the local
oscillator (LO) frequency or a lower frequency
must also be distributed. As mentioned earlier,
at mmWave frequencies, the N-element unit cell
must be envisioned while also considering the
interface between the IC and antennas.
Research and development efforts focused on
RFICs have led to scalable integrated phased
array architectures based on RF and/or LO-path
phase shifting at frequencies from 6 GHz to
beyond 100 GHz [7, 8]. The scalable low-IF 6–18
GHz array receiver in [7] incorporates two
receivers, with each receiver capable of provid-
ing two outputs with independent variable phase
shift and variable gain for multi-beam arrays.
The IC includes PLLs that operate from a 50
MHz reference enabling phase locking between
multiple ICs. The sub-100 MHz IF and refer-
ence frequencies simplify multi-IC packaging;
however, an N-element array requires Nsuch
ICs, increasing packaging complexity. In [9], a
scalable Q-band array is presented that leverages
a 16-element phased array T/R phase shifting
and combining front-end [10] along with a 4 ×4
array of wide-scan patch antennas. This approach
also addresses the challenges of RF and DC
interconnect within the unit cell with a micro-
machined silicon interposer for signal routing.
Including the antennas and ICs in the unit cell
simplifies subsequent packaging, but the signal
distribution is still at RF, and additional ICs are
required for signal combining and distribution to
the phased array unit cell. In [8], a scalable
CMOS transmit phased array element is devel-
oped at 140 GHz, with each element containing
a phase locked loop (PLL) capable of LO-path
phase shifting, digital-to-RF upconversion, and
antenna-on-PCB that eliminates the need for
mmWave signal distribution when multiple ele-
ments are tiled.
In general, digital beamforming arrays that
incorporate analog-to-digital (A/D) and D/A
conversion in each unit cell considerably reduce
RF, IF, or analog baseband signal distribution
and reduce sensitivity to packaging when the
array is scaled to larger numbers of elements.
Furthermore, digitization is an approach that is
well suited for advanced CMOS technologies.
The potential for such digital-intensive scalable
arrays has been demonstrated in X-band using
monolithic microwave ICs (MMICs) and com-
mercial off-the-shelf (COTS) components in
[11]. It must be noted, however, that digital IO
can lead to high power consumption in wide-
band arrays, limiting array size (8 bits I and Q at
1 GS/s, implies 16 Gb/s, translating to 160
mW/IC assuming 10 pJ/b serial link efficiency).
Therefore, an attractive approach to realizing
wideband large-scale arrays is a combination of
N-element RF-combined unit cells and digital
IO at the sub-array level. Hybrid analog and dig-
ital beamforming has also been explored in [12].
Each N-element unit cell forming the scalable
array can be designed to use RF-path, LO-path,
or IF-path phase shifting. Among these options,
although LO- and IF-path phase shifting are rel-
atively easier to implement, RF-path phase shift-
ing offers significant hardware and performance
It can be observed
that a 10+ km
range is potentially
achievable with a
4 ×4 array of
64-element tiles
(1024 elements), and
such an array would
occupy an area
smaller than
70 mm2.
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 198
IEEE Communications Magazine • April 2015 199
advantages. An RF-path phase shifting architec-
ture uses the minimum amount of hardware and
achieves the lowest power consumption. In the
receiver, since all the interferers are nulled out
at RF, the linearity requirements of the IF base-
band stage are reduced [13].
Figure 2 illustrates different architecture con-
cepts for combining and distributing the input
signals for each of the N-element unit cells to
form a large scalable array. In Fig. 2a, the com-
bined RF signals are output from each unit cell
and are distributed on the package or board
level before being down-converted to baseband.
Each N-element RFIC in this case uses RF-path
combining. The relative simplicity and flexibility
of the RFICs come at the expense of complex
packaging and board design. In Fig. 2b, A/D and
D/A conversion is incorporated in each unit cell.
For each N-element IC, any combination of
RF-path, LO-path, or IF-path can be used. The
incorporation of A/D and D/A inside the unit
cell enables significantly reduced signal routing
for package and board implementation; howev-
er, repeating the A/D/A in each unit cell results
in significantly higher power consumption. In
Fig. 2c, an intermediate balanced approach is
outlined where IF signals from each unit cell are
daisy chained and further down-converted to
baseband on the package or PCB level. Again,
for the option in Fig. 2c, each N-element RFIC
can use any of the three combining options.
While this replicates the on-IC IF hardware, as
opposed to the option in Fig. 2a, the distribution
of IF signals instead of RF signals significantly
simplifies packaging and board design.
For silicon-based scalable phased array at W-
band frequencies (75–110 GHz), the l/2 antenna
pitch ranges from 1.35 to 2 mm, which requires
tightly integrated antenna solutions for system
packaging. Figure 3 illustrates three categories
of packaging options for antenna integration at
these frequencies.
The first of these options involves implement-
ing antennas directly on the application PCB.
The RFICs are flip-chip bonded to the board on
the opposite side from the direction of radiation.
Note that wire bonding of the ICs would not
meet the tight pitch demands for the array that
are imposed by scalability considerations. In this
approach, the major challenges comprise design-
ing antennas with sufficient gain and efficiency,
as well as controlling the antenna variation aris-
ing from the PCB manufacturing tolerances. For
example, the registration (i.e., lateral movement
of the position) of vertical vias used for carrying
mmWave feed signals degrades as the number of
layers grows, which needs to be accounted for in
the antenna and board design.
The second option shown in Fig. 3 involves
implementing antennas on the first-level pack-
age. Together with the flip-chip bonded ICs, the
package forms a unit tile module. The modules
can then be attached to a second-level PCB
through ball grid arrays (BGAs) to form a larger
array. Depending on the application, there are
many substrate technologies that have appropri-
ate properties for implementing the package
with embedded antennas, including but not lim-
ited to low-temperature co-fired ceramic
(LTCC), glass, multi-layer organic polymer, and
embedded wafer level BGA (eWLB). The struc-
ture tolerance on the package is typically signifi-
cantly improved over that of the PCB process,
which allows antennas to be built with better
uniformity at a tight pitch. Each assembled pack-
age can also be prescreened and tested by check-
ing digital functions of all elements before the
package is mounted on the board. On the other
hand, this approach does have a disadvantage,
which is the higher complexity of the system
The third option considered in Fig. 3 is imple-
menting antennas directly on the RFIC. In [14],
it has been demonstrated that by stacking a glass
(quartz) substrate with a metal patch on top of
the RFIC with antenna feed, the peak gain of
the superstrate antenna can be boosted to 4 dBi
at 110 GHz with 50 percent efficiency. Refer-
Figure 2. Scalable array system architecture concepts: a) distributing RF signals from IC output; b) digital beamforming; c) dis-
tributing IF signals between daisy-chained unit cells.
On-chip Off-chip
On-chip Off-chip
On-chip Off-chip
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 199
IEEE Communications Magazine • April 2015
ence [14] also proposes the concept of a wafer-
scale phased array that stacks a glass wafer with
antenna elements directly with a silicon wafer
with phased array elements and antenna feeds.
An alternative is to first have RFICs attached to
the package and then a glass substrate on top of
the RFICs to form a large array. In this case,
through-silicon-vias (TSVs) are required for the
RFICs to feed signals and deliver power and
ground depending on the chip configuration
(face-up or face-down). The system integration
complexity of this third option is expected to be
the highest among all three options.
Other important challenges in system integra-
tion from an electrical perspective include the
power integrity of different voltage and ground
domains, the signal integrity of the chip-to-
antenna transition, as well as high-speed signal
wiring (e.g., for baseband, IF, and LO signals).
Characterization of on-chip and off-chip inter-
connect losses is required based on conductor
and dielectric material properties at the frequen-
cies of interest.
Thermal management is another key aspect
of the system design. Figure 3 illustrates a con-
ceptual placement of heat sinks. Multi-physics
co-simulations with the active IC power budget
are required in the design phase to accurately
evaluate on-die temperature based on different
cooling options and the projected ambient envi-
ronment. For example, the power density for 60
GHz and 94 GHz phased-array RFICs [1, 4]
operating in the receive mode can reach 87
mW/mm2and 77 mW/mm2, respectively.
Although these numbers are lower than what a
typical server processor consumes (e.g., ~200
mW/mm2), cooling the phased array system is
expected to be more challenging: compared to a
server processor, more total heat needs to be
dissipated due to a large number of active ele-
ments, and many more ICs need to be thermally
controlled simultaneously to support the scala-
bility of the system. On the other hand, advances
in technology such as SiGe BiCMOS processes
with higher cutoff frequency (e.g., IBM SiGe
8XP or 9HP), in combination with new break-
throughs in circuit design, are expected to reduce
power consumption.
The three antenna and package options in
Fig. 3 are viable approaches to support the
implementation of W-band scalable phased
arrays. Generally speaking, due to the l/2 pitch
requirement, the on-chip antenna approach
works better for higher frequencies in the band,
whereas on-board and on-package antenna
approaches work better for lower frequencies. In
the following section, a prototype scalable 64-
element phased array at 94 GHz based on a fully
integrated antenna-in-package solution is pre-
Our approach to realizing a dual-polarized scal-
able phased array is illustrated in Fig. 4a, which
follows the antenna-in-package approach
described in Fig. 3. Each transceiver IC contains
16 dual-polarized RF phase-shifting front-ends.
RF-path phase shifting was selected to achieve
minimum hardware and power consumption at
the IC level. All of the mmWave functions are
integrated monolithically. Each package houses
four ICs and includes 64 dual-polarized anten-
nas. The antennas are placed at a ~ l/2 pitch at
94 GHz in both the x and y dimensions, and the
antennas on the perimeter are placed ~ l/4
away from the package edge. By tiling the pack-
ages adjacent to one another on a PCB, phased
arrays of large aperture can be created to sup-
port long-distance communication and high-res-
olution imaging. The first two steps of this
approach to implementing scalable phased arrays
(transceiver IC and package integrating ICs and
antennas) have been demonstrated in hardware
[4, 15] and are described below in more detail.
The final step (board-level array tiling multiple
packages) is the subject of future work.
The multi-function dual-polarization phased
Figure 3. Antenna and package options for W-band scalable phased array.
Heat sink
Heat sink
Heat sink
75 GHz 94 GHz 110 GHz
(in W-band)
Heat sink
RF chip
Antennas on chip/waferAntennas on packageAntennas on PCB
Glass substrate
stacked on RF chip
PCB with
embedded antenna
1st- level package tiles
with embedded antenna
Glass wafer (with
antennas) on silicon wafer
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 200
IEEE Communications Magazine • April 2015 201
array transceiver IC supports both radar and
communication applications at W-band [4]. 32
receive elements and 16 transmit elements with
dual outputs are integrated to support 16 dual
polarized antennas in a package. As illustrated
in Fig. 4b, the IC includes two independent 16:1
combining networks, two receiver down-conver-
sion chains, an up-conversion chain, a 40 GHz
PLL, an 80 GHz frequency doubler, extensive
digital control circuitry, and on-chip IF/LO com-
bining/distribution circuitry to enable scalability
to arrays at the board level. The fully integrated
transceiver is fabricated in the IBM SiGe BiC-
MOS 8HP 0.13 mm process, occupies an area of
6.6 mm ×6.7 mm, and operates from 2.7 V (ana-
log/RF) and 1.5 V (digital) supplies. Multiple
operating modes are supported, including the
simultaneous reception of two polarizations with
a 10 GHz IF output, transmission in either polar-
ization from an IF input, or single-polarization
transmission/reception from/to I&Q baseband
Iterations of circuit-package-antenna co-
design were performed under severe physical
dimension constraints to support array scalability
at the package and board levels. Figure 4c shows
a close-up view of antenna patches at the top of
the package. 100 (10 ×10) patch structures at
1.6 mm spacing (l/2 at 94 GHz) cover the sur-
face of the package. The IC area is very close to
that required for 16 (4 ×4) antennas with l/2
spacing for all the functionality; as a result, a
multi-chip 16.2 mm2×0.75 mm package con-
taining 4 SiGe-based RFICs and a 292-pin 0.4
mm-pitch BGA was designed to achieve as high
an array fill factor as possible [15]. The multi-
chip package approach also mitigates the board-
level integration risks compared to the
single-chip package approach. Out of the 100
patches for each package, 64 are actual dual-
polarized patch antennas and 36 are dummy
structures (which do not have actual antenna
features other than the surface patch). There-
fore, the effective array fill factor is 64 percent.
The dummy structures are placed at pseudo-ran-
domized locations to minimize the impact of the
reduced fill factor on side lobes. The copper bal-
ance in terms of metal percentage per layer also
increases with the dummies, which improves
manufacturability of the package. Figure 5a illus-
trates an array simulation in MATLAB with
1024 isotropic radiators based on the antenna
pattern, which is equivalent to tiling 16 (4 ×4)
94 GHz packages. Notice that by choosing the
patch locations carefully, empty rows or columns
of active radiation elements can be avoided. The
Figure 4. a) A prototype scalable 64-element phased array at 94 GHz; b) dual-polarized 16-element 94 GHz phased array transceiver
IC photograph (6.6 mm ×6.7 mm); c) a close-up view of the 4-chip package with actual patch antennas and dummies.
4 SiGe ICs attached to the
bottom of the package
64 actual patch
36 dummy patches
16.2 mm
RX and TX I/Q
analog baseband,
IF (10 GHz) I/O
digital logic
16.2 mm
(b) (c)
Transceiver IC
Package with 4 ICs and 64
dual-polarized antennas
(unit tile) Board-level large-scale
H1 V1
...... V16
Phased array transceiver
IC supporting 16 dual -
polarized antennas
40 GHz PLL
(1 GHz REF),
freq. doubler,
RF RX mixers,
RF TX mixer
94 GHz dual-
RF front-
end (1/16)
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 201
IEEE Communications Magazine • April 2015
simulated radiation patterns are plotted in Figs.
5b and 5c for q = 0° and q = 30°, respectively.
The overlay of a SiGe die image with a quad-
rant of the package layout is illustrated in [15].
Two rows and columns of BGA pins provide all
signal, power, and ground connections to the
C4s (controlled collapse chip connections) on
the north and east sides of the die. Signal and
power integrity are taken into account in the IC-
package co-design. For example, high-speed dif-
ferential signals are routed from the inner BGA
row as short microstrip pairs on the bottom sur-
face layer to avoid via transition, whereas low-
speed single-ended signals are routed from the
outer BGA row as striplines. Dielectric proper-
ties (relative permittivity and loss tangent) of the
buildup and core layers of the organic package
are measured and characterized up to 110 GHz
so that accurate full-wave electromagnetic mod-
els for the interconnects and antennas can be
constructed. Furthermore, two groups of voltage
supply pins, as well as ground pins, are placed
evenly on the periphery to ensure good power
distribution to the chip. The RF front-end C4s
for the W-band antenna feed are laid out using a
225-mm-pitch GSGSG configuration. In order to
minimize the RF antenna feed line length, the
locations of these C4s were optimized together
with the circuit layout for the front-end, core,
and digital macros.
Figure 6a illustrates a conceptual view of the
measurement setup for one assembled multi-
chip module with 64 embedded antennas. The
patch antenna array is on the top of the package.
Four SiGe ICs are flip-chip attached to the bot-
tom of the package. The module is mounted to a
system board via a pogo-pin-based interposer,
which allows air cooling and supports easy
removal for screening. The IC package assembly
was performed using standard flip-chip attach
processes with lead-free solder reflow and under-
fill. SMP connectors are populated on the board
to provide PLL reference and IF signals to the
four ICs. In addition, a daisy-chain configuration
is implemented as illustrated in Fig. 2c, so only
one PLL reference input and one IF input are
required from external sources for antenna pat-
tern and radiated power measurement.
The test board with the phased array module
is further mounted to a field programmable gate
array (FPGA) board through which the digital
circuits are programmed and controlled by a
PC. Two motors are used to drive the rotation
of the test board (azimuth angle) and the receive
horn (elevation angle), respectively. For trans-
mit-mode testing, the 16 elements of each IC
are turned on sequentially while measuring the
receive power in the broadside direction. The
optimum phase coefficients for spatial power
combining are found by sweeping the phase of
each element with a 22.5° step. Next, a phase
offset between groups of the four 16-element
ICs can be found to achieve the module-level
64-element power combining. The measured 16-
element and 64-element special power combin-
ing results in terms of normalized EIRP are
plotted in [15]. To enable calibration, gain con-
trol is also applied to each element and tuned
to compensate the radiated power variation
(e.g., due to the intrinsic non-uniformity of
Figure 5. a) Array simulation with 1024 isotropic radiation elements based
on the 94 GHz package antenna pattern (as highlighted); b) simulated
1024-element radiation pattern (q= 0°); c) simulated 1024-element radia-
tion pattern (q= 30°).
Element position (mm)
Elements selected: 1024
Element position (mm)
10 20 30 40 50 60 70
Theta (degrees)
Normalized gain (dB)
-20 0 20 40 60
Theta (degrees)
Normalized gain (dB)
-20 0 20 40 60
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 202
IEEE Communications Magazine • April 2015 203
antenna gains). Finally, beam steering can be
enabled by adjusting the phase coefficients,
which are calculated analytically based on the
target direction. Figure 6b shows the measured
radiation patterns after spatial power combining
of all 64 elements for both H and V polariza-
tions. Good correlation with a simulated ideal
radiation pattern is shown in [15]. In addition to
the broadside radiation patterns, patterns with
15° beam steering are also demonstrated for
both polarizations with side-lobe levels lower
than 10 dB. A wider steering angle (e.g., 30°) is
achievable at the expense of a higher side lobe
level, which in turn can be overcome by using
different tapering techniques.
Millimeter-wave phased array technologies are
rapidly emerging in the areas of automotive
radar, satellite and backhaul communications,
security scanning, and imaging. In this article, we
review the existing solutions of scalable phased
array and discuss the advantages and challenges
of designing multi-function scalable W-band
phased arrays on silicon with special considera-
tion to packaging and antenna integration. Our
research efforts in this area have demonstrated
the feasibility of using silicon technology and
organic package substrates to implement scal-
able arrays at W-band. A fully integrated anten-
na-in-package solution is developed to build a
compact W-band dual polarized phased array
transceiver module with 64 antennas and 4 SiGe
ICs. The 94 GHz 16-element transceiver IC, fab-
ricated in a mature SiGe BiCMOS process,
demonstrates noise figure (<10 dB), output
power (> 0dBm per element), phase shift (~11°
resolution per element), and phase noise perfor-
mance (–110 dBc/Hz @ 10 MHz offset) suitable
to support imaging and communication applica-
tions. The results from this phased array module
have demonstrated 64-element spatial power
combining and electronic beam steering for both
horizontal and vertical polarizations. A next
important step is to further tackle system inte-
gration challenges, that is, to implement a larger
array with multiple modules on the board level
(e.g., 1024 elements with 16 packages), which
will allow exploration of the approach for larger-
scale applications.
IBM’s 94 GHz work has been partially funded
by DARPA Strategic Technology Office (STO)
under contract # HR0011-11-C-0136 (Si-Based
Phased-Array Tiles for Multifunction RF Sen-
sors, DARPA Order no. 8320/00, Program Code
1P30). The views, opinions, and/or findings con-
tained in this presentation are those of the
authors/presenters and should not be interpreted
as representing the official views or policies,
either expressed or implied, of the Defense
Advanced Research Projects Agency or the
Department of Defense. Approved for Public
Release, Distribution Unlimited.
[1] A. Valdes-Garcia et al., “Single-Element and Phased-
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cations,” IEEE Commun. Mag., April 2011, pp. 120–31.
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[3] Z. Pi and F Khan, “An Introduction to Millimeter-Wave
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[4] A. Valdes-Garcia et al., “A Fully-Integrated Dual-Polar-
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SiGe BiCMOS,” Proc. IEEE Radio Frequency Integrated
Circuits Symp., June 2013, pp. 375–78.
[5] M. LaManna and A. G. Huizing, “Scalable Multifunction
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[7] J. Sanggeun et al., “A Scalable 6-to-18 GHz Concurrent
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[8] A. Tang, et al., “A 65nm CMOS 140 GHz 27.3 dBm EIRP
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Figure 6. a) Radiated power and pattern measurement setup; b) measured
64-element array radiation patterns and beam steering.
Motor 2
Phased array
Received horn
antenna and
Signal generator
(10 GHz IF)
RF cables
Motor 1
FPGA board
Application board
USB and digital cables
Signal generator
(1 GHz PLL ref.)
0 dB
-10 dB
-20 dB
-30 dB
0 dB
-10 dB
-20 dB
-30 dB
0 dB
-10 dB
-20 dB
-30 dB
0 dB
-10 dB
-20 dB
-30 dB
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 203
IEEE Communications Magazine • April 2015
[14] W. Shin et al., “A 108–114 GHz 4×4 Wafer-Scale
Phased Array Transmitter with High-Efficiency On-Chip
Antennas,” IEEE J. Solid-State Circuits, vol. 48, no. 9,
Sept. 2013, pp. 2041–55.
[15] X. Gu et al., “A Compact 4-Chip Package with 64 Embed-
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Transceivers,” Proc. IEEE Electronic Components and Tech-
nology Conf. (ECTC), May, 2014, pp. 1272–77.
XIAOXIONG GU[SM] received his Ph.D. in electrical engineering
from the University of Washington in 2006. He joined IBM T. J.
Watson Research Center as a research staff member in January
2007. His current research activities are focused on design,
packaging, integration, and characterization of optoelectronic
and mmWave communication and computation subsystems.
He received SRC Mahboob Khan Outstanding Industry Liaison
Awards in 2012 and 2014, IBM Invention Plateau Awards in
2012 and 2013, a Best Paper Award at IEEE EMC Symposium
in 2013, the Best Conference Paper Award at IEEE EPEPS in
2011, DesignCon Paper Awards in 2008 and 2010, the Best
Session Paper Award at IEEE ECTC in 2007, and the Best Inter-
active Session Paper Award at IEEE DATE in 2008. He is the
chair of THE Professional Interest Community of Electrical Inter-
connect and Packaging at IBM. He currently serves on the
Technical Program Committees for EPEPS, ECTC, EDAPS, and
ALBERTO VALDES-GARCIA is currently a research staff member and
manager of the RF Circuits and Systems Group at IBM T. J.
Watson Research Center. He received his Ph.D. degree in elec-
trical engineering from Texas A&M University in 2006. His cur-
rent research work is on silicon-integrated millimeter-wave
systems for imaging and communications. From 2006 to 2009,
he served in the IEEE 802.15.3c 60GHz standardization com-
mittee. Since 2009 he served as a Technical Advisory Board
member with Semiconductor Research Corporation (SRC),
where he was Chair of the Integrated Circuits and Systems Sci-
ences Coordinating Committee in 2011 and 2012. He holds 17
U.S. patents and is a Co-Editor of the book 60GHz Technology
for Gbps WLAN and WPAN: From Theory to Practice (Wiley,
2011). He is was winner of the 2005 Best Doctoral Thesis
Award presented by the IEEE Test Technology Technical Coun-
cil (TTTC), the recipient of the 2007 National Youth Award for
Outstanding Academic Achievements, presented by the Presi-
dent of Mexico, and a co-recipient of the 2010 George Smith
Award presented by the IEEE Electron Devices Society. In 2013,
he was selected by the National Academy of Engineering for
its Frontiers of Engineering Symposium.
ARUN NATARAJAN received his B.Tech. degree in electrical
engineering from the Indian Institute of Technology,
Madras, in 2001, and his M.S. and Ph.D. degrees in electri-
cal engineering from the California Institute of Technology
(Caltech), Pasadena, in 2003 and 2007, respectively. From
2007 to 2012, he was a research staff member at IBM T. J.
Watson Research Center, and worked on mmWave phased
arrays for multi-Gb/s data links and airborne radar. In 2012
he joined Oregon State University as an assistant professor
in the School of Electrical Engineering and Computer Sci-
ence. His current research is focused on low-power RF
transceivers for IoT as well as mmWave and sub-mmWave
circuits and systems for wireless communication. He
received the National Talent Search Scholarship from the
Government of India (1995–2000), the Caltech Atwood Fel-
lowship in 2001, the Analog Devices Outstanding Student
IC Designer Award in 2004, the IBM Research Fellowship in
2005, and the 2011 Pat Goldberg Memorial Award for Best
Paper in CS/EE/Math in IBM Research.
BODHISATWA SADHU is currently a research staff member at IBM
T. J. Watson Research Center. He received his Ph.D. degree in
electrical engineering from the University of Minnesota, Min-
neapolis, in 2012. For his Ph.D., he worked on wideband cir-
cuits and architectures for software defined radio applications.
Since 2012, he has been working on frequency synthesizers
and mmWave transceivers in the RF/mm-wave Communica-
tions Circuits group at IBM Research. He has authored and co-
authored more than 30 papers, authored the book Cognitive
Radio Receiver Front-Ends — RF/Analog Circuit Techniques
(Springer, 2014), and holds 5 issued U.S. patents with 15+
pending. He was the recipient of the University of Minnesota
Graduate School Fellowship, 2007, 3M Science and Technology
Fellowship, 2009, and the University of Minnesota Doctoral
Dissertation Fellowship, 2011.
DUIXIAN LIU received his Ph.D. degree in electrical engineering
from the Ohio State University, Columbus, in 1990. From 1990
to 1996, he was with Valor Enterprises Inc., Piqua, Ohio, initial-
ly as an electrical engineer and then as chief engineer, during
which time he designed an antenna product line ranging from
3 MHz to 2.4 GHz for the company, a very important factor
for the prestigious Presidential “E” Award for Excellence in
Exporting in 1994. Since April 1996, he has been with the IBM
T. J. Watson Research Center as a research staff member. He
has received three IBM Outstanding Technical Achievement
Awards and one Corporate Award, IBM’s highest technical
award. He was named a Master Inventor in 2007. He has edit-
ed a book, Advanced Millimeter-Wave Technologies — Anten-
nas, Packaging and Circuits (Wiley, 2009) and is a Section
Editor for an upcoming Springer antenna handbook (2015). He
has authored or coauthored more than 100 journal and con-
ference papers. He received the 2012 S. A. Schelkunoff Prize
Paper Award of the IEEE Antennas and Propagation Society.
He has 71 patents issued or pending. His research interests are
antenna design, chip packaging, and communications tech-
SCOTT K. REYNOLDS received his Ph.D. degree in electrical engi-
neering from Stanford University, California, in January 1988.
He joined IBM in 1988, where he worked on a wide variety of
IBM products, including ICs for disk drive channels, electrical
and optical I/O, and RF communication. Beginning in 2003, he
was engaged in development of silicon millimeter-wave ICs
and packaging for high-data-rate wireless links and other
applications, including imaging. He has more than 30 U.S.
patents and many technical publications, including two papers
on 60 GHz wireless transceiver circuits that won the best paper
awards at ISSCC in 2004 and 2006. He went on to manage
the RF Circuits and Systems group at IBM Research from 2010
to 2013. In 2013, he left IBM to start his own business, Tavish
Design, LLC. He continues to consult for IBM on millimeter-
wave IC design and packaging.
GU1_LAYOUT.qxp_Author Layout 3/31/15 3:16 PM Page 204
  • Article
    In this paper, the beam-steering characteristics of photoconductive dipole phased array antenna coniguration at 1.95 THz is presented. The proposed array antenna coniguration with frequency selective surface favourably improves its gain and directivity which is useful to upsurge the imaging capabilities to address the deliberations such as limited depth-of-ield (DoF) and size-weight-and-power of the THz source for imaging applications. These are important considerations for applications like stand-of imaging and surveillance of moving targets where the high angular resolution as well as extended DoF are the important parameters for successful detection of concealed explosives. The projected planar proile and compact highly directive (2 × 2) small-gap photoconductive dipole phased array antenna can be castof for the exposure of concealed explosives such as RDX, TNT, and HMX which illustrate their substantial spectral absorption ingerprints in terahertz (1.4–2.2 THz) regime of the spectrum. A simple method of beam-steering has been explored based on phase controlled optical excitation of highly directive small-gap photoconductive dipole array antenna. Further, the efects of uniform progressive phase shift on the beam-steering of uniform linear array (along x-axis) as well as planar array (x-axis and y-axis) is investigated
  • Article
    Full-text available
    This paper presents a new implementation of the beam-steerable two-dimensional phased antenna array for the forthcoming 5G networks. The antenna enables easy integration of phase shifters and other active electronics on a single PCB, low-loss feed network, low profile, and beam steering in both azimuth and elevation plane. In addition, the antenna is scalable in the number of elements and it can be made compatible with low-cost mass production in plastic injection molding with a metal coating. The antenna consists of a rectangular waveguide feed network, waveguide-to-PCB transitions, phase shifters on a PCB, and horn antenna radiating elements. The parts have been first designed and simulated individually and the operation of the whole structure is then verified by electromagnetic simulations. The phase shifter used in this work is a meandered microstrip line section, but the structure also enables the implementation of active phase shifters. A four-by-four antenna array prototype was manufactured. The beam-steering properties of the phased antenna array have been tested with radiation pattern measurements at 72.5 GHz, and the measured gains are compared with the simulated ones. The measured gains are 15.2 and 11.2 dBi for the boresight beam, and the beam was steered to 40°.
  • Article
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  • Article
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  • Article
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  • Article
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  • Article
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  • Article
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