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Implementation of the complete predictor for DDR3 SDRAM
Abstract
In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They can suppress the latencies when accessing cache or main memory. In our previous work we proposed predictors that not only close the opened DRAM row but also predict the next row to be opened, hence the name 'Complete Predictor'. It requires less than 10 kB of SRAM for a 2GB SDRAM system. In this paper we evaluate how much additional hardware is needed and whether the activations of the predictors will slow down the DRAM controller. Copyright © 2014 The Institute of Electronics, Information and Communication Engineers.
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In the arsenal of resources for improving computer memory system
performance, predictors have gained an increasing role in the past few
years. They enable hiding the latencies when accessing cache or main
memory. In our previous work we proposed a DDR SDRAM controller with
predictors that not only close the opened DRAM row but also predict the
next row to be opened. In this paper we explore the possibilities of
trying the same techniques on the latest type of DRAM memory, DDR3
SDRAM, with further improvements of the predictors.