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214 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
A Fully-Implantable Cochlear Implant SoC With
Piezoelectric Middle-Ear Sensor and Arbitrary
Waveform Neural Stimulation
Marcus Yip, Rui Jin, Student Member, IEEE, Hideko Heidi Nakajima, Konstantina M. Stankovic, and
Anantha P. Chandrakasan, Fellow, IEEE
Abstract—A system-on-chip for an invisible, fully-implantable
cochlear implant is presented. Implantable acoustic sensing is
achieved by interfacing the SoC to a piezoelectric sensor that de-
tects the sound-induced motion of the middle ear. Measurements
from human cadaveric ears demonstrate that the sensor can detect
sounds between 40 and 90 dB SPL over the speech bandwidth.
Ahighly-reconfigurable digital sound processor enables system
power scalability by reconfiguring the number of channels, and
provides programmable features to enable a patient-specificfit.
A mixed-signal arbitrary waveform neural stimulator enables
energy-optimal stimulation pulses to be delivered to the auditory
nerve. The energy-optimal waveform is validated with in-vivo
measurements from four human subjects which show a 15% to
35% energy saving over the conventional rectangular waveform.
Prototyped in a 0.18 µm high-voltage CMOS technology, the
SoC in 8-channel mode consumes 572 µW of power including
stimulation. The SoC integrates implantable acoustic sensing,
sound processing, and neural stimulation on one chip to minimize
the implant size, and proof-of-concept is demonstrated with
measurements from a human cadaver ear.
Index Terms—Arbitrary waveform, cochlear implant, en-
ergy-efficient, hearing loss, implantable, low-voltage, microphone,
middle ear, piezoelectric, reconfigurable, SoC, stimulation,
ultra-low-power.
I. INTRODUCTION
AS OF 2010, over 30 million people in the United States
suffer from sensorineural hearing loss [1] which arises
from disease in the inner ear or auditory nerve. For mild cases of
hearing loss, a hearing aid may provide adequate compensation.
However, for profound cases (i.e., greater than 90 dB of loss), a
cochlear implant (CI) is necessary to restore hearing.
CIs use electronics to directly stimulate the auditory nerve
fibers, thus bypassing the damaged hair cells in the cochlea.
Today’s state-of-the-art CIs consist of an external and internal
Manuscript received April 23, 2014; revised July 04, 2014; accepted August
20, 2014. Date of publication September 25, 2014; date of current version De-
cember 24, 2014. This paper was approved by Guest Editor Yogesh Ramadass.
This work was supported by NSERC and the Bertarelli Foundation.
M.Yip,R.Jin,andA.P.Chandrakasan are with the Microsystems Tech-
nology Laboratories, Massachusetts Institute of Technology, Cambridge, MA
02139 USA (e-mail: anantha@mtl.mit.edu).
H. H. Nakajima and K. M. Stankovic are with Harvard Medical School,
Boston, MA 02115 USA, and also with the Eaton Peabody Laboratory,
Massachusetts Eye and Ear Infimary, Boston, MA 02114 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2014.2355822
Fig. 1. Block diagram of a conventional cochlear implant.
unitasshowninFig.1.Theexternal unit comprises a micro-
phone to pick up sound, a sound processor to digitize and com-
press the sound into coded signals, and a transmitter to send
data wirelessly to the internal unit via a coil. The external unit
also houses the battery which supplies power wirelessly to the
implanted unit via the same coil that is used for data. Without
a continuous transfer of power (e.g., if the external unit is re-
moved), the implanted unit is unpowered and does not func-
tion. The implanted unit comprises a receiver and stimulator
unit embedded in the skull, and an electrode array implanted
in the cochlea. Pulses of electrical current are modulated by the
received codes and delivered to the electrode array, triggering
action potentials in the auditory nerve which are interpreted by
the brain as sound.
Although today’s CIs are very successful in restoring hearing
for many of the profoundly deaf, the external component results
in several limitations. The device is cumbersome to wear, and
it cannot be worn in the shower or while participating in water
sports. It also raises concerns with aesthetics and social stigma.
These reasons motivate the development of a fully-implantable
cochlear implant (FICI) that is internalized and invisible.
A FICI has three main requirements that are distinct from a
conventional CI. First, a FICI that is completely untethered (i.e.,
without a coil that continuously provides power) requires an im-
planted battery that is rechargeable because of the volume and
power consumption constraints of the FICI, as well as the need
0018-9200 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 215
to avoid future surgeries for battery replacement. The number
of charges per day must also be limited to once or twice a day
to minimize user impact. As a result, a FICI requires ultra-
low-power sound processing and energy-efficient neural stim-
ulation. Secondly, recent state-of-the-art ICs are typically de-
signed for external microphone-based CIs and do not require
the neural stimulator to be on the same chip [2], [3]. In contrast,
thesizeofaFICIcouldbenefit from monolithic integration of
the signal processing and stimulation circuits. Thirdly, an im-
plantable acoustic sensor with adequate sensitivity and band-
width is required to replace the external microphone.
This paper presents a system-on-chip (SoC) for a FICI
that addresses the above issues. First, low-power implantable
acoustic sensing is achieved by interfacing the SoC to a piezo-
electric sensor that is mounted at the umbo of the malleus within
the middle ear, and this is demonstrated with measurements
from human cadaveric temporal bones. Second, a highly-re-
configurable sound processor enables system power scalability
by scaling the number of spectral channels. Third, simulations
with a computational auditory nerve fiber model from [4] are
used to determine energy-optimal biphasic stimulation wave-
forms [5], which are delivered to the nerves in the cochlea with
an arbitrary waveform neural stimulator. The energy savings
from alternate stimulation waveforms are validated in-vivo in
four human CI subjects with loudness perception tasks. The
resulting stimulation power savings over the conventional
rectangular pulse transfer directly to overall system power
savings because stimulation power typically dominates [5].
The SoC integrates an implantable acoustic sensor front-end,
sound processor, and neural stimulator on one chip to minimize
the implant size and demonstrate proof-of-concept for a FICI.
It should be noted that the wireless charger and power manage-
ment unit is not included in the scope of this work.
Section II presents the requirements and architecture of the
FICI. Section III describes the implantable acoustic sensor and
the front-end circuit implementation, and Section IV discusses
the reconfigurable sound processor design. Section V discusses
energy-efficient neural stimulation waveforms, and presents de-
tails of the stimulator architecture. Section VI presents proto-
type measurement results, Section VII discusses potential use
cases and future work, and Section VIII concludes the paper.
II. SYSTEM REQUIREMENTS AND ARCHITECTURE DESCRIPTION
This section highlights the main high-level requirements and
specifications of the system, and describes the system architec-
ture of the FICI.
A. System Requirements
1) Power Consumption: Ultra-low power consumption can
ease energy storage requirements which can translate to pos-
sible size reduction of the implant, or increased time between
recharge. Lithium-ion batteries possess high energy density but
suffer from limited (on the order of 1000’s) recharge cycles
which would eventually necessitate replacement via surgery.
Ultra-capacitors, on the other hand, can be cycled on the order of
10 times and may be more suitable for an implantable system
provided that the limited energy density still permits a one-
charge-per-day usage model. For a 5 gram ultra-capacitor with
an energy density of 5 W hr/kg, 12 hours of continuous usage
would require the FICI to consume just 1 mW of power as-
suming 50% conversion efficiency in the power management
unit. The majority of the 1 mW power budget will be consumed
by the electrode impedance and electrode drivers [6] during the
process of electrically stimulating the auditory nerve. Assuming
typical stimulation power of approximately 750 W [2], [3],
this leaves approximately 250 W for the implantable sensor
front-end circuits and sound processor.
2) Implantable Acoustic Sensor: A key enabler for a FICI
system is an implantable acoustic sensor that is able to sense
external sound pressure waves from within the body. Recently,
totally invisible middle ear implants (MEIs) have been devel-
oped to treat conductive hearing loss1[7], [8]. MEIs typically
use an implantable sensor to detect the mechanical motion of
the ossicles, using the ear as a natural microphone. The sensor
readout can be amplified and fed to an output transducer which
drives the stapes (the stirrup-shaped bone of the ossicles) with
increased vibration to compensate for hearing loss [7]. In this
work, we apply the sensors found in MEIs to a FICI system;
instead of driving the output transducer of a MEI, we use the
sensor readout as an input to the sound processor of a FICI
which stimulates the cochlea directly.
Prior work on implantable sensors has looked at MEMS
accelerometers, but they have limited sensitivity and require
milli-Watt power consumption [1]. Alternative approaches
include magnetic sensors [9] and subcutaneous microphones
[10], but they suffer from incompatibility with magnetic reso-
nance imaging (MRI) and unwanted body noise respectively.
This work leverages a piezoelectric sensor [8] because of its
small size, low-power operation, and superior sensitivity.
Considering that the loudness of normal conversational
speech is around 60 to 70 dB SPL2[1], [11] and that the
dynamic range of speech can be up to 50 dB [12], the sensor
should be able to detect sounds from 40 dB SPL (quiet library)
to 90 dB SPL (busy roadside). Furthermore, the sensor should
also support a bandwidth that spans the frequencies specificto
cochlear implant hearing from a few hundred Hz up to 5 kHz
[13], [14].
3) Number of Spectral Channels: The choice of the number
of spectral channels should strike a balance between the speech
recognition performance of CI users and the hardware com-
plexity and power consumption in a FICI. In [15], Shannon et
al. used acoustic simulations with normal hearing listeners in
quiet and showed that as few as 3 to 4 channels of spectral in-
formation can result in good speech recognition performance. A
similar study with CI users in quiet was presented in [16] where
the authors found that the average performance improved as the
number of stimulation electrodes was increased from 1 to 4, but
no differences were observed between 7-, 10-, or 20-electrode
1Conductive hearing loss occurs when there is damage to the middle ear
which blocks the conduction of sound waves toward the inner ear (cochlea). In
contrast, sensorineural hearing loss occurs when there is damage to the cochlea.
MEIs treat conductive hearing loss only and require the cochlea to be intact and
functional, whereas CIs are used to treat sensorineural hearing loss.
2Sound pressure level (SPL) in units of dB SPL is a logarithmic measure of
sound pressure with respect to a reference of Pa .
216 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
Fig. 2. Block diagram of the fully-implantable cochlear implant SoC.
processors. For CI users in noise, the best CI listeners improved
their performance only up to 7 electrodes, while CI users with
low levels of speech recognition did not benefitfrommorethan
4 electrodes [17]. Although user performance depends also on
the speech processing strategy, the effective number of spec-
tral channels possible with electrically-evoked hearing is usu-
ally limited by the current spreading between electrodes [18]. In
this work, the target number of channels is 8 which provides ad-
equate spectral resolution while minimizing the hardware com-
plexity for a proof-of-concept system.
B. Architecture Description
A block diagram of the proposed SoC is shown in Fig. 2
[19]. The system is separated into three main subsystems: 1) a
piezoelectric sensor front-end (PZFE), 2) a low-voltage recon-
figurable sound processor, and 3) an energy-efficient arbitrary
waveform neural stimulator and high-voltage electrode switch
matrix.
The PZFE conditions the signal from the sensor which is a
measure of the sound-induced motion of the umbo. The PZFE
operates from a 1.5 V analog supply and comprises three stages:
achargeamplifier (CA) to interface to the piezoelectric sensor,
a programmable-gain amplifier (PGA), and a single-ended to
differential ADC driver. A mid-rail reference voltage bi-
ases the sensor and sets the DC operating point of the PZFE.
The ADC driver stage also provides DC level shifting from
mV down to mV which is the input
common-mode of the ADC. The signal is then digitized by a
fully-differential low-power 16 kS/s 9 bit successive approx-
imation register (SAR) ADC operating from a digital supply
voltage of 0.6 V [20].
The ADC output is processed by a 0.6 V reconfigurable sound
processor that implements the well-known Continuous Inter-
leaved Sampling (CIS) sound processing strategy [21] in which
each electrode is stimulated synchronously in an interleaved
manner with an amplitude determined by the output of each
channel of the processor. The interleaved stimulation drastically
reduces interaction between electrodes which allows for a high
rate of stimulation that is important for preserving temporal in-
formation in speech [15].
The processor in this work is designed to be extremely re-
configurable in order to enable system power scalability as well
as patient-specificfitting capability. First, the number of chan-
nels can be configured to 8, 6, or 4 to enable a power-perfor-
mance tradeoff. The filter bank has reconfigurable coefficients
to adjust the filter bandwidths for the three modes of operation,
and multi-rate signal processing is leveraged to reduce power
and area. The bandwidth of the processor covers 300 Hz to
5.5 kHz, and the filter cut-off frequencies of the logarithmi-
cally-spaced channels are based on [13], [14] to emulate the
tonotopic structure of hearing. Furthermore, processor settings
like global channel gain, type of rectification, and amount of
compression are all programmable. The processor also has the
capability to adjust the volume level for each channel individ-
ually to provide additional patient fitting capability. The pro-
cessor outputs 6 bit data at an analysis rate of 1 kHz, which
represents the logarithmically compressed energy in each fre-
quency band. This value is used to modulate a train of electrical
current pulses (1,000 pulses/sec per electrode) that is delivered
to the corresponding electrode.
The interleaved operation of the CIS strategy conveniently
allows for a single current source to be interleaved between all
electrodes. This is accomplished by using a high-voltage elec-
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 217
Fig. 3. (a) Block diagram and (b) photograph of the measurement setup and discrete prototype used to characterize the piezoelectric sensor mounted on the middle
ear of a human cadaveric temporal bone.
trode switch matrix to select the active electrode and control the
direction of current flow. The SoC is designed to be used with
monopolar electrode arrays, where a common return electrode
is used to provide a return path for all electrodes. Furthermore, a
0.6 V digital controller provides the control signals for the cur-
rent DAC and switch matrix which allows the waveform of the
stimulationpulsestobeprogrammedtoanyarbitraryshape.
The stimulator has high voltage compliance in order to
accommodate up to 1 mA of stimulation current through the
electrode-tissue interface which may have a few kilo-Ohms
of impedance. The stimulation current is drawn from a high
voltage supply ( 5 V to 10 V), and the switch matrix
is driven with high-voltage logic operating from 7V
to 12 V. Level shifters are used to interface between the 0.6 V
and domains. Lastly, the current DAC circuits operate
from a supply voltage of 3.3 V.
III. IMPLANTABLE PIEZOELECTRIC ACOUSTIC SENSOR
This section first describes the characterization of the piezo-
electric sensor on the middle ear of a human cadaveric tem-
poral bone using a discrete prototype, followed by the design
and analysis of the sensor front-end of the SoC.
A. Sensor Characterization
In order to investigate the performance of the middle-ear
mounted piezoelectric sensor, human cadaveric temporal bones
were provided by the Eaton-Peabody Laboratory at the Mass-
achusetts Eye & Ear Infirmary (Boston, MA), and PZT-5A
piezoceramic material (Piezo Systems Inc., Woburn, MA) was
used. A block diagram of the prototype and measurement setup
is shown in Fig. 3(a). Swept-sine measurements were made
using an audio amplifier and speaker connected to a probe tube
that funnels sound into the ear canal of the temporal bone. Ear
canal pressure ( ) and umbo velocity ( ) were mon-
itored with a probe microphone and laser Doppler vibrometer
(Polytec) respectively. A discrete prototype was used to record
the output voltage of the sensor ( ). All three outputs were
recorded by LabVIEW and the transfer characteristics from
to to were calculated.
Fig. 3(b) shows the photograph of the measurement setup.
The temporal bone is held by a specimen holder and the sensor
is positioned by a micro-manipulator external to the bone. The
sensor is clamped at one end like a cantilever, while the other
end is placed at the umbo of the malleus. As the umbo vibrates
back and forth, it exerts a force that bends the sensor which in
turn generates a charge across its terminals which is converted
to an output voltage by a charge amplifier.
Fig. 4(a) and (b) show that the measured umbo velocity and
sensor readout are very linear with the sound pressure level in
the ear canal. Fig. 4(c) shows the measured output spectrum of
thechargeamplifier from 200 Hz to 10 kHz and it can be seen
that the sensor is able to detect sounds over a 50 dB dynamic
range from 40 to 90 dB SPL.
B. Piezoelectric Sensor Front-End
The details of the 3-stage PZFE of the SoC are shown at the
top of Fig. 2, where the piezoelectric sensor is modeled as a
Thevenin voltage source and series capacitance .Since
the charge amplifier of the first stage dominates the noise per-
formance of the front-end, its signal transfer function and noise
analysis is provided next.
1) Charge Amplifier Transfer Function: Fig. 5(a) shows the
charge amplifier (stage 1) of the PZFE with noise sources, and
Fig. 5(b) shows the equivalent block diagram, where , ,
and are the noise from ,, and the op-amp respectively,
and is the open-loop transfer function of the op-amp. In
order to determine the transfer function from the piezoelectric
sensor voltage tothechargeamplifier output , the charge
amplifier input voltage can be referred back to through
the following transfer function, ,
where . For the frequencies of interest where the
loop gain is large, the closed-loop transfer function is given by
where .
Therefore, the transfer function of stage 1 from to is given
by
(1)
which gives the desired band-pass characteristic necessary to
pass only the frequencies relevant to speech for a CI (300 Hz
to 6 kHz). The high-pass and low-pass corners are set by
and respectively, and the mid-band gain is simply
218 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
Fig. 4. (a) Umbo velocity and (b) charge amplifier output voltage versus ear canal sound pressure at 0.5, 1, 2, and 4.7 kHz. (c) Spectrum of the charge amplifier
output for sound pressure levels from 40 to 90 dB SPL.
Fig. 5. (a) Equivalent circuit for the charge amplifier including noise sources, and (b) the corresponding block diagram.
for . Note that the negative polarity of the charge am-
plifier has been ignored here for simplicity. To accommodate a
range of typical sensor sizes ( 0.2 to 3 nF), is a 3 bit
switched-capacitor tunable from 6 pF to 66 pF which provides
programmable gain in 3 dB steps, and is set to 88.4 M such
that (300 Hz) for all values of . Finally, is a 4 bit
switched-resistor with logarithmically-spaced values from 1 k
to 100 k to ensure (6 kHz) for typical values of .
2) Charge Amplifier Noise Analysis: The noise transfer
functions referred to can be determined by calculating the
noise transfer function to the output andthendividingby
.For , the noise transfer function referred to is
which evaluates to
(2)
for . As a result, the noise spectral density of referred
to is
(3)
Following similar analysis, the noise spectral density of re-
ferred to is . Finally,
the noise transfer function of the op-amp referred to is
(4)
for ,where since
. Therefore, the noise of the op-amp is magnified by
which is more dominant at lower frequencies.
From the above analysis, it can be seen that the noise spec-
tral density of ,, and the op-amp thermal noise all have
acharacteristic, and that the resistor noise is reduced for
larger values of . However, the op-amp noise is independent
of because it depends on which is generally
chosen to be fixed. For typical values of ,thenoisefrom
is negligible because of its large value, and the relative contribu-
tions of noise from and the op-amp vary depending on .
The total integrated noise from simulation for nF and
3nFare2.5 Vand 1.7 Vrespectively, which are lower
than the minimum expected signal of approximately 3 Vat
40 dB SPL as determined by the discrete prototype.
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 219
Fig. 6. Block diagram of the 0.6 V digital reconfigurable multi-rate CIS sound processor.
IV. RECONFIGURABLE SOUND PROCESSING
The sound processor in this work implements the CIS sound
processing strategy [21] because it is the most ubiquitous
strategy among CI manufacturers. The two main objectives for
the design of the sound processor are 1) ultra-low-power op-
eration and 2) highly-reconfigurable features to enable system
power scalability and patient-specificfitting capability. The first
goal is accomplished by leveraging ultra-low-voltage digital
processing at 0.6 V to maximize energy-efficiency. The second
goal is addressed with a flexible digital architecture featuring a
multi-rate reconfigurable filter bank and highly-programmable
processor parameters.
The block diagram of the reconfigurable CIS sound processor
is shown in Fig. 6. The processor spectrally decomposes the
signal with a logarithmically-spaced multi-rate filter bank to
emulate natural hearing. The envelope of each filter output is
extracted, downsampled, and logarithmically-compressed to fit
the patient’s electric hearing dynamic range, and each channel
has patient-specific volume settings. By clock-gating the unused
channels, both the processor power and stimulator power (which
dominates the SoC power) scale linearly with the number of
channels.
A. Programmable Features
Aside from being able to select between 8-, 6-, or 4-channel
modes, other programmable processor parameters can affect the
user performance and power consumption of the CI and they are
highlighted next.
•Rectification: The type of rectificationusedintheen-
velope detector can affect speech recognition scores and
sound quality [14], and therefore both full-wave (default)
and half-wave rectification are possible. Half-wave rectifi-
cation has the potential to reduce stimulation power since
the average envelope is smaller, but at the cost of poten-
tially lower sound quality [14].
•Channel gain and compression factor: Following enve-
lope detection, global gain and dynamic range compression
are applied. The global gain can be set in octaves from
to with 3 bits, and the signal is compressed according to
,where is the compres-
sion factor. Logarithmic compression is needed because
of the well-known loudness growth function of electrical
hearing which shows a linear relationship between sound
intensity in dB SPL and electrical stimulation intensity in
Amperes. Evidence shows that different amounts of com-
pression can be beneficial [12], and therefore three settings
are available: (default), 128, and 16. For low
compression ( ), the stimulation power is roughly
linear with gain, while for high compression ( ),
the stimulation power scales linearly with the logarithm of
the gain.
•Volume settings: Each channel has individual threshold
(THR) and most-comfortable-level (MCL) settings that
can be used to fit the dynamic range of the stimulus current
for each electrode based on the user. Each channel has 3 bit
programmability in both THR and MCL, and stimulation
power increases with higher THR and MCL settings.
B. Reconfigurable Filter Bank Architecture
A logarithmically-spaced filter bank requires higher fre-
quency channels to be wider in bandwidth, while low frequency
channels need to be narrow and more selective (i.e., higher
220 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
Fig. 7. Structure of the reconfigurable FIR filter (Type 3) used for channels A, C, E, G that can be reconfigured into 3 modes: 14-, 16-, and 20-tap used in 4-, 6-,
or 8-channel modes.
filter order). In this work, high order filters are avoided by
using multi-rate signal processing to achieve the narrow low
frequency filters in a power- and area-efficient manner. As
shown in Fig. 6, the ADC data is decimated in 3 stages using
efficient 19-tap half-band FIR filters, resulting in data rates of
2, 4, 8, and 16 kHz which are used for channels A/B, C/D, E/F,
and G/H respectively.
The filter bank is implemented with FIR filters for their linear
phase which can have a positive effect on sound quality and
speech intelligibility. When the sound processor is configured
in 8-channel mode, all channels are active. In 6- and 4-channel
modes, the subsets of channels (D, H) and channels (B, D, F,
H) are clock-gated respectively. The cut-off frequencies of the
individual filters vary with the channel mode and they are based
on [13], [14].
In order to achieve reconfigurability in the filter responses,
the filter bank leverages three types of FIR filters with different
levels of reconfigurability. Fig. 7 shows the most reconfigurable
filter (Type 3) which can be programmed to three different filter
lengths: 14, 16, or 20 taps used in the 4-, 6-, or 8-channel mode
(using control signals ,,and )toad-
just the frequency selectivity. Since the filters are symmetric,
the filter is folded to reduce the number of multiplications by
half. The coefficients are quantized to 8 bit precision which is
the minimum possible without significantly affecting the de-
sired frequency response, and word lengths are optimized for
the given coefficients.
The Type 3 FIR filter is used for channels A, C, E, and G
which are active for all three modes. The Type 2 FIR filter used
for channels B and F has two levels of reconfigurability and can
be programmed to have either 16 or 20 taps used in the 6- or
8-channel modes only. Finally, the Type 1 FIR filter used for
channels D and H is a fixed 20-tap filter because it is used in the
8-channel mode only.
Finally, taking channel A for example, it can be shown that
its effective filter response at kHz is given by
(5)
where and represent the half-band and channel
AFIRfilters at their respective downsampled data rates. Al-
though is only a 20-tap filter (in 8-channel mode), the
effective filter order is much higher because of multi-rate signal
processing. The effective frequency responses of the filter bank
(at kHz) reconfigured in 4-, 6-, and 8-channel modes
are shown in Fig. 8.
V. ENERGY-EFFICIENT ARBITRARY WAVE F O R M
NEURAL STIMULATOR
In this section, we consider the design of the neural stim-
ulator which delivers electrical current to the nerve fibers of
the cochlea. The typical power consumption of the stimulator
can often be a few milli-Watts [3], [22] which can represent
greater than 90% of the total SoC power given that the PZFE and
sound processor have micro-Watt power consumption. There-
fore, any power savings in the stimulator translate directly to
overall system power savings.
A. Computational Nerve Fiber Simulations
Most neural stimulators today deliver charge-balanced
biphasic rectangular current pulses as shown by the green curve
in Fig. 9(a), where the first (cathodic) phase excites the nerve
fiber and the second (anodic) phase provides charge balancing.
The rectangular waveform has been widely adopted for its
simplicity and ease of generation with a simple current source.
However, studies have shown that alternate waveforms have
the potential to excite nerves with reduced energy [5], [23].
Based on [5], a heuristic search was applied to a computational
model of an auditory nerve [4] to seek out an energy-optimal
waveform with CI-specific parameters.3The waveform was
constrained to be charge-balanced with 10 time steps/phase, but
unlike [5], no constraint was placed on the shape of either phase
of the pulse to allow both phases to be co-optimized. Fig. 9(a)
(blue curve) shows the energy-optimal waveform after 10,000
search iterations at a phase width of 25 s, and it is 28% more
energy-efficient than the conventional rectangular waveform
at threshold. The energy-optimal waveform in this work is
somewhat different from the truncated Gaussian shapes in [5]
which may be attributed to a different nerve fiber model as well
as the lack of constraint on the shape of the anodic phase.
3Typical CIs use biphasic waveforms with a phase width between 25 and
50 s.
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 221
Fig. 8. Effective frequency response of the multi-rate filter bank at 16 kHz reconfigured in (a) 4-channel, (b) 6-channel, and (c) 8-channel modes.
Fig. 9. (a) Energy-optimal stimulation waveform at 25 sfrom the heuristic search using the computational nerve fiber model. Rectangular and exponen-
tial waveforms are included for comparison. (b) Perceived loudness versus energy delivered per phase from four human subjects.
B. Validation With In-Vivo Measurements
In order to validate the modeling results and determine
the impact of alternate waveforms on auditory perception in
humans, the rectangular waveform was compared against the
exponential waveform shown in Fig. 9(a) by conducting a
psychophysical loudness perception test on four subjects with
Advanced Bionics CIs.4The exponential waveform was used
4Tests were conducted under the Massachusetts Eye & Ear Infirmary IRB
protocol #94-01-003.
because it mimics the optimal waveform closely in the cathodic
phase, but the anodic phase was constrained to be symmetric
to the cathodic phase due to test limitations. The waveforms
were alternated in pseudo-random order, and the amplitude was
swept from threshold to just beyond the maximum comfortable
level (CL) in 50 A steps on a middle electrode. The subjects
were asked to rate the loudness on a scale of 0 to 25, with 8
and 22 being the minimum and maximum CL respectively.
Fig. 9(b) shows the average perceived loudness of both wave-
forms versus the energy delivered (per Ohm of the electrode
222 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
Fig. 10. (a) Schematic of the high-voltage electrode switch matrix during the cathodic phase of electrode 2. (b) Schematic of the fast-settling 6 bit current steering
DAC.
Fig. 11. Timing diagram for the digital control of the electrode switch matrix.
resistance) for each of the 4 subjects. Overall, to achieve the
same loudness within the comfortable range between 8 and
22, the alternate exponential waveform requires approximately
15% to 35% less energy than the rectangular waveform.
C. Arbitrary Waveform Stimulator Architecture
Basedonthenervefiber simulations and in-vivo measure-
ment validation of alternate waveforms, this section describes
the architecture of the arbitrary waveform stimulator in the SoC.
1) High-Voltage Electrode Switch Matrix: The CIS sound
processing strategy permits a single current DAC to be inter-
leaved among all electrodes using the high-voltage switch ma-
trix shown in Fig. 10(a). The terminals of the intracochlear elec-
trodes are designated by (for 1to8), and is the
common return electrode of a monopolar electrode array. A
high-frequency electrode model between and
models the impedance of the electrode-tissue-electrode inter-
face. Electrode is active when is asserted, and the switches
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 223
Fig. 12. Ultra-low-voltage digital control of the stimulator.
, , ,and are used to control the direction of current
flow during the cathodic and anodic phases for each electrode.
During each phase, the value of the current is determined by a 6
bit current DAC ( [5:0])whichisdrivenbyadigitalwave-
form controller to realize any arbitrary waveform. Since the
switch matrix works like a H-bridge, current always flows from
to ground. In between the cathodic and anodic phases, an
optional switch ( ) can be used to insert an inter-phase gap.
Upon completion of each pulse, shorts the electrode to re-
move any residual charge. Although not pictured, a DC blocking
capacitor (220 nF) is placed in series with the electrodes to en-
sure that no DC current flows into the tissue for safety reasons.
Fig. 11 shows the timing diagram of the switch matrix con-
trol over a complete stimulation cycle. The start of each cycle
begins on the rising edge of (1 kHz) which generates a
pulse and also asserts whichisusedtoen-
able the 3.3 V supply from which the current DAC circuits op-
erate. Stimulation is enabled when is asserted, and the
electrode selection signals are generated by a state machine
that is clocked by . Note that rises half a cycle before
in order to provide adequate time for the current DAC
circuits to power up. Stimulation is complete on the positive
edge of which de-asserts and .
2) Current Steering DAC: The current DAC shown in
Fig. 10(b) is based on the voltage-controlled resistor (VCR)
topology [24] which is chosen for its high output impedance
and large voltage compliance. It provides 6 bits of reso-
lution at a full-scale of 1 mA which is typically sufficient
for CIs. Feedback ensures that the DAC current is simply
. Detailed analysis of the VCR in [24]
shows that is linear with which drives the gate of
themaintriodedevice .to are auxiliary devices
controlled by [1:3] and are used to linearize . All devices
are 3.3 V transistors except for which is a high-voltage
device that connects to the high-voltage switch matrix.
In this work, current-steering is used to achieve the settling
time required to generate arbitrary waveforms at a 25 sphase
duration with 10 steps/phase. The input code D[5:0] from the
digital waveform controller steers binary-weighted currents to
which are then mirrored to the resistor string on the output
branch. The generated control voltages [3:0] are linear with
D[5:0] as desired. Finally, the current DAC is power-gated from
3.3 V after all electrodes have been stimulated so that its power
scales linearly with the number of channels.
3) Low-Voltage Digital Waveform Controller: In order to
minimize the power overhead of arbitrary waveform genera-
tion, the digital waveform controller operates at 0.6 V, and level
shifters are used to interface to the high-voltage logic which
drives the switch matrix. Fig. 12(a) shows the electrode selec-
tion state machine that generates to and other signals
that govern the stimulation cycle. Control signals
and are used to reconfigure the state machine between
224 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
TAB L E I
MEASURED PERFORMANCE SUMMARY FOR EACH SUBSYSTEM OF THE FICI SOC
Fig. 13. Die micrograph of the prototype SoC.
channel modes. The state machine is triggered on ,andthe
signals are shifted out serially with which is a delayed
version of . This ensures that transitions just after the neg-
ative edges of and to avoid glitching in the switches. The
control signals for the switch matrix are generated by gating
and with non-overlapping clocks ,,and as
showninFig.12(b).
Finally, Fig. 12(c) shows the digital arbitrary waveform
interface that controls the shape of the pulses delivered to the
electrodes. The channel select block selects the appropriate
sound processor output (dstimX for X = A to H) based on
. While each is asserted, a step counter (cnt) running at
(a high-frequency waveform clock) keeps track of the
time step within the pulse. The value of cnt determines which
waveform weight (w00 to w15) is multiplied with dstimX to
generate D[5:0] which drives the current DAC. The shape of
the cathodic and anodic phases are determined by w00 to w07
and w08 to w15 respectively, for a maximum of 8 steps/phase.
VI. MEASUREMENT RESULTS
A prototype SoC was fabricated in a 0.18 m high-voltage
CMOS process, and the die micrograph is shown in Fig. 13.
The chip including pads measures 3.6 mm 3.6 mm, while the
activeareais3.36mm . This section presents the measured re-
sults, and a summary of the performance is provided in Table I.
A. Piezoelectric Sensor Front-End
Fig. 14(a) and (b) show the measured gain response of the
charge amplifier for 3.2 nF and 0.56 nF which span the
expected values for reasonable sizes of the sensor. Fig. 14(c)
shows the combined response of the charge amplifier and PGA
with 0.56 nF and 12 pF for various PGA settings.
Simulation results are shown with dotted lines and show good
agreement with measured results. Furthermore, the integrated
noise over the sound processor bandwidth is 2.81 Vand
1.93 Vfor 0.56 nF and 3.2 nF, respectively, which
is less than the minimum expected signal at 40 dB SPL.
B. Reconfigurable Sound Processor
To demonstrate the reconfigurability in the number of chan-
nels of the processor, a logarithmic chirp signal was applied at
the input of the ADC. Fig. 15(a) shows the measured spectro-
gram at the output of the ADC, and Fig. 15(b), (c), and (d) show
the measured spectrogram of the processor configuredin4-,
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 225
Fig. 14. Measured gain response of the charge amplifier (stage 1) of the PZFE with (a) nF and (b) nF. Panel (c) shows the combined
response of the charge amplifier and PGA (stage 1 and 2). Simulation results are shown with dotted lines.
6-, and 8-channel modes. Since the processor features a loga-
rithmically-spaced filter bank, its spectrogram looks linear as
expected. A Matlab simulation of the 8-channel processor is
shown in Fig. 15(e), showing good agreement with the mea-
sured results.
C. Energy-Efficient Arbitrary Waveform Stimulator
The measured INL and DNL are 0.21/+1.25 LSB and
0.14/+0.16 LSB, respectively which is adequate for neural
stimulation applications. Fig. 16 shows the measured current
and voltage from a model electrode ( k , nF)
for (a) a rectangular waveform and (b) the energy-optimal wave-
form for phase widths of 25 s and 50 s with 8 steps/phase.
Even though the energy-optimal waveform requires a higher
peak current than the rectangular waveform, it consumes less
energy and generates a smaller electrode voltage.
Fig. 16(c) shows a measurement of the interleaved current
pulse trains at 1,000 pulses/sec per electrode through all 8 elec-
trodes. In this measurement, the pulses are programmed to be
rectangular with a phase width of 31.25 s such that the current
DAC is active for 50% of the 1 ms period, and power-gated for
the remainder of the period.
D. Power Consumption
1) Stimulator Power: Fig. 17 summarizes the measured
stimulator power in 8-, 6-, and 4-channel modes while pro-
cessing a clip of speech with V. The measurement
also includes the power consumption of the low-voltage dig-
ital waveform controller, level shifters, current DAC, and
high-voltage switch matrix control circuits. The power in-
creases with the duty cycle of the current DAC which scales
with the phase width and number of channels. Finally, the
energy-optimal waveform provides power savings of approx-
imately 22% and 29% at phase widths of 25 s and 50 s,
respectively.
2) Overall SoC Power: Table II summarizes the total SoC
power consumption with typical speech input using the energy-
optimal waveform at 31.25 sphase and nominal processor
settings. Reconfigurability in the number of channels allows
for a power-performance tradeoff, and the SoC consumes 572,
425, and 281 W in 8-, 6-, and 4-channel modes, respectively,
Fig. 15. Measured spectrograms at the output of the (a) ADC, (b) 4-channel
processor, (c) 6-channel processor, and (d) 8-channel processor when a loga-
rithmic chirp signal is applied at the input. (e) Ideal Matlab simulation to com-
pare against the measured results shown in (d).
meeting the 1 mW requirement. In 8-channel mode, the PZFE,
SAR ADC, and sound processor consume only 2% of the the
total power, while 98% of the power is consumed by the stim-
ulator circuits. Therefore, the stimulation power savings from
the energy-optimal waveform transfer directly to the overall
system.
226 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
Fig. 16. Measured current and voltage of a model electrode ( k , nF) with (a) a rectangular waveform, and (b) the energy-optimal waveform.
(c) Measured current pulse trains at 1,000 pulses/sec through all electrodes in 8-channel mode.
TAB L E I I
SUMMARY TABLE OF THE MEASURED SOCPOWER CONSUMPTION
Fig. 17. Measured total stimulator power across 8-, 6-, and 4-channel modes
for phase widths of (a) 25 s and (b) 50 s.
E. System Demonstration With a Human Cadaveric Temporal
Bone
The FICI SoC was tested with a piezoelectric sensor mounted
at the umbo of a human cadaveric temporal bone. A function
generator and audio amplifier were used to generate a clip of
speech (“her husband brought some flowers”) which was played
into the ear canal of the temporal bone with a speaker at 70 dB
SPL. The signal from the umbo-mounted sensor was detected by
the PZFE and processed by sound processor. Fig. 18(a) shows
the spectrogram and time-domain waveform of the input speech
signal in the ear canal, and Fig. 18(b) shows the measured spec-
trogram and reconstructed sound (the reconstruction process is
based on sound synthesis in vocoder applications) from the pro-
cessor in 8-channel mode. The output from the umbo-mounted
sensor and SoC preserves the temporal envelope information of
the speech signal with the exception of some high frequency
content, demonstrating hearing with a human cadaveric ear.
VII. DISCUSSION AND FUTURE WORK
The eventual goal of a completely invisible CI will require
the development of other subsystems. Most notably, the user
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 227
Fig. 18. (a) Spectrogram and time-domain waveform of the input speech signal (”her husband brought some flowers”) to the audio amplifier driving
the speaker placed in the ear canal of the temporal bone. (b) Measured spectrogram and reconstructed sound from the SoC with the piezoelectric sensor
mounted on a cadaver temporal bone.
will need an external device (used a few times per day) ca-
pable of two key functions. First, a wireless charging system
is needed to recharge the implanted power management unit
(PMU). The charging system should be able to bring the im-
planted unit from empty to fully charged in just a few min-
utes to minimize the inconvenience to the user. In order to
increase the time between recharge, the implanted PMU must
be as efficient as possible which will require clever design
of DC-DC converters and regulators to generate the required
supply voltages for the SoC. If an ultra-capacitor is used as
the energy storage element, the PMU would have the added
requirement of being able to accommodate a terminal voltage
that will decrease with use.
The second key function of the external device would be to
provide wireless data transfer to the implanted unit to allow
the user to select from a range of programs as determined by
their audiologist. Each program could have a different combi-
nation of front-end and sound processor settings. Furthermore,
a wireless data link would also allow the user to manually se-
lect high-performance or low-power modes corresponding to
8-channel or 6/4-channel modes respectively. Alternatively, a
smart power management system could monitor the charge of a
battery or terminal voltage of an ultra-capacitor and adjust the
number of channels in the processor to extend the time before a
recharge is required.
VIII. CONCLUSION
This paper presents a SoC with an invisible middle-ear
sensor for a fully-implantable CI. First, a piezoelectric sensor
detects sound in the ear canal by converting the mechanical
motion of the middle ear into an electrical signal that is
captured by the PZFE. Measurements with human cadaveric
ears show that the sensor is capable of detecting sounds from
40 to 90 dB SPL over the bandwidth of interest. Second,
a highly-reconfigurable sound processor leverages digital
processing to provide greater programmability over analog
approaches, and enable voltage scaling down to 0.6 V to
maximize energy-efficiency. The number of channels can be
reconfigured between 8, 6, or 4 to enable a power-perfor-
mance tradeoff, and all processor settings are programmable
to ensure a patient-specificfit. Third, an auditory nerve
fiber model is used to determine an energy-optimal biphasic
stimulation waveform which was validated in-vivo with four
human CI users and shown to provide 15% to 35% energy
savings. A mixed-signal arbitrary waveform stimulator is
used to deliver energy-efficient current pulses to the auditory
nerve. In 8-channel mode, the SoC consumes just 572 Wof
power, 98% of which is attributed to the stimulator. There-
fore, the energy savings of the energy-optimal stimulation
waveform transfer directly to the overall system. The SoC
integrates implantable acoustic sensing, sound processing,
and neural stimulation on one chip to minimize the implant
size, and proof-of-concept is demonstrated by using the SoC
and umbo-mounted sensor to detect a clip of speech played
into the ear canal of a human cadaver ear.
ACKNOWLEDGMENT
The authors would like to acknowledge D. Eddington and
V. Noel for help with the stimulation waveform measurements,
D. Perreault for helpful discussion, and the TSMC University
Shuttle Program for chip fabrication.
REFERENCES
[1]D.J.Young,M.A.Zurcher,M.Semaan,C.A.Megerian,
and W. H. Ko, “MEMS capacitive accelerometer-based middle
ear microphone,” IEEE Trans. Biomed. Eng., vol. 59, no. 12,
pp. 3283–3292, Dec. 2012.
[2] W. Germanovix and C. Toumazou, “Design of a micropower current-
mode log-domain analog cochlear implant,” IEEE Trans. Circuits Syst.
II, vol. 47, no. 10, pp. 1023–1046, Oct. 2000.
[3] R. Sarpeshkar, M. W. Baker, C. D. Salthouse, J. J. Sit, L. Turicchia, and
S. M. Zhak, “An analog bionic ear processor with zero-crossing detec-
tion,” in 2005 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers,
San Francisco, CA, USA, Feb. 2005, pp. 78–79.
228 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 1, JANUARY 2015
[4] D. M. Whiten, “Electro-anatomical models of the cochlear implant,”
Ph.D. dissertation, Mass. Inst.Technol.,Cambridge,MA,USA,
2007.
[5] A. Wongsarnpigoon and W. M. Grill, “Energy-efficient waveform
shapes for neural stimulation revealed with a genetic algorithm,” J.
Neural Eng., vol. 7, no. 4, Aug. 2010.
[6] S.K.KellyandJ.L.WyattJr.,“Apower-efficient neural tissue stim-
ulator with energy recovery,” IEEE Trans. Biomed. Circuits Syst., vol.
5, no. 1, pp. 20–29, Feb. 2011.
[7]M.Barbara,V.Manni,andS.Monini,“Totallyimplantablemiddle
ear device for rehabilitation of sensorineural hearing loss: Preliminary
experience with the esteem envoy,” Acta Oto-Laryngologica, vol. 129,
no. 4, pp. 429–432, Apr. 2009.
[8] K. Kroll, I. Grant, and E. Javel, “The Envoy totally implantable hearing
system, St. Croix Medical,” Trends in Amplification, vol. 6, no. 2, pp.
73–80, 2002.
[9] A. Maniglia et al., “The middle ear bioelectronic microphone
for a totally implantable cochlear hearing device for profound
and total hearing loss,” Amer.J.Otology, vol. 20, no. 5, pp.
602–611, 1999.
[10] A. Jenkins et al., “U.S. phase I preliminary results of use of the Oto-
logics MET fully-implantable ossicular stimulator,” Otolaryng. Head
Neck Surgery, vol. 137, no. 2, pp. 206–232, Aug. 2007.
[11] C. J. James et al., Ear & Hearing, vol. 24, no. 2, pp. 157–174, Apr.
2003.
[12] F. G. Zeng et al., “Speech dynamic range and its effect on cochlear im-
plant performance,” J. Acoust. Soc. Am.,vol.111,no.1, pp. 377–386,
Jan. 2002.
[13] P. C. Loizou, M. Dorman, and Z. Tu, “On the number of channels
needed to understand speech,” J. Acoust. Soc. Am., vol. 106, no. 4, pp.
2097–2103, Oct. 1999.
[14] K. Nie, A. Barco, and F. G. Zeng, “Spectral and temporal cues in
cochlear implant speech perception,” Ear & Hearing, vol. 27, no. 2,
pp. 208–217, Apr. 2006.
[15] R. V. Shannon, F. G. Zeng, V. Kamath, J. Wygonski, and M. Ekelid,
“Speech recognition with primarily temporal cues,” Sci., vol. 270, no.
5234, pp. 303–304, Oct. 1995.
[16] K.E. Fishm an, R. V. Shannon, and W. H. Slattery, “Speech recognition
as a function of the number of electrodes used in the SPEAK cochlear
implant speech processor,” J. Speech Lang. Hear. Res.,vol.40,no.5,
pp. 1201–1215, Oct. 1997.
[17] Q. J. Fu, R. V. Shannon, and X. Wang, “Effects of noise and spectral
resolution on vowel and consonant recognition: Acoustic and electric
hearing,” J.Acoust.Soc.Am., vol. 104, no. 6, pp. 3586–3596, Dec.
1998.
[18] A. Faulkner, S. Rosen, and L. Wilkinson, “Effects of the number
of channels and speech-to-noise ratio on rate of connected
discourse tracking through a simulated cochlear implant speech
processor,” Ear & Hearing, vol. 22, no. 5, pp. 431–438,
Oct. 2001.
[19] M. Yip, R. Jin, H. H. Nakajima, K. M. Stankovic, and A. P.
Chandrakasan, “A fully-implantable cochlear implant SoC with
piezoelectric middle ear sensor and energy-efficient stimulation
in 0.18 m HVCMOS,” in 2014 IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers,SanFrancisco,CA,USA,Feb.2014,
pp. 312–313.
[20] M. Yip and A. P. Chandrakasan, “A resolution-reconfigurable
5-to-10-bit 0.4-to-1 V power scalable SAR ADC for sensor applica-
tions,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1453–1464,
Jun. 2013.
[21] B. S. Wilson, C. C. Finley, D. T. Lawson, R. D. Wolford, D. K.
Eddington, and W. M. Rabinowitz, “Better speech recognition with
cochlear implants,” Letters to Nature, vol. 352, pp. 236–238, Jul.
1991.
[22] J. Georgiou and C. Toumazou, “A 126- W cochlear chip for a totally
implantable system,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp.
430–443, Feb. 2005.
[23] M. Sahin and Y. Tie, “Non-rectangular waveforms for neural stim-
ulation with practical electrodes,” J. Neural Eng., vol. 4, no. 3, pp.
227–233, Sep. 2007.
[24] M. Ghovanloo and K. Najafi, “A compact large voltage-compliance
high output-impedance programmable current source for implantable
microstimulators,” IEEE Trans. Biomed. Eng.,vol.52,no.1,pp.
97–105, Jan. 2005.
Marcus Yip (M’13) received the B.A.Sc. degree in
engineering science from the University of Toronto,
Toronto, ON, Canada, in 2007, and the M.S. and
Ph.D. degrees from the Massachusetts Institute of
Technology, Cambridge, MA, USA, in 2009 and
2013, respectively.
He has held internships at Actel Corporation,
Snowbush Microelectronics, Texas Instruments, and
OnChip Power Corporation. His research interests
include low-power sensor front-ends, reconfigurable
analog-to-digital converters, and mixed-signal
circuits and systems for wearable and implantable medical applications.
Dr. Yip received the Natural Sciences and Engineering Council of Canada
(NSERC) postgraduate fellowship from 2007 to 2011.
Rui Jin (M’13) received the S.B. degree in electrical
engineering and the M.Eng degree in electrical en-
gineering and computer science from the Massachu-
setts Institute of Technology, Cambridge, MA, USA,
in 2013 and 2014, respectively.
His research interests include wireless power elec-
tronics, energy-efficient sensors, and emerging appli-
cation prototyping.
Hideko Heidi Nakajima received the B.S., M.S.,
and Ph.D. degrees in biomedical engineering from
the Boston University College of Engineering,
Boston, MA, USA, and the M.D. degree from the
Boston University School of Medicine.
She is currently an Assistant Professor in Otology
and Laryngology, Harvard Medical School, and
conducts research at the Eaton-Peabody Laborato-
ries of the Massachusetts Eye and Ear Infirmary,
Boston, MA. Dr. Nakajima’s interests include ad-
dressing fundamental scientific questions about the
auditory system, and developing new and improved methods to diagnose and
treat human hearing disease. Her primary research involves human auditory
mechanics, middle-ear prostheses and acoustical stimulation of the cochlea.
Konstantina M. Stankovic trained at Massachusetts
Institute of Technology (B.Sc. degrees in physics and
biology, Ph.D. degree) and Harvard Medical School
(M.D. degree, residency in otolaryngology, postdoc-
toral research fellowship, clinical fellowship in neu-
rotology – skull base surgery).
She is currently Assistant Professor of Otology
and Laryngology at Harvard Medical School and
Associate Surgeon at Massachusetts Eye and Ear in
Boston. Her research program is cross-disciplinary
and focused on hearing loss. She combines tools of
systems neuroscience with electronics, optics and molecular studies to develop
novel diagnostics, prognostics and therapeutics for deafness.
Dr. Stankovic serves on the Editorial Board of Otology and Neurotology and
as President of the American Auditory Society.
YIP et al.: A FULLY-IMPLANTABLE COCHLEAR IMPLANT SOC WITH PIEZOELECTRIC MIDDLE-EAR SENSOR 229
Anantha P. Chandrakasan (F’04) received the
B.S., M.S., and Ph.D. degrees in electrical engi-
neering and computer sciences from the University
of California, Berkeley, CA, USA, in 1989, 1990,
and 1994, respectively.
Since September 1994, he has been with the Mass-
achusetts Institute of Technology, Cambridge, where
he is currently the Joseph F. and Nancy P. Keithley
Professor of Electrical Engineering. He was the Di-
rector of the MIT Microsystems Technology Labo-
ratories from 2006 to 2011. Since July 2011, he has
been the Head of the MIT EECS Department.
Dr. Chandrakasan was a co-recipient of several awards including the 1993
IEEE Communications Society’s Best Tutorial Paper Award, the IEEE Electron
Devices Society’s 1997 Paul Rappaport Award for the Best Paper in an EDS
publication during 1997, the 1999 DAC Design Contest Award, the 2004 DAC/
ISSCC Student Design Contest Award, the 2007 ISSCC Beatrice Winner Award
for Editorial Excellence and the ISSCC Jack Kilby Award for Outstanding Stu-
dent Paper (2007, 2008, 2009). He received the 2009 Semiconductor Industry
Association (SIA) University Researcher Award. He is the recipient of the 2013
IEEE Donald O. Pederson Award in Solid-State Circuits.
His research interests include micro-power digital and mixed-signal inte-
grated circuit design, wireless microsensor system design, portable multimedia
devices, energy efficient radios and emerging technologies. He is a co-author
of Low Power Digital CMOS Design (Kluwer Academic Publishers, 1995),
Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), and
Sub-threshold Design for Ultra-Low Power Systems (Springer 2006). He is
also a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of
High-Performance Microprocessor Circuits (IEEEPress,2000),andLeakage
in Nanometer CMOS Technologies (Springer, 2005).
He has served as a technical program co-chair for the 1997 International Sym-
posium on Low Power Electronics and Design (ISLPED), VLSI Design ’98, and
the 1998 IEEE Workshop on Signal Processing Systems. He was the Signal Pro-
cessing Sub-committee Chair for ISSCC 1999–2001, the Program Vice-Chair
for ISSCC 2002, the Program Chair for ISSCC 2003, the Technology Direc-
tions Sub-committee Chair for ISSCC 2004–2009, and the Conference Chair
for ISSCC 2010–2014. He is the Conference Chair for ISSCC 2015. He was an
Associate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1998
to 2001. He served on SSCS AdCom from 2000 to 2007 and he was the meet-
ings committee chair from 2004 to 2007.
