Content uploaded by Bharathwaj Muthuswamy
Author content
All content in this area was uploaded by Bharathwaj Muthuswamy on Jul 11, 2015
Content may be subject to copyright.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1
A Generic Model of Memristors
With Parasitic Components
Maheshwar Pd. Sah, Changju Yang, Hyongsuk Kim, Member, IEEE,
Bharathwaj Muthuswamy, Jovan Jevtic, Member, IEEE, and Leon Chua, Life Fellow, IEEE
Abstract—In this paper, a generic model of memristive systems,
which can emulate the behavior of real memristive devices is pro-
posed. Non-ideal pinched hysteresis loops are sometimes observed
in real memristive devices. For example, the hysteresis loops may
deviate from the origin over a broad range of amplitude and fre-
quency of the input signal. This deviation fromtheidealcaseis
often caused by parasitic circuit elements exhibited by real mem-
ristive devices. In this paper, we propose a generic memristive cir-
cuit model by adding four parasitic circuit elements,namely,asmall
capacitance, a small inductance, a small DC current source, and a
small DC voltage source, to the memristive device. The adequacy
of this model is verified experimentally and numerically with two
thermistors (NTC and PTC) memristors.
Index Terms—Generic model, memristive devices, memristor,
parasitic components, pinched hysteresis loop.
I. INTRODUCTION
THE DISCOVERY of a physical model of a TiO mem-
ristor [1] by a team of scientists from has attracted
enormous interests from both industry and academia. The mem-
ristor was originally postulated by Leon Chua as the fourth basic
circuit element in electrical circuits [2]–[4], and generalized in
1976 to a broader class of dynamical systems called memristive
devices [5]. The most distinguished feature of memristive de-
vices is the “pinched hysteresis loop”oni-v plane for any bipolar
periodic voltage or current input signal that has a zero average
value. Consequently, pinched hysteresis loops are used as the
fingerprint to identify memristive devices. An “ideal” pinched
Manuscript received October 26, 2014; revised November 10, 2014; accepted
November 11, 2014. This work was supported in part by the U.S. Air Force
under Grant FA9550-13-1-0136 as well as an EC Marrie |Curie Fellowship, and
two National Research Foundation of Korea (NRF) grants funded by the Korean
government ( 2013R1A2A2A01068683 and 2012R1A1A2044078). This paper
was recommended by Associate Editor C. Fernando. (Corresponding author:
H. Kim.)
M. P. Sah is with the Department of Computer Science and Engineering, Uni-
versity of Notre Dame, Notre Dame, IN 46556 USA, and also with the Division
of Electronics and Information Engineering and Intelligent Robots Research
Center, Chonbuk National University, Jeonju, Jeonbuk, 561-756, Korea (e-mail:
msah@nd.edu).
C. Yang and H. Kim are with the Division of Electronics and Information
Engineering and Intelligent Robots Research Center, Chonbuk National
University, Jeonju, Jeonbuk, 561-756, Korea (e-mail: ychangju@jbnu.ac.kr;
hskim@jbnu.ac.kr).
B. Muthuswamy and J. Jevtic are with Department of Electrical Engineering
and Computer Science Milwaukee School of Engineering, Milwaukee, WI
53202 USA (e-mail: muthuswamy@msoe.edu; jevtic@msoe.edu).
L. Chua is with the Department of Electrical Engineering and Computer
Sciences, University of California, Berkeley, CA 94720-1770 USA (e-mail:
chua@eecs.berkeley.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2014.2373674
hysteresis loop must pass through origin for any bipolar peri-
odic input voltage [resp., input current ], which assumes
both positive and negative voltages (resp., currents) and has a
zero mean. The shape of the pinched hysteresis loop varies with
frequency and shrinks to a single-valued function through the
origin, as the frequency tends to infinity [6].
Another fingerprint of a memristor is the dependency of
pinched hysteresis lobe area on the frequency of the periodic
excitation signal. Beyond some critical frequency , the area
of each of the two pinched hysteresis lobes in the first and
third quadrant decreases monotonically as the frequency of the
periodic input voltage [resp., current ] increases.
Although pinched hysteresis loops are the fingerprints of
memristive devices, experimentally-measured pinched hys-
teresis loops of some real “physical” memristive devices may
not pass through the origin [7]–[11], [20], [21]. In some cases,
the pinched point may even disappear beyond some frequency
of the applied voltage source , or current source
[7]. Also crucial impact of parasitic components may appear
on the modeling the dynamics of log domain circuits [19].
Similarly, intelligence of the plasmodia and slime mould can
be mapped to LC contour with a memristor [22], [23]. Fig. 1
shows some examples of experimentally measured non-zero
crossing pinched hysteresis loops from real memristive devices,
such as plants, Physarum, TiO -based metal insulator devices,
redox-based resistive switches, electrochemical systems, and
venus fly trap [7]–[10], [20], [21]. The non-zero location of
the pinched point may be caused by the presence of parasitic
circuit elements and/or batteries.
The goal of this paper is to show, how to derive a composite
1-port circuit model as shown in Fig. 2, which can emulate
the measured pinched loops over a broad range of amplitude
and frequency , as closely as possible.
The concept of a “model” implies that there is no exact model
for real-world devices [12]. In this paper, we propose a simple
tractable 1-port memristor circuit model with a memristor plus
four-small circuit elements, called parasitics, that can emulate
the experimental pinched hysteresis loops as closely as possible
over a set of amplitude and frequency . Our proposed
model can be applied to any memristive device whose measured
pinched hysteresis loop did not pass through the origin [10], [20]
where the pinched point occurs near the origin. The effect of
the DC voltage source and/or current source is to translate this
pinched point to the origin.
This paper is organized as follows: Section II reviews the
characteristic fingerprints of an ideal memristor and memristive
system. Section III presents our generic memristor circuit model
using a memristor, a parasitic capacitance, a parasitic induc-
tance, a small DC current source, and a small DC voltage source.
1549-8328 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Fig. 1. Examples of non-zero crossing pinched hysteresis loops measured from
some physical and organic memristors. (a) Memristor in plants [7]. (b) Slime
mould memristors [8]. (c) TiO based metal-insulator-metal devices [9]. (d)
Nanobatteries in redox based switches [10]. (e) Electrochemical systems [20].
(f). Memristors in the venus flytrap [21].
Fig. 2. (a) Composite 1-port circuit model of a memristor-like device. (b)
Illustration of a non-zero crossing pinched hysteresis loop.
Section IV describes our generic memristor circuit model of an
NTC thermistor, and a PTC thermistor. Comparison between the
experimental and the simulated results from our generic NTC
and PTC thermistor models are presented in Section V. Finally,
some concluding remarks are presented in Section VI.
II. FINGERPRINTS OF MEMRISTORS
Amemristorisdefined as a two-terminal electrical device
whose instantaneous voltage and current obey the state-depen-
dent Ohm's law. In this paper, we consider current-controlled
memristors defined by
(1)
where is a continuous function of , called
the memristance,and 's are the “ ”state variables defined by
asystemof“ ” ordinary differential equations.
Similarly, we consider voltage-controlled memristors defined
by
(2)
Fig. 3. Fingerprints of a memristor. (a) Zero-crossing (passing through origin)
pinched hysteresis loop shrinks continuously as frequency increases. It will
tend to a straight line as tends to infinity. (b) The absolute value of each lobe
area decreases as the frequency of the input signal increases for .
where is a continuous function of the state variable
, called the memductance.
Afingerprint of memristor is the zero-crossing pinched hys-
teresis loops on the current versus voltage plane under any
bipolar zero-mean, sine wave-like excitations. Another finger-
print is the change in shape of the pinched hysteresis loop with
the frequency . In particular, it shrinks to a single-valued func-
tion through the origin, as the frequency tends to infinity. Fig.
3(a) shows an example of the pinched hysteresis loops of the
first-order generic memristor for frequencies, ,
[13]–[15], [17].
Another fingerprint of memristor is the dependency of the
hysteresis lobe area on the frequency of the periodic excita-
tion. For a bipolar periodic input voltage ,orcurrent ,
the pinched hysteresis loop has a typical shape depending on
the memristor constitutive relation. Above a certain critical fre-
quency , the magnitude of the area of the hysteresis lobe in
the 1st or 3rd quadrant is inversely proportional to the excita-
tion frequency . This property asserts that, the magnitude of
the area of the pinched lobe gradually decreases with increasing
frequency for , as shown in Fig. 3(b) for a memristor.
The lobe area computed using Riemann-Stieltjes integral tracks
the orientation of pinched hysteresis loop in clockwise or coun-
terclockwise direction [15]. If the lobe area is positive (resp.,
negative) during a half cycle of the input signal, then the orien-
tation of the pinched loop is clockwise (resp., counterclockwise)
either in the 1st quadrant, or the 3rd quadrant, respectively and
vice versa. The 1st and 3rd quadrant lobe area vs. frequency
curve shown in Fig. 3(b) for a memristor is positive and nega-
tive respectively, which illustrate that the orientation of pinched
hysteresis loop is clockwise and counterclockwise respectively.
III. GENERIC MEMRISTOR DEVICE MODEL
Our generic memristor device model is shown in Fig. 4. It
consists of a voltage-controlled or current-controlled memristor
in parallel with a parasitic capacitor and a parasitic DC
current source ,whereaparasitic inductor in series with
aparasitic DC voltage source , is connected in series with
the upper part of the circuit. The principle and circuit-theoretic
concepts behind this generic circuit model date back to the mid-
nineteen-sixties and had been presented at various conferences
and applied in several publications on device modeling [12],
[16], [18].
If is the input voltage at time in Fig. 4, then by KVL,
(3)
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
SAH et al.: A GENERIC MODEL OF MEMRISTORS WITH PARASITIC COMPONENTS 3
Fig. 4. Generic memristor device model.
where is the voltage across the parallel connection of and
,and is the voltage across the serial connection of and
.
The current is given by KCL,
(4)
where denote the DC current source, the cur-
rent through the memristor, and the current through the
capacitor, respectively. Here, denotes the memristance
which depends on the state variables
of the memristor.
It follows from (3) and (4) that,
(5)
(6)
The state variables are definedby“ ” state
equations
(7)
where we have assumed the memristor is voltage-controlled
and described by
(8)
Altogether, (5), (6), and (7) constitute state equations
in state variables .1We wil l s e e in
the following sections that the parasitic capacitance ,thepar-
asitic inductance , as well as the independent DC voltage
and DC current can cause the Lissajoux figure to deviate from
the origin .2
There exist many memristive devices made of “organic”ma-
terials or “electrolytes” which exhibit a pinched hysteresis loop
1Observe that the state variable in (5) is just the voltage across the parasitic
capacitor . Similarly, the state variable in (6) is just the current through the
parasitic inductor .
2For many real memristive devices, such as thermistors, the parasitic voltage
source and the parasitic current source are negligible and can be set to
zero.
where the “pinched point” occurs near, but not exactly at, the
origin [10], [20]. Such devices are not passive because a small
current will flow when a passive resistor is connected across the
device. The energy in such memristive devices come from the
internal chemical reactions, which can generate a small voltage,
such as the classic Nernst potential.
IV. MODELING NTC AND PTC THERMISTORS
Thermistors are physical devices whose steady-state DC re-
sistance measured at a fixed applied DC voltage varies signifi-
cantly with changes in the device temperature,whichisastate
variable whose dynamics is determined by some differential
equation involving the state variable, and the input voltage.
1) Generic Memristor Circuit Model for a Physical NTC
Thermistor: An ideal voltage-controlled, negative-tempera-
ture-coefficient (NTC) thermistor [5], [16] can be modeled by
a voltage-controlled memristor with only one state variable
:
(9)
(10)
where and denote respectively the terminal voltage and
current of the NTC thermistor, denotes the tempera-
ture-dependent conductance of the NTC thermistor, de-
notes the thermistor resistance at ambient temperature ,
denotes a single state variable in (7) representing the abso-
lute temperature of the NTC thermistor, and denotes a ma-
terial-specific constant. Observe that the conductance
of the NTC thermistor with respect to in (10) increases as
the temperature increases. Hence, the resistance
decreases as increases.3The state variable (tem-
perature) depends on the power dissipation of the device via
the heat balance equation,
(11)
where denotes the dissipation constant, and denotes
the heat capacitance of the NTC thermistor.
In this paper, we will model a real physical NTC thermistor
using the generic memristor device model in Fig. 4 via the three
state (5), (6), and (7), with and :
''
(12)
(13)
(14)
2) Generic Memristor Circuit Model for a Physical PTC
Thermistor: An ideal voltage-controlled positive-temperature-
3The NTC thermistor is said to be a “negative-temperature dependent”re-
sistor because its resistance decreases as the temperature increases. The sub-
script “ ”of ,,and in (9)–(11) pertains to a “negative-temperature depen-
dent” resistor.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
coefficient (PTC) thermistor is usually modeled with only one
state variable :
(15)
(16)
(17)
where and denote respectively the terminal voltage and
current of the PTC thermistor, denotes the conductance
of the PTC thermistor, denotes the thermistor resistance
at ambient temperature ,denotes a single state variable
(absolute temperature) in (7), denotes a material-specific
constant, denotes the dissipation constant and denotes
the heat capacitance of the PTC thermistor. Observe from (16)
that when the absolute temperature increases, then conduc-
tance of the PTC thermistor decreases. Hence, the re-
sistance increases as increases.4
In this paper, we will model a real physical PTC thermistor
using the generic memristor device model in Fig. 4 via the three
state (5), (6), and (7), with ,and :
''
(18)
(19)
(20)
V. E XPERIMENTAL AND SIMULATION RESULTS
In this section, we present hardware experiments and numer-
ical simulations of negative-temperature coefficient (NTC) and
positive-temperature coefficient (PTC) thermistors. The hard-
ware experiments were performed with commercially available
NTC and PTC thermistors at room temperature and their results
were compared with simulations from our generic memristor
device model.
The ideal mathematical models of NTC and PTC thermistors
defined in (9)–(11) and (15)–(17) were simulated with a sinu-
soidal voltage source of amplitude and
frequency . The parameters used for the NTC and PTC ther-
mistors in this paper are:
NTC thermistor: , ,
, , ,
PTC thermistor: , ,
, , .
Fig. 5(a) and Fig. 5(b) show the numerically calculated
pinched hysteresis loops of the NTC and the PTC thermistors
at different frequencies of the applied sinusoidal voltage source
(with amplitude ). Observe that, the loci in the current
vs. voltage plane for the input signal exhibits zero-crossing
pinched hysteresis loops for all the frequencies, as expected.
Observe that the shape and lobe area of the pinched hysteresis
4The PTC thermistor is said to be a “positive-temperature dependent” resistor
because its resistance increases as the temperature increases. The subscript “ ”
of ,,and in (15)–(17) pertains to a “positive-temperature dependent”re-
sistor.
Fig. 5. Zero-crossing pinched hysteresis loops of ideal mathematical models
of (a) NTC, and (b) PTC thermistors at different frequencies. The input is a
sinusoidal voltage source with amplitude .
loops shrink as the frequency of the input signal increases as
expected. All pinched hysteresis loops of the ideal mathemat-
ical model of the NTC and the PTC thermistors satisfy the
required fingerprints of a memristor, as expected.
Hardware experiments were conducted on both NTC and
PTC thermistors to validate our generic memristive device
model for real memristive devices. The first experiment was
conducted on a commercially available Thermometric's-NTC
thermistor5in our laboratory. The initial small-signal resistance
of the NTC thermistor was measured with an Ohm meter
at zero DC applied voltage to be equal to 3.89 at room
temperature. Fig. 6 shows the experimental results measured
with the NTC thermistor driven by a sinusoidal voltage source
with amplitude at different frequencies. When the
frequency of the input signal is varied from 0.01 Hz to 100
Hz, the oscilloscope displays pinched hysteresis loops which
pass through the origin. However, as the frequency of the input
signal increases beyond 1 KHz, the pinched hysteresis loops
on i-v plane did not pass through the origin and the shape
of the pinched loops also changes as the frequencies of the
input signal increases. Fig. 6 also shows the simulation results
of the NTC thermistor, when it is modeled with the generic
memristor device model. The same input (sinusoidal source
with amplitude ) is used in both tables. The parameters
used for the simulation is , , ,
. Observe that the experimental results (shown in
blue) obtained from the NTC thermistor in the left side of each
table is similar to the simulation results (shown in red)inthe
right side of the corresponding table, in Fig. 6.
In order to see the role played by the parasitic capacitor
and parasitic inductor , Fig. 7 shows the corresponding re-
sults when only (9)–(11) (without the parasitic and )are
used for simulation, instead of the generic memristor device
model. Comparing Fig. 6 and Fig. 7, we observe that the para-
sitics play an increasing role as the frequency increases beyond
100 Hz.
Fig. 8 shows simulation of the NTC thermistor when the ef-
fect of a parasitic voltage source , and a parasitic current
source are non-zero, and and are zero. When NTC
5The experiment was performed at lab environment on glass coated
NTC Diode thermometrics thermistors (NTC-3.896KGJG). The device
can be purchased and its specifications can be found from the fol-
lowing websites: http://www.devicemart.co.kr/goods/view.php?seq=8598,
http://www.ge-mcs.com/download/temperature/920-320C.pdf.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
SAH et al.: A GENERIC MODEL OF MEMRISTORS WITH PARASITIC COMPONENTS 5
Fig. 6. Experimental measurements (blue) of a commercially available Ther-
mometric's-NTC thermistor (left side) and the corresponding simulated results
(red) using the generic memristor device model (right side). The input is a si-
nusoidal source with amplitude of . The experiment on the NTC ther-
mistor was conducted at room temperature. The scale of and on the left side
of each table is identical to that shown on the right side. The parameters used
for simulations of the generic memristor device model of the NTC thermistor
are: , , , ,
, , , , .
Fig. 7. Simulated results using (9)–(11) (without parasitics) corresponding to
Fig. 6.
is driven by a sinusoidal source with amplitude at fre-
quencies and 0.3 Hz, the pinched hysteresis loops
are not only translated to the pinched point but the shape of the
pinched loops also changes as the value of and are varied.
However, for higher frequencies ,the curve of
the NTC thermistor is unchanged in shape except a translation
to the point .
In order to see the effects of non-zero parasitic circuit el-
ements in the NTC thermistor, the simulations are performed
Fig. 8. Pinched hysteresis loops of the NTC thermistor without parasitic circuit
elements (magenta) in column 1 and corresponding results (red and blue)using
the generic memristor device model in columns 2 and 3. The results of NTC
generic memristor device model is obtained for different values of and
when , .
for different values of at various frequencies.
Fig. 9 shows the pinched hysteresis loops in the NTC generic
memristor device corresponding to frequencies ,
1 Hz, and 10 KHz for sinusoidal source with amplitude
. Observe that the pinched hysteresis loops are changed to
different shapes depending on the values of non-zero parasitic
components.
We performed experiments on a commercially available Mu-
rata's-PTC thermistor.6The small-signal initial resistance at
was measured with an Ohm meter to be equal to 40 ,at
room temperature. Fig. 10 shows the experimental and simula-
tion results of the PTC thermistor using the PTC generic mem-
ristor device model for input voltage with
, at different frequencies. The parameters used for the
simulation are: , , ,
6The experiment was performed at lab environment on Murata's Lead typ-
e PTC thermistors (PTFM04BE471Q2N34B0). The device can be purchased
and its specifications can be found from the following websites: http://ww-
w.eleparts.co.kr/EPXANC6G, http://search.murata.co.jp/Ceramy/CatalogActi-
on.do?sHinnm =PTH9M04BE471TS2F333&sNHinnm=PTFM04BE471Q2N3
4B0&sNhin_key= PTFM04BE471Q2N34B0&sLang= en&sParam= PTFM04
BE471Q2N34B0.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Fig. 9. Pinched hysteresis loops of the NTC memristor without parasitic cir-
cuit elements (Magenta) in column 1 for sinusoidal input
, and corresponding results (red and blue) in columns 2 and 3 using
the generic memristor device model. The results of the NTC generic memristor
device model is obtained for non-zero values of , , and .
. Observe that at low frequencies, the pinched hys-
teresis loops on the plane are pinched at the origin. How-
ever, the loops are not pinched at higher frequencies. Observe
that the experimental results (shown in blue) obtained from the
PTC thermistor in the left side of each table is similar to the
simulation results (shown in red)intherightsideofthecorre-
sponding table in Fig. 10.
In order to see the role played by the parasitic capacitor
and parasitic inductor , Fig. 11 shows the corresponding re-
sults when only (15)–(17) (without the parasitic and )
are used for simulation, instead of the generic memristor device
model. Observe that the parasitics play an increasing role as the
frequency increases beyond 100 Hz.
Simulations are also performed in PTC generic memristor de-
vice to analyze the effects of and with zero and non-zero
parasitic voltage source and parasitic current source .
Fig. 12 shows the pinched hysteresis loops corresponding to
different values ,when and are zero. Observe
that the pinched point and shape of the hysteresis loops are
changed depending on the values of and .At
and 0.2 Hz, the parasitic voltage and parasitic current
play an important role in not only shifting the pinched point to
Fig. 10. Experimental measurement (blue) of a commercially available Mu-
rata's-PTC thermistor (left side) and the corresponding simulated result (red)
using the generic memristor device model (right side). The input is a sinusoidal
source with amplitude of . The experiment on the PTC thermistor
was conducted at room temperature. The scale of and on the left side of
each table is identical to that shown on the right side. The parameters used
for simulations of the generic memristor device model of the PTC thermistor
are: , , , ,
, , , , .
Fig. 11. Simulated results using (15)–(17) (without parasitics) corresponding
to Fig. 10.
, but also changing the shape of pinched hys-
teresis loops, as illustrated in Fig. 11. However at higher fre-
quency , the pinched point is translated without
changes in shape.
Simulations are also performed in PTC generic memristor
device for non-zero parasitic circuitelementsatdifferent
frequencies. Fig. 13 shows the pinched hysteresis loops
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
SAH et al.: A GENERIC MODEL OF MEMRISTORS WITH PARASITIC COMPONENTS 7
Fig. 12. Pinched hysteresis loops of the PTC thermistor without parasitic cir-
cuit elements (magenta)inco
lumn 1 and corresponding results (red and blue)
using the generic memristor device model in columns 2 and 3. The results of
PTC generic memristor device model is obtained for different values of and
when , .
for input at frequencies
. Observe that, the pinched
hysteresis loops are deviated and changes to different shapes
depending on the values of parasitic components.
VI. CONCLUSION
The pinched point and the shape of the “pinched hysteresis
loop” of real physical memristive devices may vary over a broad
range of amplitude and frequency . In this study, a generic
model of a real memristor device is proposed to emulate the be-
havior of real memristor devices. It is shown that the changed
of the pinched hysteresis loops of a memristive system from
the ideal operation can be emulated by introducing appropriate
parasitic circuit elements. The experimentally measured and nu-
merically simulated pinched hysteresis loops of the NTC and the
PTC thermistors illustrate that our generic model is adequate for
emulating real physical memristve devices.
REFERENCES
[1] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The
missing memristor found,” Nature, vol. 453, pp. 80–83, 2008.
Fig. 13. Pinched hysteresis loops of the PTC memristor without parasitic cir-
cuit elements (magenta) in column 1 for sinusoidal input
, and corresponding results (red and blue) in columns 2 and 3 using
the generic memristor device model. The results of the PTC generic memristor
device model is obtained for non-zero values of , , ,and .
[2] L. O. Chua, “Memristor-the missing circuit element,” IEEE Trans. Cir-
cuit Theory, vol. CT-18, no. 5, pp. 507–519, Sep. 1971.
[3] L. Chua, “Resistance switch ing memories are memristors,” Appl. Phys.
A, vol. 102, no. 4, pp. 765–783, 2011.
[4] L. O. Chua, “The fourth element,” Proc. IEEE, vol. 100, no. 6, pp.
1920–1927, Jun. 2012.
[5] L. O. Chua and S. M Kang, “Memristive devices and systems,” Proc.
IEEE, vol. 64, no. 2, pp. 209–223, Feb. 1976.
[6] S. P. Adhikari, M. P. Sah, H. Kim, and L. O. Chua, “Three fingerprints
of memristor,” IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 60, no.
11, pp. 3008–3021, Nov. 2013.
[7] A.G.Volkov,C.Tucket,J.Reedus,M.I.Volkova,V.S.Markin,and
L. Chua, “Memristors in plants,” Plant Signal. Behav., vol. 9, no. 2,
pp. e28152(1)–e28152(8), Feb. 2014.
[8] E. Gale, A. Adamatzky, and B. D. Costello ,“ Slime mould memristors,”
arXiv:1306.3414, Apr. 2014.
[9] L. Qingjiang, A. K hiat, L. Salaoru, C. Papavassiliou, X. Hu, and T. Pro-
dromakis, “Memory impedance in based metal-insulator-metal
devices,” Sci. Rep., Nat., vol. 4, no. 4522, pp. 1–6, Mar. 2014.
[10] I. Valov, E. Linn, S. Tappertzhofen, S. Schmelzer, J. V. Hurk, F. Lentz,
and R. Waser, “Nanobatteries in redox-based resistive switches require
extension of memristor theory,” arXiv:1303.2589, Mar. 2013.
[11] B. Muthuswamy, J. Jevtic, H. H. C. Iu, C. K. Subramaniam, K.
Ganesan, V. Sankaranarayanan, K.Sethupathi,H.Kim,M.P.Sah,and
L. O. Chua, “Memristor modeling,” in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), Jun. 2014.
[12] L. O. Chua, “Device modeling via basic nonlinear circuit elements,”
IEEE Trans. Circuit Syst., vol. CAS-27, no. 11, pp. 1014–1044, 1980.
[13] L. Chua, V. I. Sbitnev, and H. Kim, “Hodgkin-Huxley axon is
made of memristors,” Int. J. Bifurcation Chaos, vol. 22, no. 3, pp.
1230011(1)–1230011(48), Mar. 2012.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
[14] L. Chua, V. I. Sbitnev, and H. Kim, “Neurons are poised near the
edge of chaos,” Int. J. Bifurcation Chaos, vol. 22, no. 4, pp. 1250098
(1)–1250098 (49), Apr. 2012.
[15] M. P. Sah, H. Kim, and L. O. Chua, “Brains are made of memristors,”
IEEE Circuits Syst. Mag., vol. 14, no. 1, pp. 12–36, Feb. 2014.
[16] L. O. Chua,IntroductiontoNonlinear Network Theory.NewYork:
McGraw-Hill, 1969.
[17] A. L. Hodgkin and A. F. Huxley, “A quantitative description of mem-
brane current and its application to conduction and excitation in nerve ,”
J. Physiol., vol. 117, no. 4, pp. 500–544, Aug. 1952.
[18] L. O. Chua and P. M. Lin, Computer-Aided Analysis of Electronic Cir-
cuits: Algorithms and Computational Techniques.E
nglewood Cliffs,
NJ, USA: Prentice-Hall, 1975.
[19] A. Ascoli, P. Curran, and O. Feely, “Modeling the dynamics of log-
domain circuits,” Int. J. Circuit Theory Appl., vol. 35, no. 1, pp. 33–70,
Jan. 2007.
[20] K. MacVittie and E. Katz, “Electrochemical systems with
memimpedance properties,” J. Phys. Chem. C, vol. 117, no. 47, pp.
24943–24947, Nov. 2013.
[21] A. G. Volkov, V. F. Tuckett, J. Reedus, C. M. Mitchell, M. I. Volkova,
V. S. Markin, and L. Chua, “Memristors in the venus flytrap,” Plant
Signal. Behav., vol. 9, no. 5, pp. e29204(1)–e29204(12), May 2014.
[22] Y. V. Pershin, S. L. Fontaine, and M. D. Ventra, “Memristive
model of amoeba's learning,” Phys. Rev. E, vol. 80, no. 2, pp.
021926(1)–021926(6), Jul. 2010.
[23] F.L.Traversa,Y.V.Pershin,andM.D.Ventra,“Memorymodelsof
adaptive behavior,” IEEE Trans. Neural Netw. Learn. Syst., vol. 24, no.
9, pp. 1437–1448, Sep. 2013.
Maheshwar Pd. Sah received the B.E. in elec-
tronics and communication engineering from Nepal
Engineering College, Pokhara University, Nepal, in
2005, and the M.E. and Ph.D. in electronics engi-
neering from Chonbuk National University, Korea,
in 2010 and 2013 respectively, where he worked as
a Postdoctoral Scholar from 2013 to 2014.
He is currently a Visiting Scholar at the University
of Notre Dame, IN, USA. His main research inter-
ests include emerging transistors technology, circuit
design, cellular neural networks, analog Viterbi de-
coder, and analysis of memristor and memristive systems.
Changju Yang received the B.S and M.S. degrees
in electronics and information engineering from
Chonbuk National Univeristy, Korea, in 2008 and
2010 respectively, where he is currently studying
toward the Ph.D. degree in electronics and informa-
tion engineering. His main research interests include
circuit design, analog Viterbi decoder, and analysis
of memristor and memristive systems.
Hyongsuk Kim received the Ph.D. degree in elec-
trical engineering from the University of Missouri,
Columbia, MO, USA, in 1992. Since 1993, he has
been a Professor with the Division of Electronics
Engineering, Chonbuk National University, Korea.
From 2000 to 2002 and again from 2009 to 2010,
he was with the Nonlinear Electronics Labora-
tory, EECS Department, University of California,
Berkeley, CA, USA, as a Visiting Scholar.
His current research interests include memristors
and their application to cellular neural/nonlinear net-
works.
Bharathwaj Muthuswamy received the B.S., M.S.,
and Ph.D. degrees in electrical engineering and
computer sciences from the University of California,
Berkeley, CA, USA, in 2002, 2005, and 2009, re-
spectively. He is an Assistant Professor of Electrical
Engineering at the Milwaukee School of Engineering
(MSOE), Milwaukee, WI, USA. His areas of interest
are nonlinear dynamical (chaotic) systems and em-
bedded systems. His research involves investigating
chaotic dynamics of the Muthuswamy-Chua system,
understanding memristive behavior in discharge
tubes, PIN junction diodes and superconducting Josephson junctions, studying
applications of nonlinear dynamical systems using field programmable gate
arrays, understanding the non-linear dynamics of atrial fibrillation and intro-
ducing nonlinear dynamics education at the undergraduate level.
Dr. Muthuswamy has held visiting professor appointments for teaching/re-
search at the University of California, Berkeley; Vellore Institute of Technology;
and the University of Western Australia.
Jovan Jevtic received a Ph.D. degree in computa-
tional electromagnetics from Ohio State University,
Columbus, OH, USA, in 1999.
He is an Assistant Professor of Electrical Engi-
neering at the Milwaukee School of Engineering
(MSOE), Milwaukee, WI, USA. Prior to joining
MSOE, he worked in semiconductor processing and
medical device industries as a Technology Program
Manager and Senior Staff Scientist with a focus
on new product development. He has published
over 40 scientific works, including over 16 U.S.
and international patents. His research is in the area of electromagnetic field
applications for radio-frequency and microwave plasmas, magnetic resonance
imaging, and induction heating.
Dr. Jevtic was recognized by James Clerk Maxwell foundation of Scotland
for solving Smith's Prize problems set by Maxwell that remained unsolved since
the 19th century.
Leon Chua (LF'02) received the M.S. degree from
the Massachusetts Institute of Technology, Cam-
bridge, MA, USA, in 1961 and the Ph.D. degree in
electrical engineering from the University of Illinois
at Champaign-Urbana, IL, USA, in 1964.
He has been a Professor at the University of
California, Berkeley, CA, USA, since 1971. In 2011,
he was appointed a Distinguished Professor at the
Technical University of Münich. He was awarded
sevenpatentsand14honorarydoctorates.When
not immersed in science, he relaxes by searching
for Wagner's leitmotifs, musing over Kandinsky's chaos, and contemplating
Wittgenstein's inner thoughts.
Prof. Chua received many awards including the first recipient of the Gustav
Kirchhoff award, the Guggenheim Fellow award, and the European EC Marie
Curie Fellow award. He was elected a foreign member of the Academia Eu-
ropaea and of the Hungarian Academy of the Sciences. He was elected Con-
frerie des Chevaliers du Tastevin in 2000.
