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A Framework for Rapid System-Level Synthesis Targeting to Reconfigurable Platforms: A Computer Vision Case Study
Abstract
Reducing time-to-market while improving product quality is a big challenge for system architects of recent multimillion gate System-on-Chips (SoCs). From the software perspective, recent electronics market is governed by the development of hardware-dependent software, i.e. multiple layers of software ready to run optimal on various heterogeneous computing platforms from different application domains, such as automotive, consumer and wireless applications. From the hardware perspective there is continuous market trend in configurable systems, so that part of their functionality can be re-programmed to adapt the client’s requirements, i.e. Software Defined Radios (SDRs). In this paper we present a rapid system-level development flow that offers a concurrent fast hardware/software system-level design by enabling a) to start developing, testing and validating the embedded software substantially earlier than it has been possible in the past and b) fast flexible hardware design based on High Level Synthesis (HLS) techniques so that the underdevelopment HW prototype is evaluated and tested in the entire development time. We evaluated our design flow with a computer vision algorithm, i.e. Harris corner detection, and we managed to decrease the development time by almost 64x by pruning the HW design space by 34x, while maintaining designs that tradeoff high Quality-of-Report (QoR) on the Pareto frontier.
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This paper presents a novel technique for converting QEMU from a virtual machine into an instruction-accurate instruction set simulator (IA-ISS) and using it as the processor model of a QEMU and SystemC-based virtual platform. The proposed framework can not only simulate arbitrary hardware modeled in SystemC, but it can also be used to evaluate the performance of the target system for SoC development. Our experimental results show that the built-in vector interrupt controller of QEMU modeled in C can be easily replaced by one modeled in SystemC for demonstrating the waveform of AMBA on-chip-bus model connected with the adapted IA-ISS. Moreover, the instruction-accurate statistics can be gathered while co-simulating with a full-fledged Linux kernel. Our experimental results further show that with every instruction executed and every memory accessed since power on traced, the hardware/software co-simulation takes no more than 16 minutes in booting up the Linux kernel, even in the worst case.
Consistency of image edge filtering is of prime importance for 3D interpretation of image sequences using feature tracking algorithms. To cater for image regions containing texture and isolated features, a combined corner and edge detector based on the local auto-correlation function is utilised, and it is shown to perform with good consistency on natural imagery.
In the embedded system domain there is a continuous demand towards providing higher flexibility for application development. This trend strives for virtual prototyping solutions capable of performing fast system simulation. Among other benefits, such a solution supports concurrent hardware/software system design by enabling to start developing, testing, and validating the embedded software substantially earlier than has been possible in the past. Towards this direction, throughout this article we introduce a new framework, named Plug&Chip, targeting to support rapid prototyping of 2D and 3D digital systems. In contrast to other relevant approaches, our solution provides higher flexibility by enabling incremental system design, while also handling platforms developed with the usage of 3D integration technology.
Hardware/software codesign investigates the concurrent design of hardware and software components of complex electronic systems. It tries to exploit the synergy of hardware and software with the goal to optimize and/or satisfy design constraints such as cost, performance, and power of the final product. At the same time, it targets to reduce the time-to-market frame considerably. This paper presents major achievements of two decades of research on methods and tools for hardware/software codesign by starting with a historical survey of its roots, by highlighting its major research directions and achievements until today, and finally, by predicting in which direction research in codesign might evolve in the decades to come.
The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration we present three main contributions: a concise library format for characterization and reuse of components specified in high-level languages like SystemC; an algorithm to prune alternative implementations of a component given the context of a specific SoC design; and an algorithm that explores compositionally the design space of the SoC and produces a detailed plan to run high-level synthesis on its components for the final implementation. The two algorithms are computationally efficient and enable an effective parallelization of the synthesis runs. Through a case study, we show how our methodology returns the essential properties of the design space at the system level by combining the information from the library of components and by identifying automatically those having the most critical impact on the overall design.
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Compositional system-level design exploration with planning of high-level synthesis
- H.-Y Liu
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A novel technique for making qemu an instruction set simulator for co-simulation with systemc
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