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828 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015
Advanced Methodology for Fast 3-D TCAD
Device/Circuit Electrothermal Simulation
and Analysis of Power HEMTs
Aleš Chvála, Daniel Donoval, Member, IEEE, Alexander Šatka,
Marián Molnár, Juraj Marek, and Patrik Príbytný
Abstract— This paper introduces an advanced methodology for
fast 3-D Technology Computer Aided Design (TCAD) electrother-
mal simulation for the analysis of power devices. The proposed
methodology is based on coupling finite element method (FEM)
thermal and circuit electrical simulation in a mixed-mode setup.
A power InAlN/GaN high-electron mobility transistor (HEMT)
is used to perform validation of the designed electrothermal
simulation. A new equivalent temperature-dependent nonlinear
analytical large signal circuit model of HEMT is proposed.
The model is implemented to Synopsys TCAD Sentaurus using
compact model interface. The designed electrothermal simulation
methodology is developed to shorten the simulation time for com-
plex 3-D devices. This approach combines the speed and accuracy,
and couples temperature nonuniformity to the active device
electrothermal behavior. The simulation results are compared
with the measured data and results of 2-D FEM simulations.
The features and limitations of the methods are analyzed and
presented.
Index Terms—3-D electrothermal simulation, high-electron
mobility transistor (HEMT) equivalent circuit model, power
HEMT, TCAD modeling.
I. INTRODUCTION
RECENT progress in GaN-based high-electron mobility
transistors (HEMTs) has confirmed them to be the main
transistor technology for future high-power devices at high-
frequency operation because of their excellent electronic prop-
erties, high electron saturation velocity, and high breakdown
voltage [1], [2]. To extract and utilize the favorable GaN mate-
rial properties, however, there are still a lot of areas to be inves-
tigated. Among them the most important is to develop new,
GaN specific processes, structure design, and characterization
techniques. Today’s device and circuit simulators are standard
tools used in the development, characterization, and optimiza-
tion of electronic devices and systems. However, electrother-
mal simulations based on the finite element method (FEM) are
Manuscript received November 5, 2014; revised December 24, 2014;
accepted January 20, 2015. Date of publication February 4, 2015; date of
current version February 20, 2015. This work was supported in part by
Slovak Research and Development Agency under Grant APVV-0367-11 and
Grant VEGA 1/0866/11 and in part by the ENIAC JU Project E2COGaN under
Grant 324280/2012 through the Ministry of Education, Science, Research and
Sport of Slovakia. Samples were prepared with the support of the European
Project MORGAN under Grant FP7 NMP IP 214610. The review of this paper
was arranged by Editor R. Venkatasubramanian.
The authors are with the Institute of Electronics and Photonics, Slovak
University of Technology in Bratislava, Bratislava 812 45, Slovakia (e-mail:
ales.chvala@stuba.sk; daniel.donoval@stuba.sk; alexander.satka@stuba.sk;
marian.molnar@stuba.sk; juraj.marek@stuba.sk; patrik.pribytny@stuba.sk).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2015.2395251
very time consuming and require powerful hardware particu-
larly for complicated 3-D structures. Circuit simulations have
been limited to electronic functions at a preselected temper-
ature because the temperature dependences of the parameters
of the simulated models available today are considered at the
best by changing the static global device temperature. In power
electronic systems, in particular, temperature is one of the
critical parameters due to the nonnegligible self-heating effects
and the fact that many properties of power semiconductor
devices are strongly temperature dependent [3]–[27].
Most of simulators (such as Advanced Design System
and Spectre) include recent advanced electrothermal models
designed for devices in which the electrothermal feedback can
be accounted for by a simple single-pole equivalent network
[3], [4]. However, only the self-heating effect is included and
thermal coupling between devices is not considered. This
might lead to markedly inaccurate results, particularly when
the temperature of a transistor is affected by other close
enough devices. Moreover, the single-pole thermal circuits
have insufficient accuracy when describing the transient
behavior [5]. To be able to simulate the inherent heating
dynamically, direct and relaxation methods are available. The
direct method introduces an external equivalent thermal circuit,
e.g., RC network and its interactive coupling with the electrical
model [6], [7]. However, this method usually considers 1-D
heat flow which needs to be extracted from the measurements
and/or FEM simulations [8], [9]. Assumption of a 1-D heat
flow may be insufficient for large-area power devices and large
power loads in which an inhomogeneous temperature distribu-
tion caused by the natural 3-D heat flow inside the device can
cause an inhomogeneous distribution of the electric properties
of the power device along the whole chip. Building up a 3-D
equivalent thermal mesh is difficult and requires structure sim-
plification [10]–[13]. The relaxation method for electrothermal
simulation is based on coupling the separately solved thermal
and electrical equations [14], [15]. FEM is used for thermal
simulation and a Simulation Program with Integrated Circuit
Emphasis-like method is used for electrical simulation. The
complex solution requires a proper synchronization and data
transfer. This modeling methodology is applied to power
systems and integrated circuits to study the electrothermal
problems using a wide spectrum of electrical and thermal
software tools (such as VHDL-AMS, FLOTHERM [16],
Spectre, CircuitFire [17], HeatWave [18], GRADIENT [19],
ANSYS [20], Sentaurus device, and HSPICE [21]).
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
CHVÁLA et al.: ADVANCED METHODOLOGY 829
Our designed electrothermal simulation is based on direct
coupling between FEM thermal and circuit electrical simula-
tion using mixed-mode setup [22], [23] supported in Synop-
sys Technology Computer Aided Design (TCAD) Sentaurus
environment [24]. The mixed-mode setup allows direct inter-
connection of FEM thermal model and electrical temperature-
dependent circuit model. No synchronization and data transfers
between two different tools are required as it is in relaxation
method. The whole electrothermal simulation runs simulta-
neously. The advantages of the proposed method are in the
high speed of simulation and simplicity of implementation for
complete high complexity structure analysis. The methodology
can be applied for multifinger structures. The analysis of
thermal and electrical behaviors can help during design and
optimization of parameters and geometry from semiconductor
layers, metallization, package, and up to cooling assemblies
[25]–[27].
In this paper, we present our methodology illustrated on
electrothermal simulations of the GaN power HEMTs. Two
simulation methods, standard device 2-D FEM simulation and
our new fast 3-D simulation, are described. Their features
and limitations are analyzed. Due to highly time-consuming
3-D device FEM simulation, only the 2-D model has been
used for the comparative analysis. However, the neglected third
dimension can cause distorted results. For fast 3-D electrother-
mal simulation, the methodology has been proposed where the
electrical properties are simulated at the circuit level and only
the heat equation is solved in the 3-D model. A new equivalent
temperature-dependent nonlinear analytical large signal circuit
model of HEMT has been designed and implemented to
Sentaurus device using compact model interface (CMI) [28].
The electrical circuit model and 3-D FEM thermal model are
connected to each other in a circuit mixed-mode Sentaurus
device setup. Their heat flux and temperature exchange is
provided via thermal nodes at runtime. The simulation method
allows significant reduction of the simulation time especially
for very complex 3-D devices. All tools for thermal and
electrical simulations, structure editing, and data visualization
are covered by Synopsys. No additional tools are required.
Finally, the power InAlN/GaN HEMT is used for the veri-
fication of the designed model and electrothermal simulation
methodology, as described in Section V.
II. STRUCTURE DESCRIPTION
The structure under investigation is the power InAlN/GaN
HEMT (Fig. 1). The device consists of a 300-nm-thick AlN
nucleation layer grown on a 6H-SiC substrate followed by
a2.5-μm GaN buffer layer with a 1-nm AlN spacer layer
and a 7-nm In0.14Al0.86N barrier layer on top [29]. The
drain and source contacts are prepared by the evaporation
of a Ti/Al/Ni/Au metal stack with subsequent rapid thermal
annealing, while the gate contact is formed using Ni/Au
metallization. The gate-to-drain and the gate-to-source dis-
tances are 4.8 and 1.6 μm, respectively, while the gate length
is 1.6 μm. The device layout has a fork-shaped gate electrode
of 400 μm width each. The metal pads are prepared for
ground-signal-ground probe measurement. However, we used
Fig. 1. Top: schematic (not to scale) of 2-D cross section of the HEMT.
Bottom: 3-D view of the HEMT and metallization with a fork-shaped gate
electrode.
a needle probe setup for our analysis and two options to
measure each gate finger separately or both together.
III. 2-D FEM ELECTROTHERMAL SIMULATION
A. 2-D FEM Model Description
The 2-D FEM model of the HEMT is created in Sentaurus
Device Editor (SDE) [28] according to the structure geometry
(Fig. 1). Because of the invariant total polarization charge, the
1-nm AlN spacer layer and the 7-nm InAlN are replaced by
an 8-nm-thick InAlN layer [30]. This consideration can be
taken into account, because it provides negligible impact on
the simulation results. The interface between the GaN buffer
layer and the InAlN barrier layer is described by a value of
polarization charge σ=2.6×1013 cm−2. The opposite charge
polarity is placed at the InAlN barrier surface because of struc-
ture charge neutrality [31]. However, the charge has slightly
lower value (−1.9×1013 cm−2)considering of a neutraliza-
tion of the charge at the unpassivated structure surface. The
ohmic contacts are created under drain/source metallization
and Schottky contact under gate metallization with barrier
height 1.35 eV. The value of substrate thermal resistance is
Rth =10−3K·cm2/W. This value lumps the thermal resistance
of the SiC substrate and possible 3-D thermal effects. The
gate width (third dimension) for 2-D simulation is replaced
by coefficient area factor 2 ×400 μm. All electrophysical
model coefficients are set to match the best agreement with
measurement.
As for other heterostructure transistors, the designed mesh
must be sufficiently tight around heterointerfaces, especially
where large variations in carrier concentration are observed
within short distances, for example in the 2DEG [32]. The
dense mesh and large dimensions of the HEMT make a full
3-D TCAD approach very time consuming. Therefore, up to
now, only 2-D FEM device electrothermal simulations have
been performed.
830 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015
Fig. 2. Current density, electrostatic potential, and total heat distribution
inside the HEMT structure during ON-state operating conditions. Most of the
generated heat is located under the drain side of the gate edge.
B. 2-D FEM Electrothermal Device Simulation
A thermodynamic transport model implemented in
Sentaurus device is used for the simulation of the
HEMT characteristics. The standard Poisson equation, con-
tinuity equations for electrons and holes, and thermoelectric
power equation are solved. The simulated characteristics at
different temperatures have been used for the extraction of the
model parameters and temperature-dependent coefficients of
the equivalent electrical circuit model described in Section IV.
Proper location of the spot where heat generation occurs is
important for determining the placement of the heat sources in
the thermal model. 2-D simulations help to analyze the internal
behavior of the device. Referring to [33] and device simula-
tions, most of the heat generated during ON-state operating
conditions is located at the drain side of the gate electrode
edge, where the product of the gradient of the electrostatic
potential and current density reached the maximum (Fig. 2).
IV. 3-D MIXED-MODE ELECTROTHERMAL SIMULATION
Our designed 3-D electrothermal simulation combines the
temperature-dependent equivalent electrical circuit model of
the structure and the thermal model of the whole system. Both
models and the simulation methodology are described in the
following.
A. Analytical Circuit Model Description
The core of the HEMT equivalent circuit model is a
behavioral compact model [4], [34], [35]. The model (Fig. 3)
consists of current sources, which represent the Schottky
gate current and the drain–source current. The included resis-
tors RSa and RDa represent the resistivity of the drain/source
access regions. These components are temperature dependent.
The CDS,CGS,andCGD are the nonlinear capacitors. The
accurate Schottky gate current modeling is important for
OFF-state HEMT, where the reverse-biased gate contributes to
minimal OFF-state drain current. Moreover, the high forward
gate current loads driver output of the HEMT. The current
through the Schottky gate is modeled as a thermionic emission
current at forward bias (1) with added tunneling current at
Fig. 3. Equivalent circuit model of the HEMT structure consisting of
resistors and current sources representing parasitic resistance of 2-D electron
gas (2DEG), Schottky gate current, and drain–source current. The components
are temperature dependent and driven by the temperature on the Pthermal
node.
Fig. 4. I–Vcharacteristics of the gate electrode at different temperatures
and graphical representation of the model coefficients.
reverse bias (2). The equations are taken from [36] and [37].
They are simplified to obtain minimum important coeffi-
cients and temperature dependence is added according to the
2-D FEM simulation and measurement
Ite(GS,GD)=Is(T)·expVGS,GD
nte0 +nteT·T−1(1)
It(GS,GD)=Is(T)·exp−VGS,GD
nt0+ntT ·T−1
−1
+It(T)−1
−1
(2)
with
Is,t(T)=Is0,t0·exp(IsT,tT ·T)(3)
where Is0and IsT are the saturation current and temperature
coefficient of saturation current, respectively. The nte0,nteT,
nt0,andntT are the slopes of the thermionic emission and tun-
neling currents and their temperature dependences. It0and ItT
are the saturation of the tunneling current and its temperature
coefficient, respectively. Fig. 4 compares the results of the
analytical circuit model with 2-D FEM model simulation and
measurement of the I–VSchottky gate electrode characteris-
tics at different temperatures and graphical representation of
the model coefficients in (1), (2), and (3).
CHVÁLA et al.: ADVANCED METHODOLOGY 831
In the case of HEMTs and MESFETs, the drain–source cur-
rent source IDS is usually modeled by the empirical Angelov
expression (4) which is a product of three functions [4]. The
first part characterizes the dependence of IDS on gate voltage
VGS, and the second and the third parts characterize the slope
in the saturation region and the linear region of the output
characteristics, respectively
IDS =FA(VGS)·FB(VDS)·FC(VDS)(4)
with
FA(VGS)=Ipk ·(1+tanh(ψ)) (5)
FB(VDS)=(1+λVDS)(6)
FC(VDS)=tanh(αVDS)(7)
where ψis a function of VGS dependence with P1,2,3poly-
nomial coefficients (8), λis the saturation slope, and αis
a function of the initial increasing slope of the output charac-
teristics
ψ=sinh[P1(VGS −Vpk)+P2(VGS −Vpk)2
+P3(VGS −Vpk)3].(8)
The Ipk and Vpk in (5) and (8) are the peak drain current and
drain voltage at the transconductance maximum, respectively.
We modified the Angelov model to implement the
temperature-dependent behavior. The first function of (4),
the VGS dependence FA(VGS), is replaced by an exponential
function
FA(VGS)
=IVt0 exp(IVtTT)
·exp (sln0 +slnTT)VGS −Vt0−(slin0 +slinTT)
FB(VGS)·FC(VGS)
(9)
where Vt0is the threshold voltage, IVt0 and IVtTare the
current at the threshold voltage and the temperature coefficient
of current at the threshold voltage, respectively. The sln0,
slnT,slin0,andslinTrepresent the slopes in the exponential
and linear parts of the transfer characteristics and their
temperature dependences. This modified approach leads to
better and simpler extractions of parameters for the slope
and its temperature dependence in linear and exponential
parts of the transfer characteristics. The output and transfer
characteristics obtained from the analytical circuit model,
2-D FEM model simulation, and measurement of the HEMT
are compared in Fig. 5. Influence of the model parameters
in (9) to characteristics is also depicted.
The additional pin P of the proposed model represents an
input from the heat source of power equal to the total power
dissipated in the HEMT. The temperature Ton the node drives
the nonlinear temperature-dependent HEMT behavior.
The designed circuit model of the HEMT is implemented to
Sentaurus device using CMI. CMI provides an implementation
of user-defined compact models in C++ and they are linked
to Sentaurus device at runtime. No access to the source code
of Sentaurus device is necessary.
Fig. 5. 2-D FEM simulation, analytical circuit model simulation, and
measurement of output (top) and transfer characteristics (bottom) of the
analyzed HEMT at different temperatures.
B. 3-D FEM Thermal Model Description
The 3-D model of the structure for thermal simulation based
on the physical and geometrical description of all semiconduc-
tor and metallization layers corresponding to the real device
are created in SDE. The metallization layers are created by
Synopsys layout editor, which allows viewing and editing
the layouts in most of the industry-standard formats includ-
ing GDSII. The thermal conductance and capacitance coeffi-
cients and their temperature dependence are taken from [38]
or from default Synopsys parameter file for all used materials.
The analyzed HEMT is unpackaged and measured on the
wafer level on the top of the thermal chuck of the probe station.
The chuck is also included into the model to ensure accurate
thermal impedance of the whole system. For the applications
of real circuit, the model can be modified replacing the
package, printed circuit board, and cooling assemblies instead
of chuck.
The thermal contacts, which represent thermal heating of
the structure, are placed uniformly under the gate electrode
edge at the drain side, where the heat generation occurs during
the ON-state operation. In this paper, the structure is split
into 10 regions along the gate electrode width. Ten ther-
mal contacts are placed uniformly along both gates where
each contact corresponds to one HEMT region. The thermal
contacts are generated automatically by a directly supported
Tcl program cycle in the input command file, which allows
simple definition of their location by the user. The structure
boundary conditions are set to account for the heat sink to the
surrounding environment. The value of thermal conductance
20 W/m2·K represents heat conduction from the chip and
chuck surface to the air [39].
832 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015
Fig. 6. Circuit diagram of the electrothermal mixed-mode simulation.
Equivalent HEMT circuit model is connected to 3-D thermal model by the
thermal nodes. Heat flux and temperature exchange is provided via thermal
nodes.
C. 3-D Mixed-Mode Electrothermal Simulation
In our proposed methodology for the fast 3-D electrothermal
simulation, the 3-D FEM thermal model and the electrical
circuit model of the HEMT are directly connected using
a mixed-mode setup. The structure is split into 10 regions
along the gate electrode width. Each region represents one
equivalent temperature-dependent electrical circuit model. The
HEMT regions are electrically connected considering parasitic
resistances of the gate, source, and drain metallization. The
mixed-mode setup is built to allow heat flux calculated in
the circuit model to the thermal contacts of the 3-D thermal
model via thermal nodes (Fig. 6). Heat generation and heat
transfer are calculated in the FEM model. The temperatures
on the thermal nodes are taken to drive the temperature-
dependent electrical parameters of the HEMT circuit model.
The short time of simulation is provided by calculating only
the heat equation in the 3-D FEM model, reduction of the mesh
optimized for thermal flow, and fast solving of the equivalent
circuit electrical model.
V. SIMULATION RESULTS AND VALIDATION
The proposed methodology of electrothermal simulation has
been used to analyze the properties of a power GaN HEMT.
Fig. 7 shows a comparison of the measured and simulated
output characteristics for two different measurement setups.
The first setup connects only Source 1 to the ground (the
Source 2 is floating), so only one gate finger is active. The
second setup connects both sources (Sources 1 and 2) to
the ground and both gate fingers are active. The temperature
interaction between the gate fingers for the second setup
shows a drop of the output characteristics, which is caused by
a higher structure temperature compared with the first setup
(Fig. 8 [Cross section A]). Moreover, there is an additional
voltage drop in the metal resistance caused by doubled current
Fig. 7. Comparison of measured and simulated output characteristics for
grounded only Source 1 and both Sources 1 and 2.
Fig. 8. Temperature distribution of the HEMT for VDS =15 V and
VGS =1 V (top). (Cross section A) Comparison of the temperatures across
the gate electrodes for simulation employing only Source 1 and both
Sources 1 and 2. (Cross section B) Temperature and current distributions
inside the HEMT structure along the gate electrode.
flowing through drain metallization layer. Its main impact
is in the linear region of the output characteristics. In the
case of the 2-D simulation and assumption that the current
is proportional to the total gate width, there is no difference
between employing only one and both sources. Moreover, the
2-D device simulation considers homogeneous distributions
of all parameters in the third dimension. The 3-D heat flow
CHVÁLA et al.: ADVANCED METHODOLOGY 833
and inhomogeneous behavior along the whole structure are
neglected. Our designed 3-D electrothermal simulation splits
the structure along the gate into several parts, which allows
analysis of the inhomogeneous distribution of temperature and
of the electrical properties. The inhomogeneous distributions
of temperature and current along the gate electrode are shown
in Fig. 8 [Cross section B]. The lower temperature and higher
current density at the HEMT edge regions are caused by more
effective cooling of the structure edges compared with the
central region.
The 2-D FEM electrothermal simulation of the HEMT using
about 16500 elements takes ∼5 min. Moreover, the 2-D sim-
ulation does not consider the thermal flow and distributed
parameters of the structure in the third dimension. The full
3-D structure FEM electrothermal simulation would be very
time consuming due to the dense mesh and large dimensions
of the structure and was not attempted. The 3-D mixed-mode
electrothermal simulation based on direct coupling between
the 3-D thermal FEM model and circuit electrical model takes
about half a minute for the designed full structure model using
100000 mesh elements and 2 ×10 HEMT regions. The shorter
time consumption using the proposed method is an important
advantage for the full structure analysis.
VI. CONCLUSION
Fast 3-D electrothermal simulation based on the direct
coupling FEM thermal and circuit electrical simulation in
the mixed-mode Sentaurus device setup was designed and
verified. The designed methodology is developed for Synopsys
TCAD Sentaurus environment and allows decreasing of the
simulation time for complicated 3-D structures. The power
InAlN/GaN HEMT was used to perform validation of the pro-
posed electrothermal simulation. The equivalent temperature-
dependent large signal circuit model of a power HEMT was
designed and implemented to Sentaurus device for simulation
at runtime. The simulation approach helps to assess the device
properties by means of evaluating both temperature and current
distributions in the HEMT structures operating under different
conditions and topology. In comparison with 2-D FEM elec-
trothermal simulations, the implemented 3-D thermal flow and
distributed parameters of the HEMT provide more realistic
simulation results. The advantages of the proposed method
are the relative simplicity of implementation, the speed of
simulation, and the capability of a full analysis of complex
structures. A very good agreement between the simulation
and the measurement confirms the validity of the proposed
methodology.
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Aleš Chvála received the M.Sc. and Ph.D. degrees
in electronics from the Slovak University of Tech-
nology in Bratislava (STUBA), Bratislava, Slovakia,
in 2005 and 2009, respectively.
He has been a Researcher with the Institute of
Electronics and Photonics, STUBA, since 2007.
His current research interests include the TCAD
and SPICE electrothermal modeling, simulation, and
characterization of Si and GaN-based devices.
Daniel Donoval (M’97) received the M.Sc. and
Ph.D. degrees in electronics from the Slovak Uni-
versity of Technology in Bratislava (STUBA),
Bratislava, Slovakia, in 1976 and 1981, respectively.
He has been with the Department of Microelec-
tronics, STUBA, since 1981, where he is currently
a Professor and the Director of the Institute of Elec-
tronics and Photonics. His current research interests
include the technology and characterization of semi-
conductor structures and devices.
Alexander Šatka was born in Martin, Slovakia, in 1960. He received
the M.Sc. and Ph.D. degrees in electronics from the Slovak University of
Technology in Bratislava (STUBA), Bratislava, Slovakia, in 1984 and 1995,
respectively.
He has been with the Department of Microelectronics, STUBA, since
1988, where he is currently a Professor of Electronics with the Institute of
Electronics and Photonics.
Marián Molnár received the M.Sc. degree in
electrical engineering from the Slovak University
of Technology in Bratislava, Bratislava, Slovakia,
in 2010, where he is currently pursuing the
Ph.D. degree with the Institute of Electronics and
Photonics.
He joined the Advanced Materials and Device
Analysis Group, Institute for Microelectronics, Tech-
nische Universität Wien, Vienna, Austria, in 2012.
He is currently a Researcher with the Institute of
Electronics and Photonics.
Juraj Marek received the M.Sc. and Ph.D. degrees
in electronics from the Slovak University of Tech-
nology in Bratislava (STUBA), Bratislava, Slovakia,
in 2007 and 2011, respectively.
He has been a Researcher with the Institute of
Electronics and Photonics, STUBA, since 2006. His
current research interests include TCAD modeling
and simulation and characterizations, and parameters
extraction of power devices.
Patrik Príbytný received the M.Sc. and
Ph.D. degrees in electronics from the Slovak
University of Technology in Bratislava (STUBA),
Bratislava, Slovakia, in 2009 and 2013, respectively.
He has been a Researcher with the Institute of
Electronics and Photonics, STUBA, since 2010. His
current research interests include the characterization
of semiconductor structures and devices supported
by 2-D/3-D electrothermal modeling and simulation.
