ELECTRICAL PROPERTIES AND SCHEMATIC BAND DIAGRAMS OF Sn/PS/p-Si HETEROJUNCTION

Abstract

This paper presents a study of Sn/PS/p-Si heterojunction device which is fabricated by growing Sn thin
film onto p-type porous Si substrate by using thermal evaporation deposition and electrochemical etching
(ECE) in crystalline p-Si method. Effect etching current density on the morphology of the porous silicon
surface is checked using atomic force microscopy AFM. Current–voltage (I–V), capacitance–voltage (C–
V) characteristics. The ideality factor and series resistance are found to be large than the one (11.18 and
25 kΩ) respectively by the analysis of the dark I–V characteristics of Sn/PS/p-Si. While the analysis of
the dark C–V, the built-in voltage and carrier’s concentrations are found to be 0.59V and 1.1×1017cm-3
respectively. These characteristics are interpreted by assuming the abrupt heterojunction model from C-V
measurement. The barrier height potential is measured by both I–V and C–V which is found to be
0.74eV. The Energy band diagram of heterojunction relevant by I-V and C-V measurements is sketched.
Keywords: porous silicon, electrochemical etching (ECE), Schottky Barrier, AFM

Full text

ELECTRICAL PROPERTIES AND SCHEMATIC BAND DIAGRAMS OF Sn/PS/p-Si
HETEROJUNCTION
Hasan A. Hadi1 and Intesar H. Hashim1
Department of Physics, College of Education, Al-Mustanseriyah University, Baghdad-Iraq
ha_yaba@yahoo.com
Received 02-04-2014, revised 18-04-2014, online 22-04-2014
ABSTRACT
This paper presents a study of Sn/PS/p-Si heterojunction device which is fabricated by growing Sn thin
film onto p-type porous Si substrate by using thermal evaporation deposition and electrochemical etching
(ECE) in crystalline p-Si method. Effect etching current density on the morphology of the porous silicon
surface is checked using atomic force microscopy AFM. Current–voltage (I–V), capacitance–voltage (C–
V) characteristics. The ideality factor and series resistance are found to be large than the one (11.18 and
25 kΩ) respectively by the analysis of the dark I–V characteristics of Sn/PS/p-Si. While the analysis of
the dark C–V, the built-in voltage and carrier’s concentrations are found to be 0.59V and 1.1×1017cm-3
respectively. These characteristics are interpreted by assuming the abrupt heterojunction model from C-V
measurement. The barrier height potential is measured by both I–V and C–V which is found to be
0.74eV. The Energy band diagram of heterojunction relevant by I-V and C-V measurements is sketched.
Keywords: porous silicon, electrochemical etching (ECE), Schottky Barrier, AFM
I. INTRODUCTION
The formation of PS (porous silicon) layers on crystalline Si (c-Si) wafers using electrochemical
etching (ECE) exhibits photoluminescent and electroluminescent properties similar to those of
semiconductors with direct energy gap [1].Porous silicon composites provide modified
functionality comparing to as-prepared porous silicon and expand its applicability. Porous
structure of the material and large internal surface imply high sensitivity of physical and
chemical properties [2]. In all PS applications, information about the pore size and their
distribution and surface chemistry and their dependence on the fabrication conditions plays
decisive role. Correlation of observed physical properties with the morphology of PS films and
the relationship between PS morphology and preparation parameters is necessary. Principal
parameters controlling macro pore formation depend on the properties of silicon substrate
(crystal orientation, doping), anodizing solution and temperature [3]. Porous silicon
photoconductors are commonly fabricated by depositing aluminium film on top of oxidized
porous silicon structure. The passivation of the surface by oxidation could improve the external
quantum efficiency of porous silicon photodiode [4]. The morphology of porous silicon formed
Journal of Electron Devices, Vol. 20, 2014, pp. 1701-1710
© JED [ISSN: 1682 -3427 ]

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
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by electrochemical etching of Si crystals was investigated by atomic force microscopy
(AFM).Today, the nanoporous silicon is very interesting material for both its optical and
electrical properties. Since the observation of strong room temperature visible
photoluminescence from nanoporous silicon, there have been extensive researches to develop
optoelectronics [5].
The practical applications are oriented towards the fabrication of new structures and devices.
The compatibility of the nanocrystalline silicon-based materials with the classic mono- and/or
polycrystalline silicon (bulk or thin films) permits the use of these new materials for the
integrated micro- and optoelectronics, photonic crystals, biomedical applications or efficient
sensors [6].When metal and semiconductor are in intimate contact because the work functions
of both materials are different, built-in barrier is created at their interface, which is called
Schottky barrier [7]. The barrier height is directly related to the difference in the Fermi levels
between the metal and semiconductor material. The larger the difference is, the higher will be
the barrier height is. The barrier opposes the flow of the free charge carriers from one side to
another. The electrical behavior of M- S contacts is identified depending on the barrier height
[7, 8].Schottky suggested that the rectifying behavior could arise from potential barrier as a
result of the stable space charges in the semiconductor. This model is known as the Schottky
Barrier (SB). Metal semiconductor devices can also show non-rectifying behavior; that is, the
contact has negligible resistance regardless of the polarity of the applied voltage. Such a contact
is called an ohmic contact. The C-V characteristic of heterojunction is one of the most important
measurements since it determines different parameters such as built-in potential, junction
capacitance and junction type.In this work, Sn films were deposited onto porous layer /Si wafers
by thermal evaporation to form rectifying junctions. The electrical properties of the junctions
were determined by current-voltage (I-V) and capacitance-voltage (C-V) measurements.
II. EXPERIMENT
Several methods are developed to make the porous layer with wide variation of pore
morphologies having the pore dimensions from micro to nanometers. In most cases, the porous
silicon structure is formed by electrochemical etching of Si wafers in electrolytes including
hydrofluoric acid (HF) and methanol. Figure 1 illustrates the Cross-sectional view of lateral
anodization cell used to fabricate the porous layer reported here. PS layers were prepared by the
anodization of (111) oriented, p-type silicon substrates in 1:1 solution of hydrofluoric acid HF
(40%) and methanol at current density of 33 mA/cm2 for 11 min in the dark as shown in same
figure. The substrate material p-type silicon wafers with resistivity of 11-16 Ω.cm
corresponding with doping density of .

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
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Figure 1: Cross-sectional view of lateral anodization cell.
Before anodization, Ohmic contacts were deposited on the backside of the wafers by Al
evaporation followed by oxidization in air at 300 for 30 min. Following anodization, rinsed in
distilled water treated ultrasonically followed by drying in hot air stream. Metallization on PS
has also become another important area of interest, especially in the Schottky diode structure.
The evaporation is performed in vacuum pressure of torr, using an evaporation plant
model “E306 A manufactured by Edwards high vacuum”. After the evaporation process, the
thickness of evaporated film on glass substrate is measured using gravimetric method. To ensure
as uniform current distribution as possible, the samples are coated with thick layer of aluminum
on the backside. The samples are prepared in sandwich configuration, top Sn/PS/c-Si/bottom Al,
the top one (Sn) semi-transparent electrode thermally evaporated thin layer .The rear-side ohmic
contacts were fabricated by the electro-chemical deposition of thick Al film to get sandwich
structure as shown in cross section of Sn/PS/p-Si/Al of figure 2. Dark current – voltage in
forward and reverse directions Sn/PS/c-Si/Al measurements are carried out by applying voltage
supplied to the sample from stabilized d. c. Power supply, type LONG WEI DC PS-305D 30
ranges (-10 to +10) V. The current passing through the device is measured using UNI-T UT61E
Digital Multimeters. The measurement is done under light of different illumination power
densities supplied by Halogen lamp 150W which is connected to variance and calibrated by
power meter. Capacitance-Voltage characteristics of the Sn/PS/c-Si HJ heterojunction are
measured using a LCZ meter at room temperature. The C-V measurements at reverse bias
voltage range from (2-10) V at 200 kHz.
Figure 2: Cross-sectional view of Sn/PS/p-Si/Al metal semiconductor metal structure.

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
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III. RESULTS AND DISCUSSION
Atomic force microscope images of freshly prepared porous silicon two and three dimension
were shown in Figure 3. The irregular and randomly distributed nano-crystalline silicon pillars
and voids over the entire surface can be seen in 3D AFM image. Also shows the surface
roughness and pyramid like hillocks with un-uniform different heights surface. The scanning
area used, is 5µm 5µm. The RMS surface roughness is 3.34 nm. Sz ( ten points height) 25.7
nm, roughness average 2.08nm.
Figure 3: 2D and 3D AFM image of porous silicon prepared at 33 mA/cm2 etched current density and 11min
etching time.
IV. DARK CURRENT-VOLTAGE MEASUREMENTS:
Dc measurements were made in the dark of Sn/PS/p-Si/Al structures at room temperature.
Figure 4 shows the I-V characteristics of the heterojunction Sn/PS in the range −10 to +10 V in
a semi log plot at 33mA/cm2 etching current density and 11min etching time. I-V characteristic
of the heterostructure, Sn/PS/c-Si, is shown in Figure 4. I–V characteristics can be described by
the thermionic emission model [9] and the equation, which describes the current as a function of
the applied voltage of the junction can be expressed as [10]:
] (1)
here, Io is the reverse saturation current and is given as:
(2)
Where Richardson constant, n the value of ideality factor, V is the applied voltage and T is
the temperature in Kelvin. The barrier height and ideality factor of Sn/PS surface type Schottky
diode is calculated from the current-voltage characteristics by using the following equation [11]:
) (3)
. (4)

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
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Figure 4: log (I) –V curves of a Sn/PS/n-Si/Al structure.
I-V characteristics give information about the junction properties such as rectification factor
(Rf), Ideality factor (n), Series resistance (rs) and Saturation current (Is). The electrical
parameters of the heterojunction Sn/PS/n-Si/Al is presented in table (1). These parameter were
obtained from dark (I-V) characteristics. The experimental data presented in Figure 4 were fitted
with a simple diode model [12]. Rectification factor which represented the ratio of the forward
current to the reverse current at a certain applied voltage calculated .The junction Sn/PS/p-Si
exhibits rectifying characteristics showing diode-like behavior of rectification factor was 3.6 at
V.
Figure 5: log (I) - V measurement.
The reverse saturation current, barrier height and ideality factor of the diode can be determined
from the forward-biased characteristic in figure 5, and have been calculated using equations
(3 and 4). It has been found that the reverse saturation current ( ), barrier height ( ) and
ideality factor of Sn/PS/p-Si junction is 1.12 µA, 0.74 eV and 11.8 respectively. Increasing
saturation etching current is due to the effect of the interface layer between PS/n-Si has large
amount of pinning, which acts as a defect in the interface and lead to increase saturation etching

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
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current density and hence to decreasing the barrier height of PS [12].When the structure has a
series resistance and interface states, ideality factor (n) becomes higher than unity as showing in
the table (1); most practical Schottky diodes shows deviation from the ideal thermionic theory.
The fact that such recombination currents are flowing not homogeneously in the structure. The
high ideality factor can be attributed to the sum of the ideality factors of the individual
rectifying junctions (i.e., the actual PS/c-Si heterojunction junction and Schottky diodes at the
Sn/PS or the two metal-semiconductor junctions (Sn/PS, c-Si/Al) of a diode ideally have Ohmic
characteristics) [13, 14] The nature of porous silicon implies a very large effective surface area,
and consequently, a large concentration of dangling bonds. Porous layers act as series resistance
in Sn/PS/c-Si/Al structure, so we have a large value of dynamic (series) resistance (see table 1).
Table 1: Values obtained from I-V measurements
Rectification
factor
( )
Ideality
factor
(n)
Series
resistances
() kΩ
Saturation
current
( ) µA
Barrier
potential
( ) eV
3.67
11.18
25
1.12
0.74
IV.1 Dark capacitance-voltage measurements:
It is known that a capacitance of a Schottky diode can be represented by the relation between
voltage and capacitance which expressed as a standard Mott–Schottky relationship [15]:
(5)
The plots of versus V is linear which indicates the formation of Schottky junction
where C is the diode capacitance, is the built in voltage, is the semiconductor dielectric
constant, is the permittivity in vacuum, is the applied voltage, q is the charge, A is the
diode active area, and is the charge carrier concentration. By plotting versus V as
shown in figure 5 and applying Equation 5, a straight line is obtained, the slope gives the free
carrier concentration and it was found to be by applying the relation:
(6)
Also, the intercept at = 0 gives the built-in-voltage Vbi by linear fitting as shown in figure 6
The capacitance of the Sn/PS/p-Si heterojunction was measured at a low frequency of 200 kHz
in dark and at room temperature as shown in left inset of figure 6 the junction capacitance is
inversely proportional to the bias voltage. There was a decrease in the capacitance at bias.

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
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Figure 6: of Sn/ PS/p-Si/Al structure vs. the applied voltage and left inset of figure the Junction capacitance
of Sn/PS/p-Si/Al structure vs. the applied voltage.
The value of barrier height can be obtained by using following relation []:
(7)
where, is the accepter concentration, is built in potential and is the effective density
of states in the conduction band of silicon is calculated from the slope of plot as
shown in table (2).
Table 2: Values obtained from C-V measurements
Effective
carrier density
Built in
voltage
(V)
Capacitance
Co (nF)
barrier
height
(eV)
1.1E+17
0.59
2.31
0.743
As observed from the figure 6, variation is linear in the voltage range studied
indicating that the junction is of abrupt nature. That means the carrier concentration will be
constant at the depletion layer [16]. That means the carrier concentration will be constant at the
depletion layer. The reduction in the junction capacitance with increasing the bias voltage
results from the expansion of depletion layer with the built-in potential. The linearity of this
dependence indicates that the junction is reasonably interpreted by assuming that an abrupt

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
8
heterojunction, this property give an indication of the behavior of the charge transition from the
donor to the acceptor region, that mean the depletion layer is constant
The thickness of the surface space-charge region W can be given by:
(8)
where is the relative dielectric constant, is the elementary charge, is the built in voltage
at the surface see Figure 6 and is the concentration. We obtain W=15 nm Therefore, any
change in the concentration will change the depletion layer width
IV.2 Energy gap of porous silicon:
The photosensitivity of the photodetector is investigated in the wavelength with the aid of Joban-
Yvon monochromatic and standard Si power meter. The value of energy gap is determined by the
photoresponse spectrum curve between photocurrent and energy of quanta of the incident light.
In the case of nano- or micro-porous silicones, quantum confinement causes spatial fluctuations
of the effective band gap as can be seen in Figure 7, so as [17, 18] reported that the porous layer
behaves as wide band semiconductor sensitive to the visible light. The photoelectrical method of
definition of effective band gap in the vicinity of PS/c-Si heterojunction is proposed. As it is
known the width of the band gap of crystal silicon is 1.12 eV. The enhancing of band gap in PS is
connected with quantum-size effect. The main quantum confinement effect is represented by the
appearance of new energy levels in the silicon band gap. Band diagram of Sn/PS/p-Si/Al
heterojunction using Anderson model indicated in figure 8.
Figure 7: The spectrum of photocurrent of Sn/PS/p-Si/Al structure vs. incident photon energy.

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
9
V. CONCLUSIONS
In this work the preparation of nanocrystalline porous silicon (PS) by electrochemical
anodization has been described .Morphology and electrical properties of porous silicon have been
mentioned. Sn was chosen as the top semitransparent metal electrode to fabricate the Sn/PS/p-
Si/Al photodetector heterojunction structure. The junctions were characterized by I-V and C-V
studies and were confirmed to behave as Schottky devices. No difference is observable between
the values of barrier height calculated by I-V or obtained from C-V measurement.
References
[1] L.T.Canham, "Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers",
Appl. Phys. Lett., 57, 1046-1048 (1990).
[2] Juraj Dian, Martin Konečný, Gabriela Broncová, Martin Kronďák and Iva Matolínová, "Electrochemical
fabrication and characterization of porous silicon/polypyrrole composites and chemical sensing of organic
vapors", Int. J. Electrochem. Sci., 8, 1559-1572 (2013).
[3] N. Jeyakumaran, B. Natarajan, S. Ramamurthy and V. Vasu, "Structural and optical properties of n- type porous
silicon– effect of etching time", International Journal of Nano science and Nanotechnology, 3, 45-52 (2007).
[4] C. Li. Tsai, KH., JC. Campbell and A. Tasch, "Photodetectors fabricated from rapid thermal oxidized porous Si",
Appl. Phys. Lett., 62, 2818 (1993).
[5] G. Garcia Salgado, T. Diaz Becerril, H. Juarez Santiesteban and E. Rosendo Andres, "Porous silicon organic
vapor sensor", Opt. Mater, 29, 51-55 (2006).
[6] M. L. Ciurea, V. Iancu and I. Stavarache, "Quantum confinement modeling of electrical and optical processes in
nanocrystalline silicon", Journal of Optoelectronics and Advanced Materials, 8, 2156 -2160 (2006).
X Ps=1.38 eV
X Si=1.11eV
EC
EF
EV
∆EC= .278eV
Eg Ps= 2.26 eV
∆EV= .842eV
n-Si
p-Ps
Eg,Si= 1.12eV
Figure 8: Band diagram of Sn/PS/p-Si/Al heterojunction

Hasan A. Hadi and Intesar H. Hashim, Journal of Electron Devices 20, 1701-1710 (2014)
10
[7] Salinas, O. H., Lpez-Mata, C., Hu, H., Nicho, M. E. and Snchez, A., "Metal contact properties of poly3-
octylthiophene thin films", Solar Energy Material & Solar Cells, 90, 760-769 (2006).
[8] Sze, S.M., "Physics of semiconductor devices", (1990), John Wiley & Sons.
[9] R.Jarimavičiūtė, Žvalionienė, V.Grigaliūnas, S.Tamulevičiu, and A. Guobienė, "Fabrication of porous silicon
microstructures using electrochemical etching", Materials Science. 9, 1392–1320 (2003).
[10] Z.Ahmad, M.H.Sayyad, M.Yaseen, and M. Ali, "Investigation of 5,10,15,20-Tetrakis (3’,5’-di-tert-butylphenyl)
porphyrinatocopper (II) for Electronics Applications" World Academy of Science, Engineering and Technology,
76, 811-814 (2011).
[11] A.A.M.farag, "Structure and transport mechanisms of Si/porous Si n–p junctions prepared by liquid phase
epitaxy", Applied Surface Science, 255, 3493-3498 (2009).
[12] Felipe A Garc'es, Raul Urteaga, Leandro N Acquaroli1, Roberto R Koropecki and Roberto D Arce, "Current-
voltage characteristics in macroporous silicon/SiOx/SnO2:F heterojunctions", Nanoscale Research Letters, 7, 419-
430 (2012).
[13] M.Pattabi, S.Krishnan,X. Ganesh ,and X.Mathew, "Effect of temperature and electron irradiation on the I–V
characteristics of Au/CdTe Schottky diodes"," Solar Energy, 81, 111-116 (2007).
[14] K.S.Khawla, A.A.Amany, and A.M.Maysaa, "effect on rapid thermal oxidation process on electrical properties
of porous silicon", Eng. and Tech Journal, 27, (2009).
[15] W.C.Huang, T.C.Lin, C.T.Horng, and C.C.Chen, "Barrier heights engineering of Al/p-Si Schottky contact by a
thin organic interlayer", Microelectronic Engineering 107, 200–204 (2013).
[16] G.Al un, and M. CArikan, "An Investigation of Electrical Properties of Porous Silicon", Tr. J. of Physics, 23,
789 -798 (1999).
[17] D.Timokhov, F.Timokhov, "Avalanche multiplication of charge carriers in nanostructured porous silicon",
Semiconductor Physics, Quantum& Optoelectronics, 6, 307-310 (2003).
[18] D. F. Timokhov, F. P. Timokhov, "Determination of Structure Parameters of Porous silicon by the Photoelectric
Method", Journal of Physical Studies, 8, 173-177 (2004).