Article

Comparative Study of Schottky Barrier Heights of the Different Metals Based on Porous Silicon Prepared by Photo-Electrochemical Etching (PECE)

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  • Mustansiriyah University
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Abstract

In this paper, we present the fabrication of Schottky devices by the photo electrochemical etching of nano crystalline silicon layer on single-crystal silicon substrates. Porous silicon layers have been prepared from n-type silicon wafers of (111) orientation. XRD results revealed that the porous layer was nanocrystalline in nature. We have estimated crystallites size from X-Ray diffraction about nano-scale for porous silicon. Atomic Force Microscopy AFM shown the etching possesses inhomogeneous microstructures and confirms the nano-metric size. The influence of the inhomogeneous of porous layer on the Schottky barrier height, built in voltage, series resistance, shunt resistance, and donor concentration of the devices was studied. I–V methods and dark I–V measurements, which demonstrate good rectifying behavior. Measurements of Schottky barrier height from (I–V) and (C–V) of Au/PS/n-Si, Sb/PS/n-Si, and Sn/PS/n-Si structures (Heterojunction) have been described. The ideality factor of diodes which deduced from I–V characteristics confirms that the recombination current is dominated at low voltage. C–V investigations indicate that the diodes are abrupt type.

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... Transition elements such as nickel and cadmium have been used as photoconductors (metal windows) and contact materials in a variety of optoelectronic and microelectronic applications [1,2]. Electrochemical etching, where silicon as an anode and an electrolyte is etched with an external power supply and light assistance [3], is an efficient and simple way to prepare porous structures, and so it has been extensively used in many areas of research and in numerous applications. ...
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In this work, nanocrystalline porous silicon (PSi) was prepared by the photo-electrochemical etching (PECE) technique. A comparison study between the optoelectronic properties of double junctions Ni/PSi/c-Si and Cd/PSi/c-Si photodetectors is reported. The Ni and Cd thin films were deposited on the porous silicon layers by the thermal evaporation technique. The structural, electrical, and optoelectronic properties of Cd/PSi/n-Si and Ni/PSi/c-Si devices were examined at room temperature. The XRD analysis confirmed the formation of the nanocrystalline structure of the PSi layer. Scanning electron microscope (SEM) studies reveal the formation of circular pores with an average diameter of 250 nm. The dark and illuminated I-V characteristics of the photodetectors are investigated at room temperature, and the junction characteristics of the Cd/PSi/c-Si junction are better than those of the Ni/PSi/c-Si junction. The maximum responsivity of the Cd/PSi/c-Si photodetector is 1.47AW⁻¹ at 400 nm, while the maximum responsivity of Ni/PSi/c-Si was about 1.45AW⁻¹ at 540 nm. The external quantum efficiency (EQE) of Cd/PSi/c-Si and Ni/PSi/c-Si photodetectors was 450% and 330% at 400 nm, respectively.
... Photodetectors are used for accurate measurement of light intensity in science and industry [11]. Among several types of photodetectors like p-n junctions, p-i-n diodes, p-i-n diodes, schottky barrier detectors and metal-semiconductor-metal (MSM) photodetectors, the advantages of MSM devices such as simplicity of fabrication, high response speed and reduction in noise are unique [12]. The study of the mechanisms of charge carrier transport, have gain great importance according to its wide applications such as light-emitting devices, photodetectors, solar cells, chemical, and other fields of science [13]. ...
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We have studied the dependence of photodetector photocurrent on incident power density of light with anodization current and time. The fabrication of Al/PS/p-Si photodetector heterojunction PDH by electrochemical etching method ECE and semi-transparent Al films in thickness range of 80 nm are deposited by thermal evaporation on porous silicon layers to investigate the photocurrent -voltage characteristics of the PDH. When the anodization current varied from 20 to 60 mA, the photocurrent PC was increase according to the anodization parameters at 1.2 mw/cm2 power density. The results also show that the short current Isc and open circuit voltage Voc saturate at high power density. The difference in the value of Voc and Isc at different etching current density is related to the Si nano crystallites layer thickness and the porosity which itself is greatly affected by the etching current density.
... To study the PS/c-Si junction properties, I-V measurements, usually, provide a valuable source of information about the junction properties. In general, the electrical properties of the Schottky contacts on n-Si type, p-Si type and the other semiconductor have been investigated by large number of research groups by different method [10]. Analysis of current-voltage I-V characteristics of Al/PS Schottky junction allows us to understand different aspects of current transport. ...
Article
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In this work, porous silicon layers PS were fabricated on p-type crystalline silicon wafers using electrochemical etching ECE process. Al films were deposited onto porous layer /Si wafers by thermal evaporation to form rectifying junction. An investigation of the dependence on applied etching time to formed PS layer was studied. Effect etching time on the electrical properties of porous silicon is checked using Current–voltage I–V characteristics. The ideality factor and dynamic resistances are found to be large than the one and 20 (kΩ) respectively by the analysis of the dark I–V characteristics of Al/PS/p-Si heterojunction
Article
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In this work, nanocrystalline porous silicon layers were fabricated by photoelectrochemical etching of n type silicon (n-Si) wafer. Different etching time (15, 20, 25 and 30) min and 10 mA/cm 2 current density were tested to study their effect on the formation nanosized pore array. Porous silicon is investigation by X-Ray diffractions (XRD) and atomic force microscopy properties (AFM). Crystallites size was estimated by X-Ray diffraction. Atomic Force microscopy confirmed the nonmetric size Chemical Anodization the electrochemical etching was noticed of PS. The atomic force microscopy investigation showed the rough silicon surface which increased with etching time porous structure nucleates which leads to an increase in the depth and width (diameter) of surface pits.
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Photodetector Sn/PS/p-Si was fabricated based on porous silicon PS layer prepared by electrochemical-etching technique ECE of p-type silicon wafers. The porous layer formation was confirmed by AFM and SEM studies. Surface analysis by atomic force microscopy AFM showed that the morphology of the porous layer is nanostructures. The photodetector has good linearity characteristics and shows a good photoresponse in visible region.The photosensitivity of the detector measured at a wavelength 500nm and 600í µí²m, at reveres bias (1)V equals 2.64 and 3.19 A/W.These values correspond to quantum efficiency 66%. The normalized detectivity D* of the fabricated Sn/PS/p-Si photodetector at wavelength of 500 and 600nm were found to be about í µí¿. í µí¿“í µí¿í µí¿ × í µí¿í µí¿Ž í µí¿í µí¿
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In this paper, formation of a nano-crystaline porous silicon layer on n-type and P-type crystalline Si substrates prepared by the electrochemical etching and photo-electrochemical etching techniques (in order to fabricate heterojunctions photodetector) has been studied. The fabricated Al/PS/n-Si/Al photodetector has responsivity to white light higher than that for Al/PS/p-Si/Al photodetector. The values of minority carrier life time obtained are 125 and 208 ls for junctions made on n-type silicon substrates at etching time of 5 and 10 min respectively. While, junctions made on p-type silicon substrates prepared at the same etching time have life time of 83–113 ls.
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By an analysis of the exchange of carriers through a semiconductor junction, a general relationship for the nonequilibrium population of the interface states in Schottky barrier diodes has been derived. Based on this relationship, an analytical expression for the ideality factor valid in the whole range of applied bias has been given. This quantity exhibits two different behaviours depending on the value of the applied bias with respect to a critical voltage. This voltage, which depends on the properties of the interfacial layer, constitutes a new parameter to complete the characterization of these junctions. A simple interpretation of the different behaviours of the ideality factor has been given in terms of the nonequilibrium charging properties of interface states, which in turn explains why apparently different approaches have given rise to similar results. Finally, the relevance of our results has been considered on the determination of the density of interface states from nonideal current-voltage characteristics and in the evaluation of the effects of the interfacial layer thickness in metal-insulator-semiconductor tunnelling diodes. © 1997 American Institute of Physics.
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We propose the first systematical method to control Schottky barrier heights of metal/semiconductor interfaces by controlling the density of interface electronic states and the number of charges in the states. The density of interface states is controlled by changing the density of surface electronic states, which is controlled by surface hydrogenation and flattening the surface atomically. We apply establishing hydrogen termination techniques using a chemical solution, pH controlled buffered HF or hot water. Also, slow oxidation by oxygen gas was used to flatten resultant semiconductor surfaces. The density of interface charges is changeable by controlling a metal work function. When the density of surface states is reduced enough to unpin the Fermi level, the barrier height is determined simply by the difference between the work function of a metal φm and the flat-band semiconductor φFBs. In such an interface with the low density of interface states, an ohmic contact with a zero barrier height is formed when we select a metal with φm < φFBs. We have already demonstrated controlling Schottky and ohmic properties by changing the pinning degree on silicon carbide (0001) surfaces. Further, on an atomically-flat Si(111) surface with monohydride termination, we have observed the lowering of an Al barrier height. Moreover, we found the recovery of an ohmic property after TiC formation at Ti/6H-SiC interface at 700°C whereas conventional 5% HF rinsed Schottky Ti/6H-SiC interfaces still have Schottky properties after TiC formation.
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