Conference Paper

3D-IC System Verification Methodology: Solutions and Challenges

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A verification methodology for 3D-ICs is presented, including connectivity checking and parasitic extraction. An example was given to illustrate a true 3D-IC stack verification using a GDS based flow. The new challenges were presented and the development efforts to respond to those challenges were identified.

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... КомплеКсная, сКвозная интеграция * Для более быстрого вывода на рынок сложных корпусов ИС требуется бесшовная интеграция разработки и верификации всех этапов -от проектирования подложки до радиаторов и крепежных элементов конструкции 1 Mentor, A Siemens Business, маркетинг менеджер в области корпусирования, 2 Институт НМСТ НИУ МИЭТ, руководитель УНЦ, 3 Институт НМСТ НИУ МИЭТ, доцент, ...
Рассматриваются вопросы сквозной интеграции средств проектирования современных корпусов микросхем и микросборок по технологии цифрового двойника: комплексное проектирование составных частей изделия с учетом тепловых характеристик, термомеханических напряжений и целостности сигналов.
A real layout design cutting solution to speed up the post-layout extraction run time is presented. It reduced the extraction run time down to less than 10 min for a huge design block with Electrical Changes Order (ECO) consist of small layout area changes and able to maintain the accuracy within 1%. The solution can be applied to improve the In-Die-Variation (IDV), System-On-chip (SoC) level Electrical Static Discharge (ESD) structure verification and 3D-IC interface verification without accuracy loss with runtime and memory consumption reduction.KeywordsParasitic extractionTransistor level parasitic extractionPost-layout extraction and simulation speed upAnalog design
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