This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those statements, resolution functions, delta delays, and hierarchical component structuring. Based on this model, several extensions to VHDL are proposed, including nondeterministic assignments and unbounded asynchrony. Nondeterminism allows the
... [Show full abstract] specification of environments and of classes of devices. This model naturally captures the meaning of composition of VHDL programs. 1 Introduction When defining a formal semantics for a programming language, it is important to identify key concepts in the language, develop a good formalization of those concepts, and define the rest of the language around this formalization. Such an approach helps unify the formalization effort, and provides insight into the key semantic underpinnings of the language. Furthermore, models of key concepts may suggests extensions to the programming language which a...