Conference PaperPDF Available

3D Simulation of Three-Dimensional Filling Process for Stacked-Chip Scale Packages (S-CSPs)


Abstract and Figures

Encapsulation is one of the key processes in electronic packaging and to protect the integrated circuit chips from environmental and mechanical damages. The most obvious choice for the encapsulation process is transfer moulding due to its capability to mould small parts with complex features. An electronic package that employs transfer moulding is Stacked-Chip Scale Package (S-CSP). However, a computer simulation is one of the tools that could be used to simulate and predict the mould process. It is highly desirable in order to avoid the typical time-consuming procedure of mould design and process optimization by trial and error. In this paper, a fully three-dimensional (3-D) analysis to predict transfer moulding process of S-CSP encapsulation using finite volume method (FVM) based software, FLUENT is presented. The proposed FVM simulation model is built and meshed using GAMBIT. Some simplification is done for the simulation model due to time consumption and complicated geometry of actual S-CSP model. In the analysis, volume of fluid (VOF) technique was used to track the flow front of the encapsulant. The viscosity versus shear rate is plotted and void formation problem also discussed. The numerical results are compared with the previous experimental results and found good conformity. KEY WORDS: Stacked-Chip Scale Package (S-CSP); Finite volume method (FVM), Volume of Fluid (VOF), Front tracking, Void.
Content may be subject to copyright.
3D Simulation of Three-Dimensional Filling
Process for
Stacked-Chip Scale Packages (S-CSPs)
M.F.M.A. Majida, M.Sabri Sidika,M Husaini A.Ba, K. Shahrila, Zainal Nazria, Shukri Zaina, M. Z.
aUniversiti Kuala Lumpur, Malaysian Spanish Institute,
Kulim Hi-Tech Park, Kedah
bSchool of Mechanical and Aerospace Engineering,
Universiti Sains Malaysia, Engineering Campus,
Seri Ampangan, 14300 Nibong Tebal, Seberang Perai Selatan, Pulau Pinang, Malaysia.
Abstract—Encapsulation is one of the key processes in electronic
packaging and to protect the integrated circuit chips from
environmental and mechanical damages. The most obvious
choice for the encapsulation process is transfer moulding due to
its capability to mould small parts with complex features. An
electronic package that employs transfer moulding is Stacked-
Chip Scale Package (S-CSP). However, a computer simulation is
one of the tools that could be used to simulate and predict the
mould process. It is highly desirable in order to avoid the typical
time-consuming procedure of mould design and process
optimization by trial and error. In this paper, a fully three-
dimensional (3-D) analysis to predict transfer moulding process
of S-CSP encapsulation using finite volume method (FVM) based
software, FLUENT is presented. The proposed FVM simulation
model is built and meshed using GAMBIT. Some simplification is
done for the simulation model due to time consumption and
complicated geometry of actual S-CSP model. In the analysis,
volume of fluid (VOF) technique was used to track the flow front
of the encapsulant. The viscosity versus shear rate is plotted and
void formation problem also discussed. The numerical results are
compared with the previous experimental results and found good
KEY WORDS: Stacked-Chip Scale Package (S-CSP); Finite
volume method (FVM), Volume of Fluid (VOF), Front tracking,
Electronic packaging is defined as a package to house a
silicon chip in an electronic system. The main functions of an
electronic package are to protect the electronic components
from adverse environmental and mechanical effects and to act
as a structural support and electrical insulation [1]. It also
provides heat dissipation, signal timing and power distribution
[2]. In electronic packaging, one of the key processes is
encapsulation. Generally, transfer moulding and liquid
encapsulation are the most common encapsulation techniques.
In transfer moulding, epoxy moulding compound (EMC) is
preheated before loading into transfer port. By applying
certain pressure, the heated molten moulding compound is
transferred from the transfer port through the runners and then
into the mould cavities which may consist of a single or many
dies [3].
An example of electronic package using transfer moulding
process is Chip Scale Package (CSP) which is a package
whose area is less than 1.2 times the area of the IC. CSP has
smaller, thinner and lighter characteristics and has been
developed to address the demands of modern electronics. The
pace of CSP technology development is accelerating rapidly.
The semiconductor industry is driven by the broad adoption of
CSP in wireless handsets and handheld electronic devices.
Looking into the modern life today, the market demand for
thin, small, light and user friendly electronic packaging that
can provide wider variety of functions is still on the increase
in recent years [4-6]. The Stacked-Chip Scale Packages (S-
CSP) can be a best option to meet the aforesaid demands to a
remarkable extend. It integrates Application Specific
Integrated Circuit (ASIC) and memories such as flash, Static
Random Access Memory (SRAM), and Double Data Rate
(DDR) into one package by stacking dies, interconnecting
them with wire bonding and moulding all into one package
based on Joint Electronic Device Engineering Council
(JEDEC) standard [7-8]. S-CSP is adopted widely in portable
multi media devices such as cellular telephones, digital
cameras, PDAs and audio players [9].
There are several factors that can affect the mould filling
yields, such as die thickness (gap clearance), size and array
arrangement of complicated stacking dies. They are defined
as critical factors at initial stage of product quality planning
[10]. As the S-SCP mould is the matrix array type with thin
space and wide filling area, the quality concern of filling
process become very significant. It involves complex non-
Newtonian fluid flow, coupling heat transfer and chemical
reaction. As a result, the problems like incomplete mould,
void formation, unbalanced flow and wire sweeping are
common. Moreover, these phenomena in the complex mould
geometry make it difficult to analyze the process and further
optimize the design [11].
Although transfer moulding is a mature technology, it is still
difficult to optimize and the mould design is a costly and
lengthy process. Prototype often requires numerous
modification and revision. To minimize the impact of these
problems and for better mould design and optimization,
numerical flow analysis during the encapsulation process is
needed [12]. Turng and Wang [13], Han and Wang [14], and
Nguyen et al [15-18] are the pioneers in numerical simulation
of the flow during encapsulation. Their numerical formulation
was mostly based on finite element method (FEM) coupled
with the volume of fluid (VOF) technique. Generalized Hele-
Shaw approximation was made for the fluid field. Basically,
the Hele-Shaw cell consists of two flat plates that are parallel
to each other and separated by a small distance. The Hele-
Shaw approximation uses gapwise-averaged mass and
momentum-conservation equations ignoring the gapwise
component of the flow. Moreover, the thickness of the model
is relatively small as compared to its width and length, and
viscous effect dominates the flow. Thus, the inertia effect is
negligible [19]. Abdullah et al. [20-21] presented flow
visualization and EMC rheology on S-CSP encapsulation
studies using finite difference method.
An alternative FVM-based three dimensional (3-D) mould
filling analysis using incompressible Navier-Stokes equation
is introduced in the current study. The epoxy moulding
compound (EMC) is modelled as a non-Newtonian fluid and
the EMC is treated as a generalized Newtonian fluid (GNF).
Accordingly, in our previous work [22], 3D simulation of
pressurized under-filling of flip chip package has been
presented. The simulations were done on the computational
fluid dynamic code FLUENT 6.3. The volume of fluid (VOF)
technique is used to track the flow front during calculation. In
the present study, we adopt the technique to investigate the
flow visualization and encapsulant filling in microchip
encapsulation process. Numerical results of flow front profiles
are compared with previous experimental results. In
additional, void formation are observed for the studies.
The three-dimensional incompressible flow namely
conservation of mass, Navier-Stokes equation and
conservation of energy for non-isothermal, generalized
Newtonian fluids (GNF) are given below:
i. Continuity equation:
u (1)
ii. Navier-Stokes Equation:
iii. Energy equation:
However, a modification in the conservation of energy has
been made by inserting energy source term. The energy
source term is as follows:
For predicting the relationship between viscosity and the
degree of polymerization that are given accordingly as:
The Cross rheology model:
 
,0 (7)
BT b
n is the power law index, 0
the zero shear rate viscosity,
is the parameter that describes the transition region
between zero shear rates and the power law region of the
viscosity curve,
is the shear rate, B is an exponential-fitted
constant and Tb is a temperature fitted-constant, and T is the
absolute temperature.
In a three-dimensional filling simulation, accurate tracking
of the melt fronts as well as the representation and evolution
of the complex topology are very important. In the VOF
method the melt front can be tracked by solving the transport
equation of the fractional volume function. The transport
equation can be solved by either in the geometrical approach
or the algebraic approach. The VOF equation is given as:
dF (9)
where F is defined either it is equal to one (F = 1) for fluid
region or equal to zero
(F = 0) for empty region and partially full if F has value in
between one and zero at the melt front (0<F<1).
The volume of fluid (VOF) model in FLUENT 6.3.26 is
utilized to simulate the
S-CSP mold filling process. In the VOF model, a single set of
momentum equations is shared by the fluids, and the volume
fraction of each of the fluids in each computational cell is
tracked throughout the domain. Air and encapsulant material
Hitachi CEL-9200 XU (LF) [23] are defined as the phases in
the analysis and the mould temperature is set as 175oC.
Implicit solution and time dependent formulation are applied
for the volume fraction in every time step. The volume
fraction of the encapsulant material is defined as one and zero
value for air phase. Besides, viscosity cross model and VOF
techniques are applied to track the melt front. The model is
created by using GAMBIT software and total 94196
tetrahedral elements are generated for simulation. The
simulation took about seven hours to complete for a single
case. The S-CSP package model used in the present study and
its simplified model and the meshed model are shown in Fig. 1
and 2 respectively. Some simplifications have been made to
actual model such as replacement of chamfered corners by 90o
corners and removal of vents for simulation model. The
material properties [23] for the current study are summarized
in Table 1. The boundary and initial conditions are used in the
calculation are as follows:
a) On mould wall: 0
wvu ; w
TT ; 0
b) On melt front: 0
c) On inlet:
tzyxpp in ,,,; in
Table 1 Material Properties [23]
Parameter Value
n 0.7938
B 5.558E-4
a) Actual model b) Simplified model
Fig. 1. The actual and simplified S-CSP models.
Fig. 2. 3D meshed model
The experiments have been done to investigate the flow
behaviour of epoxy moulding compound (EMC) inside the
actual mould of Stacked-Chip Scale Package (S-CSP) with
twelve arrays of six stacking dies. The EMC used in this
investigation is HITACHI CEL-9200-XU (LF). The mould
temperature is set at 175oC and the package pressure is 70
kg/cm2. Short-shot results have been performed to observe the
melt front advancement at different times step. The short-shot
samples can be obtained by setting certain stroke length of the
plunger. The package will be incomplete if the sets less stroke
length. Thus the front profile can be attained. Fig. 3 illustrates
the gate, air vents, stacking dies in matrix array of 4 × 3 and
the flow direction.
Fig. 4 demonstrates respectively the experiment and
simulation (short shot) results of melt front advancement with
inlet velocity of 4 mm/s in the S-CSP. Hitachi CEL-9200-XU
(LF) is used as an encapsulant in the simulation. The
encapsulation process shows the good agreement of flow front
profile at 1.5s and 2s for experimental and simulation result.
The mould compound flows around the dies and moves
quickly before it starts to cover the dies. However, the flow
above the dies covers more area in experiments compared to
that of simulation. The effect of dies on the flow fronts is
clearly visible. It restricted the flow along the edges and over
the dies. As a result, the flow around the dies is accelerated.
Fig. 3. Schematic of flow in the cavity
Experiment Simulation Experiment Simulation
1.5 s 2.0 s
2.5 s 3.0 s
Free passage flow
Backside flow
Top die flow
3.5 s 4.0 s
5.0 s 6.0s
Fig. 4. Short shot results of melt front advancement at distinct time steps with velocity inlet of 4 mm/s
However, at 2.5s the simulation flow front profile is found
more slowly in filling compared to experiments. This
phenomenon is caused by the simplification of the simulation
model. The simplification on the stacked chip may be a factor
for affecting the encapsulant during the process. The
simplified chips act as a larger obstruction to the flow and
caused the encapsulant to fill the free region. At 6s of filling
stage, void is found in the mold filling process. Fig. 5 shows
the void formation of S-CSP filling process.
Fig. 5. Void formation at circled region.
Fig.6 shows viscosity variation versus shear rate. The curves
show as a power law viscosity variation where the viscosity
reduces with the shear rate.
Fig. 6. Viscosity versus Shear rate
A three-dimensional non-isothermal incompressible analysis
model based on finite difference method (FVM) for the
transfer moulding is presented and compared with the
experimental results. The three dimensional S-CSP package is
simulated to study the flow visualization in the process. The
encapsulant material used is Hitachi Chemical CEL-9200-XU
(LF). Cross-viscosity model and volume of fluid (VOF)
technique are used to track the flow front in the numerical
simulation. Navier-Stokes equations are solved by finite
volume method and SIMPLE segregated algorithm. It is found
that simulation results of melt fronts are in good agreement
with the experimental results, thus proving the strength of the
model and the fluent software in handling stacked chip
encapsulant problems. The present study may be extended
further for more actual type of stacked chip and different
parameter on different S-CSP packages.
[1] Rao R. Tummala, Fundamentals of Microsystems
Packaging, McGraw Hill, Singapore, 2001, pp. 44-79.
[2] Manzione LT. Plastic Packaging of Microelectronic
Device. Van Nostrand Reinhold: New York, 1990; pp.
[3] Rong-Yeu Chang, Wen-Sheng Yang, Eugen Chen, Chris
Lin and Chia-Hsiang Hsu. (1998). “On the Dynamic of
Air Trap in the Encapsulation Process of Microelectronis
Package”, in Proc. ANTEC’ 98 Conf., 1998.
[4] C.W. Liang, Vanktesh M. Kulakarni, P.A. Aswatha
Narayana, and K.N. Seetharamu, “Parametric Studies in
Transfer Molding for Newtonian Fluids”, Journal of
Physical Science, Vol. 16(2), 103-114, 2005.
[5] Venkatesh M. Kulkarni, K. N. Seetharamu, Ishak Abdul
Azid, P. A. Aswatha Narayana and Ghilam Abdul Quadir,
“Numerical Simulation of Underfill Encapsulation
Process Based on Charecteristic Split Method”, Int. J.
Numer. Meth. Engng 2006; 66:1658-1671.
[6] Chein Chang Pei and Sheng Jye Hwang, “Three-
Dimensional Paddle Shift Modelling for IC Packaging”,
Transactions of the ASME, Journal of Electronic
Packaging, 324-334 / Vol. 127, September 2005.
[7] Zhou, T. and Dreiza, M. (2004). “Stacked die package
design guidelines”, Proc IMAPS Conference, November
17, 2004.
[8] Yasuki Fukui, Yuji Yano, Hiroyuki Juso, Yuji Matsune,
Koji Miyata, Atsuya Narai, Yoshiki Sota, Yoshikazu
Takeda, Kazuya Fujita and Morihiro Kada, (2000),
Triple-Chip Stacked CSP”, IEEE 2000 International
Electronic Components and Technology Conference. 0-
[9] Morihiro Kada and Lee Smith. (2000), “Advancements in
Stacked Chip Scale Packaging (S-CSP) Provides System-
in-a-Package Functionality for Wireless and Handheld
Applications”. Future Fab. Intl. Volume 9.
[10] Sze, M.W.H. and Papageorge, M. (1998), “Encapsulation
selection, characterization and reliability for fine pitch
BGA (fpBGA)”. 4th Annual Flip Chip, BGA, Chip Scale
Packaging ’98, April 28-29, 1998. pp. 1-7.
[11] Min Woo Lee, Jin Young Kim, Min Yoo, JiYoung Chung
and Choon Hueng Lee, (2006), “Rheological
Characterization and Full 3D Mold Flow Simulation in
Multi-Die Stack CSP of Chip Array Packaging”,
Electronic Components And Technology Conference, 1-
[12] Nguyen, L., Quentin, C., Lee, W., Bayyuk, S., Bidstrup-
Allen, S. A. and Wang, S.T. (2000) “Computational
modeling and validation of the encapsulation of plastic
packages by transfer molding”. Transactions of the
ASME, Journal of Electronic Packaging, 138-146 / Vol.
122, June 2000.
[13] Turng, L. S. and Wang, V. W. (1993) “On the simulation
of microelectronic encapsulation with epoxy molding
compound”. Journal of Reinforced Plastics Composites,
12, pp. 506-519.
[14] Han, S. and Wang, K. K. (1995) Flow Analysis in a cavity
with leadframe during semiconductor chip encapsulation.
Advance in Electronic Packaging, ASME EEP-Vol. 10-1.
[15] Nguyen, L. T. (1993) Reactive flow simulation in transfer
molding of IC packages. 0569-5503/93/0000-0375 IEEE.
[16] Nguyen, L. (1994) Flow simulation in IC chip
encapsulation. Electronic Components and Technology
Conference, Buena Vista.
[17] Nguyen, L., Jackson, J., Teo, C. H., Chillara, S.,
Asanasavest, C., Burke, T., Walberg, R., Lo, R., Weiler,
P., Ho, D. and Rauhut, H. (1997) Wire sweep control with
mold compound formulation. 47th Electron. Comp. &
Tech. Conf., p.60-71.
[18] Nguyen, L., Quentin, C. G. and Lee, W. W., (1999) Flow
modeling and visualization of the transfer molding of
plastic ball grid array packages. 1999 Electronic
Components and Technology Conference, Santa Clara.
[19] Kim, S.W. and Turng, L.S. (2004) Developments of
three-dimensional computer-aided engineering simulation
for injection molding. Institute of Physics Publishing,
Modelling Simul. Mater. Sci. Eng. 12(2004) S151-S173.
[20] M. Khalil Abdullah, M. Z. Abdullah, S. Kamarudin, and
Z. M. Ariff, Study of flow visualization in stacked-chip
scale packages (S-CSP), International Communications in
Heat and Mass Transfer 34 (2007) 820-828.
[21] M. Khalil Abdullah, M. Z. Abdullah, M. A. Mujeebu, and
S. Kamaruddin, A study of effect of expoxy molding
compound (EMC) rheology during encapsulation on
stacked-CHIP scale packages (S-CSP), Journal of
Reinforced Plastics and Composites, Vol. 00, No.
[22] C.Y. Khor, M. A. Mujeebu, M. Z. Abdullah, F. Che Ani,
Finite Volume Based CFD Simulation of Pressurized Flip
Chip Underfill Encapsulation Process, Microelectronics
Reliability (PDF proof returned,
[23] Modeling multiphase flow, FLUENT Documentation,
Chapter 23.
ResearchGate has not been able to resolve any citations for this publication.
Microelectronic devices, such as transistors, capacitors, and resistors, within an active chip, require some protection from the environment, as well as both electrical and mechanical connections to the surrounding components. Electronic packaging is the science of placing electronic devices and circuitry in protective enclosures and providing interconnections within and between different electronic devices. Electronic devices have been packaged in a variety of ways. One of the first methods was a kovar (high nickel alloy) preformed package. The device was bonded to the bottom, and the top was later secured. Ceramic packages, similar in construction to the Kovar casing, later appeared as a cheaper alternative. The first evidence of plastic encapsulation was seen in the early 1950s, using compression molding of phenolics. The phenolic material was compressed around electrical devices leaving the electrical connectors sticking out. The problem with this method was that the delicate connections were often severed due to the high pressure. By the early 1960s, plastic encapsulation emerged as an inexpensive, simple alternative to ceramics and metal encasing and during the 1970s virtually all high-volume integrated circuits (ICs) were encapsulated in plastic. As of 2015, plastic encapsulation is used in most devices in both consumer electronics as well as high reliability applications. A plastic-encapsulated microcircuit (PEM), often called a plastic package, consists of an integrated circuit chip physically attached to a leadframe, and/or signal traces on the substrate, forming an electrical connection to the I/O leads or interconnects, and encapsulated, forming a direct contact with the chip, leadframe, and interconnects. PEMs are made in either surface-mount or through-hole configurations.
The stacked-Chip Scale Package (S-CSP) is a new technology that provides high density of the package. It enables to stack the die in a single package. The S-CSP is widely adopted in portable multi-media products. However, the resin flow through a thin surface and wide filling area is of concern. Therefore, this paper presents a study of flow visualization during encapsulation process in S-CSP. The Navier–Stokes equation has been solved by the finite different method. For non-linear terms, the Kawamura and Kuwahara technique has been adopted in the flow analysis. Pseudo-concentration based on the volume of fluid (VOF) technique was used to track a melt fronts for each time step. The numerical model has been verified by comparing the prediction with the experimental results. The numerical results show good agreement with the experimental results. The prediction also shows that the short shot problem that occurred for the die top clearance is lower than 0.25 mm.
This paper presents the stacked die CSP design guidelines for optimized yield and performance at lowest cost. Stacked die CSP has the advantage of higher packaging density and better performance. For a given stacked die package, there are multiple options to configure the package. Early design optimization helps to avoid manufacturing problems down stream and maximize the produce performance with lowest cost. Wire bond design approaches to avoid the yield loss due to wire short are achieved by reducing the wire length and properly manage the wire crossing. Risk of capillary interference can be avoided by optimizing the wire loop and bonding sequence. Guidelines for optimized electrical performance are given. Design for cost discussion is centered on the substrate cost. Die and substrate design methodologies are presented to achieve lower substrate cost. Introduction The electronics industry trend is to offer products that are smaller, with more functionality, better performance and lower cost. A stacked die chip scale package (SCSP) stacks multiple dice vertically in the same package. It effectively increases the device functionality within same footprint as a single die product. There have been many innovations in stacked die design, process and materials. Zhang and Tee [1] analyzed strip warpage of a stacked die BGA during package assembly processes. For a given stacked die concept, there are multiple options to configure the package. Upfront design optimization helps to avoid manufacturing problems down stream and maximize the produce performance with lowest cost. The intention of this study is to present design guidelines to optimize the SCSP. There are many types of electrical carriers. This paper will only focus on laminate based and wire bonded CSP with >200 I/O, typically used in handheld device applications. In the following sections design for yield, performance and cost is presented. Conclusions are made at the end. Design for Yield For a package that involves mixed technology die stacking (such as ASIC + memory), the challenge is often high bond wire density. Correctly designing the bond wire connections is critical to avoid later manufacturing yield and quality problems. This session gives guidelines for wire bond design to avoid risk of wire short due to wire sweeping which results in yield loss. There two focuses: minimizing the wire sweeping and increasing space between adjacent wires.
An effort has been made to more accurately analyze the flow in the chip cavity, particularly to model the flow through the openings in the leadframe and correctly treat the thermal boundary condition at the leadframe. The theoretical analysis of the flow has been done by using the Hele- Shaw approximation in each cavity separated by a leadframe. The cross-flow through the openings in the leadframe has been incorporated into the Hele-Shaw formulation as a mass source term. The temperature of the leadframe has been calculated based on energy balance in the leadframe. The flow behavior in the leadframe has been verified experimentally. In the experiment, a transparent mold and clear fluid have been used for flow visualization. Comparisons were made between the calculation and experimental results which showed a good agreement.
Transfer molding is the primary process method for microelectronic encap sulation with epoxy molding compound (EMC). Traditionally, the selection of the EMC as well as the tool and process design for microelectronic encapsulation are usually determined based on experience and intuition, which are costly and time-consuming. This article presents the numerical simulation for microelectronic encapsulation, which is aimed at providing designers useful information to detect various molding problems in an efficient and cost-effective way. In addition, it also discusses the material and geometry modeling which are critical to the accuracy of the simulation. As an illustration, a case study for a 40-lead dual-in-line (DIL) IC packaging is presented with comparison between the predic tions and experimental measurements from the literature. Finally, this article concludes with an overview of the future direction in this research.
In this paper, methods to analyze the flow during semiconductor chip encapsulation have been developed. A numerical method in used for the flow analysis in the chip cavity. In this study, for accurate analysis of flow in the chip cavity, models for the cross flow through the leadframe openings have been developed. The models have been verified by comparing with two experiments. In the first experiment, clear polymer and transparent mold have been used for the visualization of flow in a cavity with a leadframe. In the next experiment, actual epoxy molding compound together with an industrial encapsulation process have been used to observe the melt-front advancement shapes. The calculated and experimental results show good agreement.
The plastic packaging process for integrated circuits is subject to several fabrication defects. For packages containing leadframes, three major defects may occur in the molding process alone, namely, incomplete filling and void formation, wire sweep, and paddle shift. Paddle shift is the deflection of the leadframe pad and die. Excessive paddle shift reduces the encapsulation protection for the components and may result in failures due to excessive wire sweep. Computer-aided analysis is one of the tools that could be used to simulate and predict the occurrence of such molding-process-induced defects, even prior to the commencement of mass production of a component. This paper presents a methodology for computational modeling and prediction of paddle shift during the molding process. The methodology is based on modeling the flow of the polymer melt around the leadframe and paddle during the filling process, and extracting the pressure loading induced by the flow on the paddle. The pressure loading at different times during the filling process is then supplied to a three-dimensional, static, structural analysis module to determine the corresponding paddle deflections at those times. The paper outlines the procedures used to define the relevant geometries and to generate the meshes in the "fluid" and "structural" subdomains, and to ensure the compatibility of these meshes for the transfer of pressure loadings. Results are shown for a full paddle shift simulation. The effect on the overall model performance of different element types for the mold-filling analysis and the structural analysis is also investigated and discussed. In order to obtain more accurate results and in a shorter computational time for the combined (fluid and structural) paddle shift analysis, it was found that higher-order elements, such as hexahedra or prisms, are more suitable than tetrahedra.
This paper presents, discusses, and compares results from experimental and computational studies of the plastic encapsulation process for a 144-lead TQFP package. The experimental results were obtained using an instrumented molding press, while the computational predictions were obtained using a newly-developed software for modeling transfer molding processes. Validation of the software is emphasized, and this was done mainly by comparing the computational results with the corresponding experimental measurements for pressure, temperature, and flow front advancement in the cavities and runners. The experimental and computational results were found to be in good agreement, especially for the flow-front shapes and locations.
This paper presents the state-of-the-art technology and developments of three-dimensional computer-aided engineering (CAE) simulation for injection moulding. It is aimed at providing insights into the emerging three-dimensional CAE tools to facilitate judicious application and further developments of these tools for design and manufacturing of complex injection moulded parts. It begins with background information on the evolution of CAE for injection moulding, followed by a discussion of advantages and limitations inherent with the widely adopted 2.5-dimensional Hele–Shaw flow approximation. After that, the mathematical formulations and numerical methods used in three-dimensional simulation are presented. This paper also discusses some special issues related to three-dimensional simulation, such as intensive CPU requirement and solution resolution in the gap-wise direction. A number of illustrative examples are presented to demonstrate the capabilities of three-dimensional simulation and the difference between predictions from the 2.5-dimensional and three-dimensional analyses.
Electronic packaging protects the integrated circuit chip from environmental and mechanical damages. Underfilling encapsulation is an electronic packaging technology used to reinforce the solder joints between chip and the substrate. For better mould design and optimization of the process, flow analysis during the encapsulation process is the first necessary step. This paper focuses on the study of fluid flow in underfilling encapsulation process as used in electronics industry. A two-dimensional numerical model was developed to simulate the mould filling behaviour in underfilling encapsulation process. The analysis was carried out by writing down the conservation equations for mass, momentum and energy for a two-dimensional flow in an underfilling area. The governing equations are solved using characteristic based split (CBS) method in conjunction with finite element method to get the velocity and pressure fields. The velocity field was used in pseudo-concentration approach to track the flow front. Pseudo-concentration is based on the volume of fluid (VOF) technique and was used to track fluid front for each time step. A particular value of the pseudo-concentration variable was chosen to represent the free fluid surface which demarcates mould compound region and air region. Simulation has been carried out for a particular geometry of a flip-chip package. The results obtained are in good agreement with the available numerical and experimental values and thus demonstrate the application of the present numerical model for practical underfilling encapsulation simulations. Copyright