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Power Blurring (PB) methods enable calculation of IC temperature profiles from the power dissipation map with calculation speeds hundreds of times faster than finite element methods (FEM). Both static [1,2] and transient distributions can be obtained [3]. Extensions to 3D chips [4] and to the inverse problem, i.e. estimating the power map from the temperature field [5], are available. So far however, the temperature dependence of the material parameters has been neglected. Temperature rises of 40-50°C on the chip will reduce the thermal conductivity of the silicon by 10-20%. This could affect the hot spot temperature by 5-7°C. In this work, we extend the PB approach to account for this effect. We propose two Adaptive Power Blurring (APB) methods based on iterative procedures. In both methods, the PB method provides an initial temperature distribution guess using room temperature Si thermal conductivity. Subsequent iterations take into account the preliminary temperature profile in the chip. The key difference between the two APB methods is the way the thermal masks are selected from a look-up table. The first variant uses one single mask based on the average temperature increase in the silicon, while the second approach employs a different mask for each point to account for the spatial variation of the temperature and according non-uniform thermal conductivity. In either case, the new estimate of temperature profile is acquired from convolution of the thermal masks and the IC Power map. These schemes are then applied iteratively until a final, self-consistent solution is reached. Good convergence is achieved only in 2-3 iterations in both methods. We will demonstrate that these APB methods substantially improve the accuracy under high temperature rise regime, in particular at hot spots, while still being much faster than traditional FEM computations.

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... The PB technique is based on the superposition principle, which requires linearity of the heat conduction equation. An adaptive PB technique is developed in [26], which can solve nonlinear problems, e.g., when the thermal conductivity of the silicon is modified based on the local temperature of the chip, using two or three iterations. Excellent agreements with self-consistent finite-element simulations have been obtained. ...

... Three orders of magnitude improvement in runtime as well as six orders of magnitude speedup are obtained by their PB method in comparison with solving the thermal network of the chip directly. Acquiring temperature profiles of power electronic transistor arrays [25], solving nonlinear problems (calculating temperature profiles in ICs considering temperature dependence of material properties of the chip) using only two or three iterations [26], and solving the inverse problem (i.e., obtaining heat dissipated in ICs from their temperature profiles) [27] are some other examples, which are illustrative of versatility of the PB technique. ...

High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced
computation time.

... According to the work presented in [SASD10], the phase-shift, given in degrees, generated by heat diffusion can be expressed as follows: In [ZBS19], it is shown that the thermal conductivity varies less than 3% on the [289, 297] K temperature range, a quite large span when considering temperature drifts in a test room. Similarly, in [GP01], the specific heat variation does not excess 2% on the same temperature range. ...

The generalization of integrated circuits and more generally electronics to everyday life systems (military, finance, health, etc) rises the question about their security. Today, the integrity of such circuits relies on a large panel of known attacks for which countermeasures have been developed. Hence, the search of new vulnerabilities represents one of the largest contribution to hardware security. The always rising complexity of dies leads to larger silicon surfaces.Circuit imaging is therefore a popular step among the hardware security community in order to identify regions of interest within the die. In this objective, the work presented here proposes new methodologies for infrared circuit imaging. In particular, it is demonstrated that statistical measurement analysis can be performed for automated localization of active areas in an integrated circuit.Also, a new methodology allowing efficient statistical infrared image comparison is proposed. Finally, all results are acquired using a cost efficient infrared measurement platform that allows the investigation of weak electrical source, detecting power consumption as low as 200 µW.

... Electrical power simulation was performed using the R3D [9] method. Temperature change simulation based on the simulated power distribution was performed using the power blurring method [10], [11]. ...

Thermoreflectance imaging with high spatial resolution is used to inspect self-heating distribution in active high power (4A) metal-oxide-semiconductor field-effect transistor transistor arrays designed for high-frequency (MHz) operation. Peak temperature change and self-heating distribution is analyzed for both low- and high-dc bias cases and for different ambient die temperatures (296–373 K). Thermoreflectance images reveal temperature nonuniformity greater than a factor of two over the full area of the transistor arrays. Thermal nonuniformity is revealed to be strongly dependent on both bias level and ambient die temperature. Verification based on the fine grain power dissipation in the transistor array was performed using the R3D method for electrical simulation and power blurring for thermal simulation. Results demonstrate thermoreflectance imaging as an effective tool for fast submicrometer noncontact thermal characterization of active power devices.

To sustain Moore’s law, three-dimensional integrated circuit (3-D IC) is a promising solution to achieve high performance and low cost targets. However, its operating temperature is higher than that of a 2-D IC because of its high power density of stacked dies and ill of heat dissipation capability. Therefore, on-chip thermal effects have become major concerns of 3-D ICs. Utilizing look-up table approach, this paper, LUTSim, provides two thermal simulation engines, I-LUTSim and S-LUTSim, to efficiently calculate the thermal profile of a 3-D IC. I-LUTSim is suitable for full-chip thermal analysis, and S-LUTSim is suited for incremental-thermal updating. With utilizing the prebuilt tables, compared with a commercial tool ANSYS, the absolute error of I-LUTSim is less than 0.29%. Moreover, with negligible loss of accuracy, I-LUTSim can be 38.8 times faster than a well-known matrix solver SuperLU for performing full-chip thermal simulation. Besides, S-LUTSim can be over 1.05 million times faster than SuperLU for adjusting the thermal profile after inserting/removing a through silicon via.

High temperatures and non-uniform temperature distributions have become a serious concern since they limit both performance and reliability of Integrated Circuits (IC). With computer architect's concern to position microarchitecture blocks in a processor, faster thermal models can be developed at the cost of hiding finer grain details such as circuit or transistor level information. Several methods to quickly estimate the surface temperature profiles of microarchitecture blocks have been investigated in recent years. HotSpot simulator is widely used in computer architecture community. SESCTherm is another architecture level thermal simulator which has shown good performance and modularity in modeling. Recently Power Blurring (PB) method has been developed for both steady-state and transient thermal analysis of standard and 3D chips. While some of these methods are validated against finite element and Green's function based techniques, there are no detailed comparisons of the accuracy and speed for some common applications. In this paper we present the steady-state and transient temperature distributions calculated by these three architecture level thermal simulators. A detailed comparison taking into account the accuracy and the computation speed is performed. Our results indicate that Power Blurring has the potential to be a promising architecture level thermal simulator for fast calculation of temperature profile from the input power map in a realistic package which, in turn, is a key ingredient for full self-consistent simulations.

With temperature being one of the main limiting factors in design of high performance processors, early evaluation of thermal effects in design stages is becoming a necessity. Floorplanning is an imperative step in the design process where thermal effects can be taken into account. This work studies a thermal-aware floorplanning scheme, with the goal of increasing both reliability and performance measures of the design. We show that a majority of thermal emergencies can be averted by a) leveraging the lateral heat transfer effects (as has been shown previously), and b) by reducing the power density of thermally critical blocks. The former becomes possible through moving, and modifying the aspect-ratio of the blocks in the floorplanning process. The latter, one of the key contributions of this work, is carried out through resizing of functional blocks in a controlled way. We also propose a selective power map generation method for the floorplanning process. In this method the time windows in which thermal emergencies occur guide the power map generation. As a result, we observed an 8.8% performance improvement, and a 40% reliability increase with the area overhead of just 3%.

The degraded thermal path of 3-D integrated circuits (3DICs) makes thermal analysis at the chip-scale an essential part of the design process. Performing an appropriate thermal analysis on such circuits requires a model with junction-level fidelity; however, the computational burden imposed by such a model is tremendous. In this paper, we present enhancements to two thermal modeling techniques for integrated circuits to make them applicable to 3DICs. First, we present a resistive mesh-based approach that improves on the fidelity of prior approaches by constructing a thermal model of the full structure of 3DICs, including the interconnect. Second, we introduce a method for dividing the thermal response caused by a heat load into a high fidelity “near response” and a lower fidelity “far response” in order to implement Power Blurring high definition (HD), a hierarchical thermal simulation approach based on Power Blurring that incorporates the resistive mesh-based models and allows for junction-level accuracy at the full-chip scale. The Power Blurring HD technique yields approximately three orders of magnitude of improvement in memory usage and up to six orders of magnitude of improvement in runtime for a three-tier synthetic aperture radar circuit, as compared to using a full-chip junction-scale resistive mesh-based model. Finally, measurement results are presented showing that Power Blurring high definition (HD) accurately determines the shape of the thermal profile of the 3DIC surface after a correction factor is added to adjust for a discrepancy in the absolute temperature values.

Due to the aggressive scaling down of the CMOS technology, VLSI ICs become more and more vulnerable to the effect of non-uniform high temperatures which can significantly degrade chip performance and reliability. Therefore, we are interested in surface temperature profiles of VLSI ICs. In IC thermal analysis, heat conduction equation is conventionally solved by grid-based methods which are computationally expensive. To reduce the com-putation time, we developed a matrix convolution technique, Power Blurring (PB). It calculates the steady-state temperature profile with maximum temperature errors less than 1% for various types of power distributions. It re-quires a spatial impulse response, called the thermal mask, which can be obtained by using Finite Element Analysis (FEA) tools such as ANSYS. The thermal mask is a function to be convoluted with power distribution for tempera-ture profile. Thus, the PB method uses FEA repeatedly for the changes in parameters of thermal packages such as thermal conductivity, convection heat transfer coefficient, and silicon substrate thickness to obtain new thermal mask. Our test structure is divided into 49,323 elements of which 1600 correspond to the surface of the silicon sub-strate. Performing FEA repeatedly is time consuming. In this paper, we will describe the PB method and propose a method for parameterization of the thermal mask to avoid many FEA simulations under parameter variations. The PB method using parameterized mask yields maximum error less than 2.3% for various case studies and reduces computation time from 17 seconds to 0.1 second for our test structure.

CMOS VLSI technology has been facing various technical challenges as the feature sizes scales down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ~ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.

Thermal Simulation, Thermal Modelling and Investigation of PackagesThermal aware routing and placement algorithms are important in industry. Currently, there are reasonably fast Green's function based algorithms that calculate the temperature distribution in a chip made from a stack of different materials. However, the layers are all assumed to have the same size, thus neglecting the important fact that the thermal mounts which are placed underneath the chip can be significantly larger than the chip itself. In an earlier publication, we showed that the image blurring technique can be used to calculate quickly temperature distribution in realistic packages. For this method to be effective, temperature distribution for several point heat sources at the center and at the corner and edges of the chip should be calculated using finite element analysis (FEA) or measured. In addition, more accurate results require correction by a weighting function that will need several FEA simulations. In this paper, we introduce the method of images that take the symmetry of the thermal boundary conditions into account. Thus with only "two" finite element simulations, the steady-state temperature distribution for an arbitrary complex power dissipation profile in a packaged chip can be calculated. Several simulation results are presented. It is shown that the power blurring technique together with the method of images can reproduce the temperature profile with an error less than 0.5%.

Recently VLSI IC design is concerned with the large temperature non-uniformity in high power chips. Thus far, thermal simulations have been limited to steady-state worst case conditions, which have caused the use of conservative margins in thermal designs. Transient temperature characteristics were not simulated in prior art chip-level simulations due to the high computational expense. To drastically reduce the time for the chip-level thermal simulations, we have developed a matrix convolution technique, called the Power Blurring (PB) method. Our method renders the temperature profile of a packaged IC with maximum error less than 3% for several case studies done and reduces the computation time by a factor of 100, compared to the simulations done by the industry standard finite element tools.

Thermal aware routing and placement algorithms are important in industry. Currently, there are reasonably fast Green's function based algorithms that calculate the temperature distribution in a chip made from a stack of different materials. However, the layers are all assumed to have the same size, thus neglecting the important fact that the thermal mounts which are placed underneath the chip can be significantly larger than the chip itself. In an earlier publication, we showed that the image blurring technique can be used to calculate quickly temperature distribution in realistic packages. For this method to be effective, temperature distribution for several point heat sources at the center and at the corner and edges of the chip should be calculated using finite element analysis (FEA) or measured. In addition, more accurate results require correction by a weighting function that will need several FEA simulations. In this paper, we introduce the convolution by images that take the symmetry of the thermal boundary conditions into account. Thus with only "two" finite element simulations, the steady-state temperature distribution for an arbitrary complex power dissipation profile in a packaged chip can be calculated. Several simulation results are presented. It is shown that the power blurring technique together with the method of images can reproduce the temperature profile with an error less than 0.5%.

In this paper, we present a method to efficiently identify the on-chip hot spots in ULSI circuits. A set of mathematical formulae were derived in analytical forms so that local temperature information can be fetched quickly. These formulae were based on the Green's function and error function approximation, and the resulting equations were further simplified to a tractable level by asserting different constraints. Experimental result shows that this method is able to accurately locate the hot spots with little time complexity. It is particularly useful for temperature-driven circuit macro placement in the early chip design phase, for which a large number of design iterations are needed and simulation efficiency is required

In this paper, we present a new technique to calculate the power dissipation profile from the IC temperature map using a process analogous to image processing and restoration. In this technique, finite-element analysis (FEA) is used to find the heat-point spread function (heat PSF) of the IC chip. Then, the temperature map is used as input for an efficient image restoration algorithm which locates the sources of strong power dissipation non-uniformities. Therefore, it optimally solves the inverse heat transfer problem, and estimates the IC power map without extensive lab experiments. Our computationally efficient and robust method, unlike some previous techniques, applies to many experimental scenarios. Simulation results on a typical commercial integrated circuit chip confirm the effectiveness of our proposed method.

The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI industry limiting both the performance and the reliability of packaged chips. Thus the surface temperature profile of VLSI ICs has become critical information in chip design flow. for fast computation of surface temperature profile, power blurring (PB) method has been developed. This method can be applied to simulations with high spatial resolution, which have been prohibitively expensive with conventional methods. Comparative case studies with different levels of resolution illustrate that not only localized small hot spots can be overlooked but even the average chip temperature can be underestimated, and hence the necessity of thermal simulation with high spatial resolution. Using our PB method, we obtained transistor level thermal map (5times5 mum<sup>2</sup> grid) of a 5times5 mm<sup>2</sup> chip with a computation time of 20 seconds.

Thermal simulation has become increasingly important in chip design, especially in the nanometer regime, where the on-chip hot spots severely degrade the performance and reliability of the circuit and increase the leakage power. In this paper, we present a highly efficient and accurate thermal simulation algorithm that is capable of performing full-chip temperature calculations at the cell level. The algorithm is a combination of several important numerical techniques including the Green function method, the discrete cosine transform (DCT), and the frequency domain computations. Experimental results show that our algorithm can achieve orders of magnitude speedup compared with previous Green function based algorithms while maintaining the same accuracy.

Fast Computation of Temperature Profile of VLSI ICs with High Spatial Resolution" Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 24)

- J H Park
- X Wang
- A Shakouri
- S M Kang

J.H. Park, X. Wang, A. Shakouri, S.M. Kang,
"Fast Computation of Temperature Profile of VLSI
ICs with High Spatial Resolution" Semiconductor
Thermal Measurement, Modeling, and Management
Symposium (Semi-Therm 24), pp. 50-55, 2008.