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On the Depth Profiling of the Traps in MOSFET's with High-k Gate Dielectrics
Abstract
A general and reliable model for charge pumping (CP) proposed recently has been extended to trap depth distributions towards oxides depth. The fundamental features concerning the energy and depth region probed at the Si-SiO2 interface and in the direction of oxides depth are presented in the case of the different basic CP curves. The effect of the electric field is accounted for and its impact on the results is discussed. Then, MOSFET's with HfO2 gate dielectric are studied. Trap depth concentration profiles recorded from devices after different technological processes are presented and discussed.
... It is known that La 2 O 3 has an ionic bonding nature while the bond in the La-silicate layer is more covalent, thus creating a larger amount of oxygen vacancies at the La 2 O 3 /Si interface [59]. It has been reported that charge-pumping measurement can be used to detect the interface traps between ionic HfO 2 and covalent SiO 2 , and so the traps located at the La 2 O 3 /La-silicate interface can be considered as slow states [60]. Figure 10c shows the density of this slow state (D slow ) together with D it calculated based on the measured conductance of the La 2 O 3 -gated MOS capacitor, with D slow much higher than D it and almost distributed uniformly in the Si band gap [58]. ...
... Figure 10c shows the density of this slow state (D slow ) together with D it calculated based on the measured conductance of the La 2 O 3 -gated MOS capacitor, with D slow much higher than D it and almost distributed uniformly in the Si band gap [58]. [60], (e) Si 1s spectrum at the La2O3/Si interface for different annealing temperatures [57], and (f) XRD patterns of La2O3 and LaON films after annealing [61]. ...
... It has been reported that doping La into other high-k materials can also achieve improvements, and the most important effect of La doping is to passivate the oxygen vacancies in other high-k binary oxides. After several reports showing that La incorporated in HfO2 could significantly improve the device performance [53][54][55][56][57][58][59][60][61][62][63][64][65][66], X. P. Wang et al. proposed that this improvement should be ascribed to the reduction of oxygen vacancies (VO) in HfLaO [66]. Therefore, several studies on the physics of this phenomenon have been made and confirmed the VO passivation [55,56], (c) band diagram showing the traps in a metal/La 2 O 3 /La-silicate/Si gate stack [58], (d) calculated D it and D slow in the band gap of Si with E i as the midgap of the Si substrate [60], (e) Si 1s spectrum at the La 2 O 3 /Si interface for different annealing temperatures [57], and (f) XRD patterns of La 2 O 3 and LaON films after annealing [61]. ...
This paper reviews the studies on La-based high-k dielectrics for metal-oxide-semiconductor (MOS) applications in recent years. According to the analyses of the physical and chemical characteristics of La2O3, its hygroscopicity and defects (oxygen vacancies, oxygen interstitials, interface states, and grain boundary states) are the main problems for high-performance devices. Reports show that post-deposition treatments (high temperature, laser), nitrogen incorporation and doping by other high-k material are capable of solving these problems. On the other hand, doping La into other high-k oxides can effectively passivate their oxygen vacancies and improve the threshold voltages of relevant MOS devices, thus improving the device performance. Investigations on MOS devices including non-volatile memory, MOS field-effect transistor, thin-film transistor, and novel devices (FinFET and nanowire-based transistor) suggest that La-based high-k dielectrics have high potential to fulfill the high-performance requirements in future MOS applications.
La-silicate/Si interface were investigated by measuring C-V characteristics and infra-red absorbance spectra. Interface state density (Dit) down to 1010 cm-2/eV was obtained by annealing at temperature over 800 °C. A red-shift due to Si-O-Si LO phonon toward 1250 cm-1 was found. We speculate that relaxation of SiO4 networks in La-silicates results in low Dit.
A novel interpretation for conductance spectra obtained by conductance method of La2O3 gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10 k to 200 kHz and the other near 1 kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (Dit) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (Dslow) at the interface between La2O3 and La-silicate. Finally, the Dit and Dslow trends on annealing temperature are summarized.
The defects in the SiO(2) interfacial layer (IL) in SiO(2)-HfO(2) gate stacks are studied using charge pumping (CP). To that aim, conventional CP curves and interface trap density vs. energy, D(it)(E), profiles measured on these devices are compared with those recorded from state of the art (S-A) MOSFETs. By doing so, specific features in the results recorded from the devices with HfO(2) are pointed out. Then, trap depth concentration, N(t)(x), profiles, recorded from the Si-SiO(2) interface towards HfO(2) are reported. With regard to S-A MOSFETs, these profiles provide evidence of 1) a strong increase in N(t) towards HfO(2), 2) an impact of HfO(2) on the trap properties up to the Si-SiO(2) interface, and 3), a large increase in the minimum Nt value. As the SiO(2)-HfO(2) interface is probed for the devices annealed at the lowest temperature, TA, the profiles show a continuous increase of N(t) from SiO(2) to HfO(2). Then, the impacts on the trap profiles of both TA, and the HfO(2) thickness deposited, d(HfO2), are dealt with. A higher TA yields SiO(2) re-growth. This 1) pushes the increase of Nt observed towards HfO(2) further away from the Si-SiO(2) interface but 2) yields also to a deeper penetration of this increase in the IL. The first effect dominates. Also, it seems that increasing d(HfO2) slightly increases the trap penetration into the IL. Finally, the two states of the P(b0) center are identified in the trap depth concentration profiles. Their characteristics differ from those in S-A MOSFETs. They are correlated for the first time in fresh and fully processed devices with the interface trap densities measured in both parts of the silicon bandgap. By adjusting the experimental conditions, the N(t)(x) profiles corresponding to the two P(b0) center levels can be drawn.
Charge pumping (CP) is the most widely used Si−SiO2 interface trap electrical characterization technique. However, several important characteristics and basic principles of this technique have not yet been rigorously defined. In this article, the onsets of nonsteady-state carrier emission and steady-state carrier capture, which occur during the transition edges of the gate signal when large gate pulses are used, are defined. The energies at the Si−SiO2 interface where these mechanisms start are calculated. Then, the case of asymmetrical or of small gate pulses, where capture of at least one carrier type cannot occur during the transition edges of the gate signal but proceeds during the following steady-state bias, is dealt with. The consequences of such a situation on the contribution of carrier emission to the CP current is studied. This allows a model which accurately describes the CP current in a large number of situations to be obtained. Using this model, it is shown that when the trap capture cross sections are small near the band edges, the energies where non-steady-state carrier emission takes place, interact with the high and/or low Fermi-level position. It is also shown that under asymmetrical biases, the energy regions in the upper and lower half of the band gap contributing to the CP current vary nearly symmetrically. This model is used for discussing the reliability of two-level CP for extracting interface trap concentration versus energy, Dit(E), profiles in metal–oxide–semiconductor devices. A comparison is carried out with the simplified extraction methods found in literature. The influence, on the Dit(E) profiles, of the trap cross sections and of the biases is discussed. The advantages of the spectroscopic CP are pointed out. © 2003 American Institute of Physics.
The reliability of a charge pumping (CP) technique proposed recently, which allows the extraction of the Si – Si O 2 interface trap concentration profiles in metal-oxide-semiconductor transistors, from fast to slow traps, is discussed. The shape of the trap concentration profiles measured, the values of the trap cross section extracted, and the integration of the trap profiles, which should give the interface trap density obtained using the conventional CP technique, are discussed with regard to the trap filling function variation and to surface-potential fluctuations. Then, the influence, on these profiles, of both carrier emission, which is neglected in the model used for calculating the profiles, and of the source and drain regions (S/D-R) of the devices, where the threshold and flatband voltages are different from those in the central region of the channel, is investigated. It is shown that carrier emission does not impact on the trap profiles and that the trap time constant distribution measured does not originate from the S/D-R of the devices. A way to detect a significant contribution of these regions to the charge pumping current measured is proposed. Finally, a comparison with noise spectroscopy is carried out. The results obtained using the two techniques agree very well.
Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (Dit). The charge pumped per cycle (Qcp) versus high level (Vh ) of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on Qcp as a function of frequency was successfully used to determine the depth profile of border-trap density near the high-kappa gate dielectric/Si interface. The influence of border trap in high-kappa dielectric on the Dit measurement can be prevented by an appropriate selection of gate frequency in CP technique