ArticlePDF Available

Abstract and Figures

A CMOS voltage controlled ring oscillator based on N-stage single-ended chain of different inverter types is described in this paper. The proposal is characterized by increased frequency stability (Δf = f < 2%) in term of power supply voltage variations in respect to Standard solutions (Δf = f > 4%). The presented results are obtained using HSpice simulation and CMOS library model, level 49, for 1.2 μm technology.
Content may be subject to copyright.
SCIENTIFIC PUBLICATIONS OF THE STATE UNIVERSITY OF NOVI PAZAR
SER . A: AP PL . MATH . IN FO RM .AN D MECH. vol. 2, 1 (2010), 1-9.
A CMOS Voltage Controlled Ring Oscillator with Improved
Frequency Stability
G. Jovanovi´
c, M. Stojˇ
cev, Z. Stamenkovic
Abstract: A CMOS voltage controlled ring oscillator based on N-stage single-ended chain of
different inverter types is described in this paper. The proposal is characterized by increased
frequency stability (f/f<2%) in term of power supply voltage variations in respect to stan-
dard solutions (f/f>4%). The presented results are obtained using HSpice simulation and
CMOS library model, level 49, for 1.2
µ
mtechnology.
Keywords: Voltage controlled oscillator, ring oscillator, CMOS, frequency stability.
1 Introduction
A voltage controlled oscillator (VCO) is one of the most important basic building blocks
in analog and digital circuits [1]-[6]. There are many different implementations of VCOs.
One of them is a ring oscillator based VCO, which is commonly used in the clock generation
subsystem. The main reason of ring oscillator popularity is a direct consequence of its
easy integration. Due to their integrated nature, ring oscillators have become an essential
building block in many digital and communication systems. They are used as voltage-
controlled oscillators (VCO’s) in applications such as clock recovery circuits for serial data
communications [1], [2], disk-drive read channels [3], on-chip clock distribution [4], and
integrated frequency synthesizers [5], [6]. The design of a ring oscillator involves many
tradeoffs in terms of speed, power, area, and application domain [13]. The problem of
designing a ring oscillator is in focus of our interest in this paper. This paper proposes a
suitable method for increasing frequency stability of a CMOS ring VCO.
The rest of the text is organized as follows. In Section 2, we give a brief review of volt-
age controlled ring oscillators, and define some crucial operating parameters. Hardware
description of the proposed ring oscillator is presented in Section 3. In addition we present
the simulation results which relate to frequency stability in terms of temperature and supply
Manuscript received January 27, 2010 ; revised April 17, 2010; accepted May 31, 2010.
G. Jovanovi´
c, M. Stojˇ
cev are with the University of Niˇ
s, Faculty of Electronic Engineering, Serbia; Z.
Stamenkovic is with the IHP GmbH,Innovations for High Performance Microelectronics Leibniz-Institut fuer
innovative Mikroelektronik, Im Technologiepark 25, 15236 Frankfurt (Oder) Germany
1
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 2
voltage variation. In Section 4, we define the terms of jitter and phase noise in ring oscilla-
tors, and present the appropriate simulation results. Finally, conclusion is given in Sections
5.
2 CMOS ring VCO - a review
A ring oscillator is comprised of a number of delay stages, with the output of the last stage
fed back to the input of the first. To achieve oscillation, the ring must provide a phase
shift of 2
π
and have unity voltage gain at the oscillation frequency. Each delay stage must
provide a phase shift of
π
/N, where Nis the number of delay stages. The remaining phase
shift is provided by a dc inversion [7]. This means that for an oscillator with single-ended
delay stages, an odd number of stages are necessary for the dc inversion. If differential
delay stages are used, the ring can have an even number of stages if the feedback lines are
swapped. Examples of these two circuits are shown in Fig. 1.
A1A2AN
A1A2AN
(a)
(b)
Fig. 1. Ring oscillator types: (a) single-ended and (b) differential
In order to determine a frequency of the ring oscillator we will use its linear model as
is given in Fig. 2.
-gm-gm-gm
R C CR R C
Fig. 2. . Linear model of ring oscillators
We assume that all inverting stages are identical and that they can be modeled as a trans-
conductance loaded by a parallel connection of resistor R and capacitor C. The gain of the
inverting stage is defined as
A1(j
ω
) = A2(j
ω
) = ...=AN(j
ω
) = gmR
1+j
ω
RC (1)
According to Barkhausen criteria the ring oscillator is operative when the following condi-
tions are satisfied
|A1(j
ω
)·A2(j
ω
)·. . . ·AN(j
ω
)|=1
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 3
A(j
ω
) =
θ
=arctan
ω
RC =2k
π
N(2)
The frequency of oscillation is given by
ω
0=tan
θ
RC (3)
and the minimal single stage gain is
gmR1
cos
θ
(4)
Alternatively we can derive an equation for the frequency of oscillation if we assume that
each stage provides a delay of td. The signal goes through each of the Ndelay stages once
to provide the first phase shift in a time of Ntd. Then, the signal must goes through each
stage a second time to obtain the remaining phase shift, resulting in a total period of 2Ntd.
Therefore, the frequency of oscillation is
f0=1
2Ntd
(5)
The difficulty in obtaining a value for the frequency arises when trying to determine td,
mainly due to the nonlinearities and parasitic of the circuit. As is referred in [7] the delay
per stage is defined as the change in output voltage at the midpoint of the transition, VSW ,
divided by the slew rate, Iss/C, resulting in a delay per stage of CVSW /Iss. Using definition
(5), the oscillation frequency is given by
f0=Iss
2NVswC(6)
3 Ring oscillator inverting stage
As we have already mentioned, the ring oscillators is realized with N inverter stages. There
are numerous types of inverter stages by which a ring oscillator can be realized [8], [9].
Some of the standard solutions are pictured in Fig. 3.
Designs given in Fig. 3 b), c), d) are of current starved type, for which the charging
and discharging output capacitor current is limited by a bias circuit. More details related to
realization of this type of inverter stage can be found in References [8], [9].
Relative frequency deviations in term of temperature variations for 3-stages ring os-
cillators based on type of inverters stages presented in Fig. 3 are given in Fig. 4. In
general all frequency deviations have similar behavior, but the basic type (Fig. 3 a)) and
current starved with symmetrical load (Fig. 3 d)) inverters have the highest, while cur-
rent starved with output-switching (Fig. 3 b)) inverter has the lowest sensitivity. The ratio
of relative frequency deviations between basic type (Fig. 3 a)) and current starved with
output-switching (Fig. 3 b)) inverters is 5:1.
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 4
Vdd
Vctrl
Vdd Vdd
bias
circuits
Vctrl
Vdd Vdd
bias
circuits
Vdd Vdd
bias
circuits
Vctrl
Vdd
(a)
(b)
(d)(c)
Fig. 3. Invertor: (a) basic type; (b) current starved with output-switching; (c) current starved with power-
switching; (d) current starved with symmetrical load.
Relative frequency deviations in term of power voltage supply variations for 3-stages
ring oscillators based on type of inverters stages presented in Fig. 3 are given in Fig. 5.
As can be seen from Fig 5, the basic type (Fig. 3(a)) and current starved with symmetrical
load (Fig. 3(d)) inverters have characteristics with negative slope, while current starved
with output-switching (Fig. 3 (b)) and current starved with power-switching (Fig. 3 (c))
inverters have characteristics with positive slope. Absolute value of inverters sensitivity
in function to power supply voltage variation is within a range of 10% excluding current
starved inverter with power-switching (Fig. 3 c)) inverters which has sensitivity of 5%.
Taking into consideration the opposite slope characteristics of the relative frequency de-
viations in terms of power voltage supply variations of the mentioned inverters (Fig. 5),
we can conclude that is reasonable to design a ring oscillator composed of cascade chain
of inverters. For example, odd numbered inverters can have positive, while even numbered
negative slope. In this way, the relative frequency deviation in term of power voltage supply
can be drastically reduced (more than 100%).
Several typical design solutions of 3-, 5- and 7- stages ring oscillators with reduced
sensitivity are given in Fig. 6 a), b) and c), respectively. We call them as combined ring
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 5
Fig. 4. Relative frequency deviation in term of temperature variation
Fig. 5. Relative frequency deviation in term of power supply voltage variation
oscillators. Let note that in combined ring oscillators the odd numbered inverter stages are
implemented with basic type, while even numbered as current starved with output-switching
inverters.
The relative frequency deviations in term of power supply voltage for all three type of
ring oscillators pictured in Fig. 6 are given in Fig. 7. By analyzing the results presented
in Fig. 7 we can conclude the following: The relative sensitivity of the ring oscillator from
Fig. 6 a) is less than 2%, while for those given in Fig. 6 b) and c) is less than 1%.
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 6
Fig. 6. Combined ring VCOs
Fig. 7. Relative frequency deviation in term of power supply voltage variation for proposed ring VCOs
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 7
4 Jitter and phase noise in ring oscillators
In general, CMOS circuits are sensitive both to power supply and temperature variations, as
well as to noise generated in IC’s building blocks (noise is inserted through power supply
and the substrate). Due to these effects, the propagation delay, td, is variable [10], [11], [12].
As a consequence there are variations in td, in respect to its nominal value. This deviation
is manifested as variation of the rising and falling pulse edges, and is referred as jitter (see
Fig. 8).
td
Dtd
VSW
Fig. 8. Jitter effect
As can be seen from Fig. 8 the jitter for the rising edge is defined as a rms time error
value, td
2. The normalized jitter value is defined as a ratio between the effective time
error and its nominal delay value, i.e. tdrms
td.
Consider now a VCO with nominal period T0, and with a timing error accompanying
each period that is Gaussian, with zero mean and variance tVCO
2. If this timing error is
expressed in terms of phase, ∆Φ =2
π
t/T0, then the variance of the phase error per cycle
of oscillation is given by [10]
σ
2
Φ= (2
π
)2(TVCOrms
T0)2
(7)
The amount of phase noise for all types of ring oscillators discussed in this paper is
sketched in Fig. 9. By analyzing Fig. 9 we can conclude that the best performance (phase
noise approx. 0.06 rad) have ring oscillators based on current starved inverters with output-
switching, while the worst (phase noise approx. 0.3 rad) correspond to ring oscillators
realized with basic type or current starved with power-switching inverters. Combined ring
oscillators, composed of basic and current starved with output-switching inverters, have
approximately phase noise within the range 0.16-0.2 rad.
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 8
Fig. 9. Relative frequency deviation in term of power supply voltage variation for proposed ring VCOs
5 Conclusion
Ring oscillators are basic building blocks of complex integrated circuits. They are mainly
used as clock generating circuits. Many different types of ring oscillators are presented
in literature [1]-[4]. They differ in respect to architectural, realization of inverters stages,
number of inverter stages, etc. In this paper we have considered realization of ring oscillator
based on four different types of single-ended inverters. The simulation was performed using
HSpice Version 03.2006 and library model for 1.2
µ
mCMOS technology. According to the
obtained simulation results we can conclude:
a) that for frequency stability in terms of temperature variations the best performance
(f/f<2%) has current starved inverters with output-switching;
b) that for frequency stability in terms of power supply voltage variations the best per-
formance (f/f<4%) has current starved inverters with power-switching;
c) by realizing combined types of ring oscillator the relative frequency deviation in
terms of power supply voltage variations can be significantly decreased (f/f<2%)
in respect to the best standard solutions (f/f>4%).
d) in respect to phase noise, ring oscillators based on current starved inverters with
output-switching have the best performance (phase noise approx. 0.06 rad).
References
[1] C. H. PAR K, O. KIM , B. KI M,A 1.8-GHz self-calibrated phase locked loop with precise
I/Q matching, IEEE J. Solid-State Circuits, vol. 36, (2001), 777-783.
[2] L. SU N AN D T. A. KWASNIEWSKI,A 1.25-GHz 0.35- m monolithic CMOS PLL based on a
multiphase ring oscillator, IEEE J. Solid-State Circuits, vol. 36, (2001), 910-916.
[3] J. SAVOJ A ND B. RA ZAVI,A 10-Gb/s CMOS clock and data recovery circuit with a half-rate
linear phase detector, IEEE J. Solid-State Circuits, vol. 36, (2001), 761-767.
A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability 9
[4] C. K. K. YANG , R. FARJAD-RAD, M. A. H OROWITZ,A 0.5- m CMOS 4.0-Gbit/s serial
link transceiver with data recovery using oversampling, IEEE J. Solid-State Circuits, vol. 33,
(1998), 713-722.
[5] M. AL IOT O, G . PAL UM BO , ”Oscillation frequency in CML and ESCL ring oscillators”,
IEEE Trans. Circuits Syst. I, vol. 48, (2001), 210-214.
[6] B. RAZAVI,A 2-GHz 1.6-mW phase-locked loop, IEEE J. Solid-State Circuits, vol.
32,(1997), 730-735.
[7] S. Docking, M. Sachdev, A Method to Derive an Equation for the Oscillation Frequency
of a Ring Oscillator, IEEE Trans. on Circuits and Systems - I: Fundamental Theory and
Applications, vol. 50, 2,(2003), 259-264.
[8] G. JOVAN OVI ´
C, M. STO J ˇ
CE V,Current starved delay element with symmetric load, Interna-
tional Journal of Electronics, Vol. 93, 3, (2006), 167-175.
[9] O.-C. CHE N, R. SHE EN,A Power-Efficient Wide-Range Phase-Locked Loop, IEEE Journal
of Solid State Circuits, vol.37, 1, (2002), 51-,.
[10] TODD CH AR LE S WEIGANDT,Low-Phase-Noise, Low-Timing-Jitter Design Techniques for
Delay Cell Based VCOs and Frequency Synthesizers, PhD dissertation, University of Cali-
fornia, Berkeley, 1998.
[11] S. DO CK IN G,A ND M. SACH DEV,An Analytical Equation for the Oscillation Frequency of
High-Frequency Ring Oscillators, IEEE Journal of Solid State Circuits, vol.39, 3, (2004),
533-537.
[12] A. HAJIMIRI, S. LIMOTYRAKIS, T. LE E,Jitter and Phase Noise in Ring Oscillators, IEEE
Journal of Solid State Circuits, vol.34, 6, (1999), 790-804.
[13] G. JOVAN OVI ´
C, M. ST OJ ˇ
CEV,A Method for Improvement Stability of a CMOS Voltage
Controlled Ring Oscillators, ICEST 2007, Proceedings of Papers, vol. 2, pp. 715-718, Ohrid,
Jun 2007.
... Considering this, the general architecture of a single-ended implemented ring oscillator with its linearised model is shown in Fig. 6 where N is always an odd number [29]. The utilised delay cell for oscillator which was previously proposed in [28], is illustrated in Fig. 7. ...
... For better comparison, the same simulations were applied to the conventional architecture of [23] and the structure reported in [30]. Fig. 7 Employed delay cell of [29] for ring oscillator block At the simulation frequency of 1.1 GHz which is equal to the period of 0.9 ns, the measured dead zone for proposed PFD was 0.02 ns while the obtained value for structures of [23,30] were 0.1 and 0.15 ns, respectively. Therefore, the calculated dead zone of our work will be Dead zone = 0.02 ns × 2π 0.9 ns = 2π 45 (26) Considering (26), the corresponding dead zones for [23,30] will be 2π/9 and 2π/6 , respectively. ...
Article
Full-text available
In this study, the design routine of a novel phase frequency detector and charge‐pump (PFD‐CP) is discussed. The main advantage of the proposed circuit is its improved dead zone performance as the circuits of PFD‐CP have been merged to reduce the latency of the structure. To justify this, by means of a reconfigurable loop filter, a fast‐locking low‐power phase‐locked loop (PLL) has been implemented which can operate at the range of 100 MHz–1.2 GHz while its power consumption is 2.53 mW at 1.2 GHz operating frequency. The whole PLL is implemented in 0.18 µm complementary metal–oxide–semiconductor technology with a 1.8 V power supply. The post‐layout simulation results are provided to show the conformity of theoretical assumptions and circuit‐level implementations which depict the locking time of 0.54 µs at 1.2 GHz operating frequency.
... The phase noise in the Voltage controlled oscillator plays a crucial role in the design, may degrade the overall performance of the system, if not properly optimized. In the range of GHz Frequency generation applications, Ring oscillators and LC oscillators are commonly used [ [15], [16] , [17]]. Compare to LC oscillator, Ring oscillators suffer from poor phase noise, so LC VCO is the better choice for RF -ISM band applications. ...
... For obtaining the propagation delay, different approaches are followed in the literature. In case of SERO, the gate capacitance of the inverter is utilized, and delay is computed in terms of the effective capacitance and the switching current [7], [8]. This is expressed in (3). ...
Conference Paper
Full-text available
In this article, the design and simulation results of single ended as well as differential ring oscillators are presented. The empirical equations are made use of, for the purpose of design and comparison. For the single ended ring oscillator, initially a 5-stage circuit is utilized, with different Beta ratios. Later on, the circuit simulation is performed from 5-stage till 23-stage, and the output is obtained as 3.0817 GHz and 0.6705 GHz respectively. Similarly, for the differential ring oscillator, initially a 7-stage circuit is utilized, with different Beta ratios. Later on, the circuit is simulated from 3-stage till 21-stage, and the output is obtained as 2.6925 GHz and 0.3756 GHz respectively. The difference in between the computed and the simulated output with single ended and differential ring oscillators is found to be 3.64% and 1.98% respectively.
Conference Paper
The Internet of Things (IoT) concept is mainly enabled by wireless sensor networks (WSNs), which are continuously gaining attention, due to their multidisciplinary applications. To enhance the WSNs energy efficiency, different solutions have been proposed. One of them is the integration of wakeup receivers (WuRxs), which activate the sensor nodes through an identity-based approach. In this work a low power oscillator-based WuRx architecture is presented, and verified by simulations in TSMC-180nm CMOS process. The WuRx sequentially verifies if the received signal resembles the wake-up call (WuC) one by means of oscillators, counters and logic gates. It consumes 16.1μW when detecting a 1.6ms WuC signal, and 1.2nW in idle mode.
Chapter
Dynamic voltage and frequency scaling (DVFS) is useful for low power digital circuit design. The work proposes a novel DVFS module offering any finer clock frequency change to produce an appropriate supply voltage to feed a digital circuit driven by DVFS module. In DVFS with varying supply and clock conditions the chances of setup and hold timing violations in D flip-flop (DFF) circuit may increase. The DVFS module driving a digital circuit utilizing Razor D flip-flop is used to correct errors occurring due to timing violations. The proposed circuit simulation shows that DVFS module driving simple D flip -flop shows error due to timing violations, while the DVFS module driving Razor D flip-flop shows the correct operation. In the digital pipelined circuits any occurrence of timing violations, the Razor DFF uses the error correction mechanism to prevent data loss with a penalty of one additional clock cycle.
Chapter
Interconnects are the basic connections used to establish between two silicon-based chips or devices. Basically, the interconnect quality and size differ based on the physics on which these work, such as electrical and/or optical. With the increased demand of the high quality and speedup communication, it is essential to work on the various different aspects of the chip. Conventional interconnects used in electronics devices are basically electrical, and these are reaching to their limits. Since Moor’s law suggests that the density of electrical component gets double in every 18 months, but with the increasing density of the components on/off chip, it is not possible to scale interconnect beyond a particular limit. Optical interconnects are feasible option which overcome the delay, loss, parasitic capacitance, etc., of electrical interconnect. In optical interconnects, nonlinear signals are transmitted through silicon-based waveguide through either two-dimensional or three-dimensional fabrication. Progression in nanotechnology made it viable to arrange light source; laser, medium; waveguide, and detector; and photodiode into a single silicon chip. However, there are still a lot of challenges to commercially implement dense optical interconnects to silicon chips, such as losses, packaging, and integration of two different technologies in single chip. It is observed that optical interconnect technology is not mature enough and needs a thorough analysis. On the designing aspect, there are a lot of features of optical interconnects which need to be addressed. Thus, this chapter is focused on optical interconnects for silicon on insulator (SOI) chips, analyzed the work which is already done and the basic challenges in this technology to make it practical.
Article
Full-text available
Variable delay elements are often used in different types of high-speed integrated circuits, mainly intended for delay compensation, skew equalization, etc. These circuits are normally realized as hybrid, composed of digital and analog controlled parts. The digital part is used for coarse-grain, while the analog for fine-grain delay variation. Efficient analog delay element architecture is proposed in this paper. The proposal is based on modification of the standard current starved delay element solution. An analytical equation that corresponds to the delay of the circuit is given also. In terms of control voltage, the proposed circuit has a linear delay transfer function in the whole range of regulation. Improvement is achieved at a cost of small hardware overhead in respect to the standard solution. Delay linearity error is less than 1% and the agreement between analytical model and simulation results is good, i.e. the error is less than 5%.
A new method for deriving an equation for the oscillation frequency of a ring oscillator is proposed. The method is general enough to be used for a variety of types of delay stages. Furthermore, it provides a framework to include various parasitic and secondary effects. The method is used to derive an equation for a common ring oscillator topology. The validity of the method and the resulting equation have been verified through simulation. The oscillation frequencies predicted by the proposed method are more accurate than existing equations and account for more secondary effects.
In this paper a model to accurately evaluate even in a pencil-and-paper manner the oscillation frequency of a ring oscillator made up by a CML or ESCL differential gate is proposed. The model allows us to simply estimate the oscillation frequency changes due both to the bias current change and to process tolerances. The model was validated by Spice simulations on both 6- and 20-GHz technologies for the CML ring oscillator, and on 0.8-μm CMOS process for the ESCL ring oscillator. The estimated oscillation frequency agrees with the simulated one. Indeed, average errors lower than 10% were found
Article
An analytical equation for the oscillation frequency of a ring oscillator is derived. The derivation is done using a novel method which does not need to find an expression for the delay of each stage. The resulting equation includes the effect of time-varying parasitics. It also includes the effect of the gate resistance, which has a large effect on the oscillation frequency at high frequencies. Measurement results of ring oscillators fabricated in a 0.18-μm CMOS process show that the resulting equation has an average error of 8% over a large range of parameter variations.
Article
This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-μm CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations
Article
A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-μm CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply
Article
A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm<sup>2</sup>, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10<sup>-6</sup>, with random data input of length 2<sup>23</sup>-1. The power dissipation is 72 mW from a 2.5-V supply
Article
This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-μm CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply
Article
A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed