Article

On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays

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Abstract

Often, when performing fixed-point multiplication, it is sufficient to return a faithfully rounded result, i.e., the machine representable number either immediately above or below the arbitrary precision result, if the latter is not exactly representable. Compared to correctly rounded multipliers, i.e., those returning the nearest machine representable number, faithfully rounded multipliers use considerably less silicon area, typically by implementing a truncation scheme within the partial product array. A number of such heuristically inspired schemes exist in the literature, however their use in industrial practice is hampered by the absence of verification, and exhaustive simulation is typically infeasible, e.g., a 32 bit multiplier requires ${bf 2}^{bf {64}}$ simulations. We present three truncated multiplier schemes which subsume the majority of existing schemes and derive both closed form necessary and sufficient conditions for faithful rounding. For two of the schemes we provide closed form expressions for the bit vectors giving rise to the worst-case error and the probability of encountering these inputs during Monte-Carlo simulation. From these expressions, we show how HDL code can be created that performs correct-by-construction faithfully rounded multiplication. We also present a method for truncating an arbitrary array while maintaining faithful rounding, creating two novel truncated multiplier schemes in the process.

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... Hence, in order to reduce the complexity of a multiplier, either the width m or the height n must be diminished. Lowering m leads to truncated multipliers [17]- [19], which is not the purpose of this work. Adopting the other approach, the height of the PPM is usually reduced by applying a Booth recoding [14], [15], [20] in radix R = 2 r , r > 0, which maintains the accuracy of the multiplier. ...
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... Hence, in order to reduce the complexity of a multiplier either the width m or the height n must be diminished. Narrowing m leads to truncated multipliers [10]- [12], which is not the purpose of this work. On the other hand, the height of the PPM is usually reduced by applying a Booth recoding [1], [8], [9] in radix R = 2 β , β > 0, which maintains the accuracy of the multiplier. ...
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This paper presents an error compensation method for fixed-width canonic signed digit (CSD) multipliers that receive a W-bit input and produce a W-bit product. To efficiently compensate for the quantization error, the truncated bits are divided into two groups (major group and minor group) depending upon their effects on the quantization error. The desired error compensation bias is first expressed in terms of the truncated bits in the major group. Then the effects of the other truncated bits in the minor group are taken care of by a probabilistic estimation. Also, an efficient sign extension reduction method applied to the fixed-width CSD multipliers is proposed. By simulations, it is shown that 25% reduction in the truncation error and 13% hardware complexity can be achieved by the proposed error compensation and sign extension reduction methods, respectively.
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About half the hardware for floating point multipliers is needed only to guarantee correctly rounded results. For multimedia, graphics, and DSP systems, a significant reduction in area, delay, and power can be achieved by producing results that are not correctly rounded. This paper presents an efficient method for designing variable-correction truncated floating point multipliers that produce results with a maximum error of less than one unit in the last place. With this method, several of the less significant columns of the significand multiplier and the rounding logic for floating point multiplication are eliminated. Technical areas: (13) DSP hardware, software, and coreware; (14) ASIC and FPGA algorithm/processor design. POC: Michael Schulte, 19 Memorial Dr. West, EECS Dept., Lehigh University, Bethlehem, PA 18015. Email: mschulte@eecs.lehigh.edu, Phone: (610) 758-5036, FAX: (610) 758-6279. Extended Abstract Most modern processors perform floating point operations accord...
Coding Guidelines for Datapath Synthesis.
  • R Zimmermann
R. Zimmermann, " Coding guidelines for datapath synthesis, " https://www.synopsys.com/dw/doc.php/wp/coding guidelines.pdf, July 2005.