Fast Real-Time Hardware Engine for ZWC Text
Ammar Odeh, Khaled Elleithy, and Miad Faezipour
Dept. of Computer Science and Engineering
University Of Bridgeport
Bridgeport, CT 06604, USA
firstname.lastname@example.org, email@example.com, firstname.lastname@example.org
Abstract—Different strategies were introduced in the
literature to protect data. Some techniques change the
data form while other techniques hide the data inside
another file. Steganography techniques conceal
information inside different digital media like image,
audio, and text files. Most of the introduced techniques
use software implementation to embed secret data inside
the carrier file. This is while software implementations are
not sufficiently fast for real-time applications. In this
paper, we present a new real-time zero-width-character
(ZWC) Steganography technique to hide data inside a text
file using a hardware engine with 6.415Gbps hidden data
rate. The fast Steganography implementation is presented
in this paper.
Keywords—Steganography; Steganayalsis; Hardware
Different strategies have been used to protect
sensitive data during transmission over unsecure
channels. Some algorithms suggested changing plain
text into cipher text, which is called cryptography. On
the other hand, some algorithms are presented to protect
secret information by hiding its existence.
Steganography is a security mechanism used to hide
data inside a carrier file such as image, sound, video, or
text . Secret information can be inserted inside the
carrier file using different strategies, where each one of
them has advantages and drawbacks. The first insertion
technique is the case where data is injected inside a
carrier file. This increases the file size and sometimes
changes the file format. The second suggested
technique is substitution, where sensitive information is
replaced by other information from the carrier file. The
substitution method searches for bits that have the
lowest effect in the carrier file to apply the exchange
operation on them. The main advantage of this
technique is that the Stego object is the same size as the
carrier file, and this avoids any attacker suspicions. The
main idea is to hide data inside the carrier file and then
place the Stego file in some transport media. Stego-
analyst will start analyzing the data if there is any
suspicion about the carrier file. Some file properties
will be basic rules for the analyzer to discover the
hidden data. The file size and file format are examples
of such properties.
Most of Steganography algorithms are applied on
images which contain huge amount of redundant data.
The Least Significant Bit replacement algorithm (LSB)
is one such Steganography algorithm . Other
complex algorithms are introduced to be applied on
images. However, the main problems that are faced in
image steganography are :
I. File Size: - Image file sizes are already
relatively large compared to other files.
II. Image Distortion: - The replacement of some
bits may destroy/distort the image, and this
will enable the Stego-analyst to acquire the
hidden data .
III. Deterministic Changes: The same
deterministic algorithm will produce the same
distribution bits over the image and this will
produce the same hidden image area style. In
other words, if we try to replace white pixels
by red ones, all white pixels will be converted
to red, and this way, the original file could be
Audio carrier files also have some weak points, since
any audio signal can be converted and processed in
frequency domain and by computing the lower control
limit and upper control limit, we can deduce if there are
any hidden data in that file. Video carrier files have the
disadvantages of merging the weaknesses in sound and
image files [5, 6].
Text files represent the smallest files in terms of size
that can be used to transfer data from sender to receiver,
when compared with the other carrier files .
Moreover, huge amount of textual data over the internet
enables us to hide data over different websites and
update those websites with a new style of hidden
information that can be embedded within the files. On
other hand, text files represent the most difficult
Steganography carrier files that do not have redundant
patterns like other carrier files  .
In this paper, we build on top of our prior work and
apply our ZWC  algorithm over hardware concepts
to speed up the system efficiency. In our algorithm,
we also suggest optimization techniques to offer the
highest performance to achieve “Magic Triangle
Concepts” for Steganography; that is, the function
ability to achieve transparency, robustness, and hiding
The rest of this paper is organized as follows. In
Section II, we discuss previous text Steganography
techniques. Our proposed ZWC hardware engine is
discussed in Section III. Discussion and analysis of our
algorithm are also provided in the same Section.
Simulation results are provided in Section IV. Finally,
concluding remarks are offered in Section V.
II. PRIOR WORK
In , a novel hardware design was proposed for
image steganography using the least significant bit
(LSB) algorithm. The implementation was carried out
using Cyclone II FPGA of the ALTERA family. The
technique employed 2/3LSB design to produce a good
image quality to avoid any attacker doubt. Meanwhile,
it provided a high memory access performance to speed
up the system performance. In , an FPGA hardware
architecture was introduced to hide the secret
information by exploiting the noise regions in an image.
This strategy improved system transparency which
made it hard to realize the hidden data. In , an
implementation of audio or video Stenography using
FPGAs was discussed. The proposed algorithm speeds
up the secret data embedding rate at the hardware
implementation for real-time Steganography. Another
hardware architecture was introduced in  to
simulate the ability to hide information inside image
and video carrier files. Two schemes were applied to
speed up real-time video applications. The main
drawback of this system is its need for a high speed
memory buffer. In , the proposed algorithm
employed image as carrier file by using multilayer
embedding in parallel with three-stage pipeline on
FPGA. Promising results showed high throughputs
while maintaining the image quality. In  and ,
authors employed perturbed quantization to hide data
inside JPEG image. The main feature of perturbed
quantization is that it is undetectable with current
As can be seen, most of the presented algorithms
were implemented in hardware focus on image, video,
or audio as the carrier file for the secret message. This
is while text steganography has not been considered for
implementation in hardware engines and/or digital
III. PROPOSED MODEL
In this paper, a novel hardware engine
implementation is presented over text as a carrier file.
The process is based on this underlying concept that we
try to hide data inside a word file without any change in
the file format. Stego-analyst will try to analyze the file
containing the formatting. If there is any change in the
file format, the hidden data can be caught. In this work,
we will use the Zero Width Character (ZWC);Ctrl+
Shift +I; algorithm. The Unicode character for ZWC is
U+200B, which does not occupy any space or change
the file formatting. By adding ZWC before and after the
space character, we can hide data.
In Microsoft Word, it’s a possible to count the
number of characters in any file without counting space
characters. Therefore, after adding ZWC, the number of
letters will not be increased. The proposed algorithm
counts the number of spaces between words to evaluate
which file can hold more secret data.
The Hiding Data Algorithm describes the scenario at
the hidden stage. Software implementation of this
technique would consist of two steps. The first stage is
the searching process and the second stage is
processing. By hiding data in the file, the time
complexity will be ,where M is the number
of carrier files, and N is the number of bits we want to
embed inside the file. The best case is . In the
hardware implementation, however, a high speed
performance can be achieved while increasing
Steganography’s robustness and transparency.
A. Hiding Data Algorithm
The main algorithm used in this hardware engine
implementation is presented in , where complete
details are provided. For the purpose of this discussion,
we show here a simple sketch of the algorithm.
Algorithm I: Hidden Data
Input:-File: Hidden bits file
Output: - Stego file (embedded ZWC inside file)
Step1:- Choose any text file
Step2: Measure space ratio in selected test file, if
successful, continue, otherwise go back to Step1
Step 3. Repeat while! (EOF)
Step4: Embed hidden data inside selected file by:
Step 4a. Select space
Step 4b. Pack out first two hidden bits
If 00, then, no ZWC before space
Else if 01, then there is no ZWC after
Else if 10, then there is ZWC before space
Else, there is ZWC after space character.
Step 5: Go to Step 3
Step 6: Save file and send it.
For implementing this algorithm in hardware, a state
transition diagram must be constructed that reflects the
algorithm procedure. Figure 2 shows the state diagram
of the system. This system consists of five states, where
each state depends on the input value (e.g. character in
the text file) and the hidden data. State A represents the
initial state of the search. The hidden information
represents an input data to transfer from one state to
Figure 3 represents the main components of the
hardware engine in RTL view. The system consists of
four comparison units to check the hidden information
in order to choose a suitable data path based on what
the hidden data bits are. Table I provides a list of the
used components representing the device utilization of
the FPGA for this hardware engine.
Furthermore, the system checks the input file data
too. It searches in the carrier file to insert ZWC
depending on the hidden data. In other words, two sets
of inputs decide the next state transition in the state
IV. SIMULATION RESULTS
Table III represents the simulation results of the file
size and number of bits added to web page carriers.
ZWC and space algorithm have the following
I. File format will not be changed.
II. Can be applied to any code (e.g. Unicode,
ASCII). In other word, this algorithm can be
applied to any language.
III. As Figure 1 shows, the file size will not be
Figure 1. Size effect after add secret data in carrier file
In our implementation, we process the hidden file
two bits in each step to hide it and then transition the
current state to another state based on the conditions.
Figure 4 shows the signal analysis of data inserted and
the system states transformation using a timing wave
The state transitions occur based on the conditions
of the input data characters and hidden data bits.
The critical path time reported by the tool (Quartus
II) is . Hence,
We process 16 bits in each clock cycle. Therefore,
the system has an overall throughput of
6.415Gbits/second. This is while software simulations
would require O (n) time to process any file, and are
controlled by the file size and processor speed.
Table I. Device Utilization of the FPGA
ALTERA Cyclone DE II
Met timing requirements
Total Logic elements
Total virtual pins
Table II provides a list of hardware-based
steganography algorithms. All the presented hardware
implementations process audio, image or video files. To
the best of our knowledge, there is no hardware systems
reported in the literature for processing text. The ZWC
Algorithm hardware implementation represents one of
the unique text Steganography algorithms, as it
provides very high speed processing of real-time
applications while maintaining a minimum memory
Table II. Steganography Hardware Engines
2/3 Image Steganography
Noisy region of image
Multilayer and parallel Image
Text file/ without change file size
V. CONCLUSIONS AND FUTURE DIRECTIONS
In this paper, we presented a fast and real-time
hardware implementation for secure and safe
communications over networks. We have presented the
hardware implementation of the ZWC algorithm. The
proposed design represents one of the fastest text
steganography techniques in hardware. Previous
implementations provided efficient hardware
implementations over other carriers such as image,
video or audio files. This is the first hardware
implementation presented in literature for text
Steganography. In the future, we are planning to present
a parallel processing design to optimize the system
encryption speed and power consumption for the ZWC
algorithm as well as other text Steganography
1 2 3 4 5 6
page size (byte)
File Size Change
Figure 2. Finite State Machine Diagram
Figure 3. RTL view of the hardware engine
Figure 4. Timing Simulation results of the hiding data algorithm and state transitions (where space as input).
Input: - space
Table III. File size and the number of bits added to carries web pages
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