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A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM cell
Abstract
Improving the Noise margin is one of the important challenge in every state of the art SRAM design. Due to the Process variations like threshold voltage variations, supply voltage variations etc.. in scaled technologies, stable operation of the bit cell is critical to obtain with high yield in low-voltage SRAM. In this paper a new assist technique (Read assist and write assist) is proposed to enhance the read and write margins of the 6T SRAM bit cell and the same write assist circuit is applicable to enhance the write margin of the 8T SRAM bit cell. The simulations are performed in 90nm TSMC process Technology node and the read and write margin simulation results are compared with different SRAM circuits like 6T SRAM bit cell with cell ratio of 1, 2, 3 and Dynamic word line swing technique and 8T SRAM bit cell. The effect of temperature and threshold voltage values on Read and Write margins are observed. By using the proposed read assist technique the read margin is improved by 2.375 times for 6T cell and with write assist technique the write margin is improved by 1.89 times for 6T and 8T cells.
... Word line voltage is reduced by a Vt drop using an NMOS device [5], [13]. Which is applied to the gate to source voltage of pass transistor and this voltage level is lower than the supply voltage. ...
The objective of this paper is to demonstrate how to improve the read stability of the SRAM cell using the read assist technique. SRAM cell stability is the primary concern for the present and future technologies due to process variations like Vt and Vdd scaling, etc. So it requires additional circuit techniques such as write and read to assist to improve the stability of SRAM memories. To accomplish the non-destructive read operation, we need to either weaken the pass transistor or strengthen the pull-up transistor during the read operation. Towards decrease of pass transistor strength, we implemented the lower word line voltage as read assist circuit. The lower word line voltage will help the selected and un-selected columns (for higher column mux options) during a read operation. But during write operation the lowered word line voltage scheme will impact the write operation. So, in order to improve the read margin we used read assist technique at the same time to ensure that write operation is successful we combined the negative bit line write assist scheme along with read assist technique. The proposed assist circuit gain the power and read margin improvement of 10%, 30% respectively. We observed the read margin analysis at process, voltage and temperature corners.
... As it can be seen inTable 4, RSNM is not very affected. Despite that, in[20], a technique to recover the RSNM of a 6T cell is analyzed. In addition, WSNM is degraded in some cell types (the ones in which pMOS transistors are increased in size). ...
Due to integrated circuit technology scaling, a type of radiation effects called single event upsets (SEUs) has become a major concern for static random access memories (SRAMs) and thus for SRAM‐based field programmable gate arrays (FPGAs). These radiation effects are characterized by altering data stored in SRAM cells without permanently damaging them. However, SEUs can lead to unpredictable behavior in SRAM‐based FPGAs. A new hardening technique compatible with the current FPGA design workflows is presented. The technique works at the cell design level, and it is based on the modulation of cell transistor channel width. Experimental results show that to properly harden an SRAM cell, only some transistors have to be increased in size, while others need to be minimum sized. So, with this technique, area can be used in the most efficient way to harden SRAMs against radiation. Experimental results on a 65‐nm complementary metal‐oxide‐semiconductor (CMOS) SRAM demonstrate that the number of SEU events can be roughly reduced to 50% with adequate transitory sizing, while area is kept constant or slightly increased.
In addition, critical charges for a 6T cell for various combinations of Wp, Wn were calculated. Figure 6 shows the results in a graph where the independent variables are rp, rn. Results are shown for two different pulse widths and only for Qcrit,e, since Qcrit,h show similar results.
If the charge collection efficiency values obtained as fitting parameters are analyzed, it is confirmed that charge collection efficiency for electrons (ηe) is higher than for holes (ηh) [19]. In addition, critical charge for electrons (Qcrit,e) is smaller than for holes (Qcrit,h). This electron and hole asymmetry in terms of charge collection efficiency and in terms of critical charge is the root cause of the observed differences of SER dependency with rn and rp.
Results also show that SER is improved by increasing the pMOS transistors channel width (Wp), and worsened when the nMOS transistors channel width is increased (Wn). For this reason, the best way to design a hardened 6T SRAM cell is by minimizing the nMOS transistors channel width and dedicating all additional area to increase pMOS transistor channel width. In addition, for a 65‐nm CMOS commercial technology, SER was reduced to a 57% of the value that conventional nonstructured layout cells exhibit. Due to careful transistor sizing, this radiation robustness improvement was achieved with minor area penalty. However, this hardened cells with wider pMOS transistors, also show a reduction in cell writability. To overcome this issue, write assist techniques can be implemented. Nevertheless, if a trade‐off between writability, area, and radiation robustness is achieved by proper transistor sizing, hardened cells remain writable without any further action. Finally, with the modulation technique presented in this chapter, the achieved cell radiation robustness gain is fundamentally an area trade‐off, provided that the cell remains writable. For this reason, at design level, radiation robustness can be set as an adjustable parameter in memory compilers.
Conventional 6T SRAM cell parameters have degraded with scaling to newer technologies and reduced power supply voltages. This has led to numerous tradeoffs with respect to cell stability, performance, power, and area. In this paper, a novel Dual Port SRAM design has been introduced that aims at improving the read and write ability of the standard 6T SRAM cell. The simulations for the proposed structure have been performed on HSpice using PTM 32nm Technology node. The comparison of results with the standard cell showed an increase of 84.76% in read margins and 40.81% in the write stability. Also, the proposed design was found to be capable of writing at high frequencies as the minimum pulse width of WWL for a successful write operation was determined to be 25ps. Further, the design also improves in the areas of WTV, SVNM, WTP, SPNM
The explosive growth of battery operated devices has made low-power design a priority in recent years Moreover, embedded SRAM units have become an important block in modern SoCs. Present day SRAMs are striving to increase bit counts while maintaining low power consumption and high performance. To achieve these objectives there is a need of continuous scaling of CMOS transistors, and so the process technology scaling and need for better performance enabled embedding of millions of Static Random Access Memories (SRAM) cells into modern-day ICs. In several applications, the embedded SRAMs can occupy the majority of the chip area and contain hundreds of millions of transistors. As the process technology continues to scale deeper into the nanometer region, the stability of embedded SRAM cells is a growing concern. The supply voltage must scale down accordingly to control the power consumption and maintain the device reliability. Scaling the supply voltage and minimum transistor dimensions that are used in SRAM cells challenge the process and design engineers to achieve reliable data storage in SRAM arrays. This task is particularly difficult in large SRAM arrays that can contain millions of bits .In this paper we proposed a novel 9T SRAM cell with the objective to increase the stability and reduce the leakage for multimedia mobile applications at deep submicron level. All the Simulations are done at 45nm technology.
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have special correlation and similar data are read out in consecutive cycles. As well as the power reduction, the precharge-less structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% reduction) on the bitlines, and saves 74% of a readout power when considered as an H.264 reconstructed-image memory. The area overhead is 14.4% in a 90-nm process technology.
This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCCmin estimation for active VDD scaling designs.
We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.
Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its limitation like read disturbance. In this paper we have analyzed a novel PP based 9T SRAM at 45 nm technology. Cell which has 33% increased SVNM (Static Voltage Noise Margin) from 6T and also 22% reduced leakage power. N curve analysis has been done to find the various stability factors. As compared to the 10T SRAM cell it is more area efficient.
SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the β ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124μm<sup>2</sup> half-cell) and full 8T (0.1998μm<sup>2</sup>) cells to date.
We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To minimize the discharge power on a read bitline, a majority-logic circuit decides if input data should be inverted in a write cycle, so that ldquo1rdquos are in the majority. In addition, for further power reduction, write-in data are reordered into digit groups from the most significant bit group to the least significant bit group. The measurement result of a 68-kbit video memory in a 90-nm process demonstrates that a 45% power saving is achieved on the read bitline. The speed and area overheads are 4% and 7%, respectively.
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.
We redefine write margin in order to be able to quantify the effect of both PVT variation and write-margin improvement. A write-margin monitoring circuit based on this definition is implemented in a 90nm CMOS process. This circuit can be applied to an SRAM power supply circuit to improve the write margin
A new SRAM circuit technique based on dynamically adjusting the wordline voltage swing is proposed in this paper for reducing the leakage power consumption and enhancing the data stability in static memory banks. With the proposed technique, the wordline voltage swing is reduced in order to suppress the voltage disturbance at the data storage nodes during a read operation. The stability of a minimum sized standard six transistors (6T) SRAM cell is thereby significantly enhanced. Alternatively, during a write operation the wordline signal has a full voltage swing in order to achieve write-ability with a high write margin. With the proposed circuit technique, the static noise margin is enhanced by up to 122% as compared to the conventional full-voltage-swing 6T SRAM circuits with minimum sized transistors. Furthermore, the leakage power consumption with the proposed technique is reduced by 51% as compared to the conventional full-voltage-swing circuits sized for data stability in a 65nm CMOS technology.
A single-power supply 64 kB SRAM is fabricated in a 45 nm bulk CMOS technology. The SRAM operates at 1GHz with a 0.7 V supply using a fine-grained bitline segmentation architecture and with an asymmetrical unit-ratio 6T cell. With the asymmetrical cell, 22% cell area has been saved compared to a conventional symmetrical cell. This bulk SRAM is designed for GHz-class sub-lV operation.
Variability in process parameters is making accurate estimate of nano-scale SRAM stability an extremely challenging task. In this paper, we propose a new method to detect the read failure in an SRAM cell using critical point sampling technique. Using this technique, we propose two types of read failure probability estimation method, (1) quasi-analytical and (2) completely analytical method. The result shows that our proposed model can achieve high accuracy, while being 20× faster in computational speed. Our method can be applied to different phases of design to reduce the overall design time, and can be used for optimizing the given design in order to obtain a better yield.
The increased importance of lowering power in memory design has produced a trend of operating memories at lower supply voltages. Recent explorations into sub-threshold operation for logic show that minimum energy operation is possible in this region. These two trends suggest a meeting point for energy-constrained applications in which SRAM operates at sub-threshold voltages compatible with the logic. Since sub-threshold voltages leave less room for large static noise margin (SNM), a thorough understanding of the impact of various design decisions and other parameters becomes critical. This paper analyzes SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, V<sub>DD</sub>, temperature, and local and global threshold variation. The V<sub>T</sub> variation has the greatest impact on SNM, so we provide a model that allows estimation of the SNM along the worst-case tail of the distribution
The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing VLSI, 2007. ISVLSI '07
- M Kawaguchi
- Yoshimoto
Kawaguchi, M. Yoshimoto, "A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing," VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on, vol., no., pp.107-112, 9-11 March 2007.