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In non-volatile memories, reading stored data is typically done through the use of predetermined fixed thresholds. However, due to problems commonly affecting such memories, including voltage drift, overwriting, and inter-cell coupling, fixed threshold usage often results in significant asymmetric errors. To combat these problems, Zhou, Jiang, and Bruck recently introduced the notion of dynamic thresholds and applied them to the reading of binary sequences. In this paper, we explore the use of dynamic thresholds for multi-level cell (MLC) memories. We provide a general scheme to compute and apply dynamic thresholds and derive performance bounds. We show that the proposed scheme compares favorably with the optimal thresholding scheme. Finally, we develop limited-magnitude error-correcting codes tailored to take advantage of dynamic thresholds.

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... We refer to this type of read reference as a dynamic read reference. The approach was introduced first for single level cells (SLC) in [11] and generalized for multiple level cells (MLC) in [12], where it was shown that this detection is sub-optimal but has a performance that is superior to that of fixed read references. In this paper, fixed and dynamic read references will play pivotal roles within our study. ...

... The logical state of a cell is mapped into a voltage level reflecting the charge stored in its floating gate, i.e., s 0 reflects the lowest voltage while s q−1 reflects the highest voltage. Without loss of generality, it can be assumed that the states themselves are the voltages [12]. ...

... The boundaries of the regions are described by a read vector t = [t 1 , . . . , t q−1 ] ∈ R q−1 , where t i > t i−1 ∀i [12]. If the voltages of a wordline of size n are described by X = [x 1 , . . . ...

We present a novel data programming scheme for flash memory. In each word-line, exactly k out of n memory cells are programmed while the rest are kept in the erased state. Information is then conveyed by the index set of the k programmed cells, of which there are �n k possible choices (also called activation patterns). In the case of multi-level flash, additional information is conveyed by the threshold voltage levels of the k programmed cells (similar to traditional programming). We derive the storage efficiency of the new scheme as a function of the fraction of programmed cells and determine the fraction that maximizes it. Then, we analyse the effect of this scheme on cell-to-cell interference and derive the conditions that ensure its reduction compared to traditional programming. Following this, we analyse the performance of our new scheme using two detection methods: fixed reference detection and dynamic reference detection, and conclude that using dynamic reference detection will result in page error performance improvements that can reach orders of magnitude compared to that attainable by the fixed reference approach. We then discuss how logical pages can be constructed in the index programming similarly to traditional programming. Finally, we discuss the results and trade-offs between storage efficiency and error resilience proposed by the scheme along with some future directions.

... Several papers have explored dynamically adjusting to the degrading read channel [19]- [21]. In [19], read thresholds are progressively adjusted to minimize hard decoding BER or provide better log-likelihood for soft decoding based on previous reads. ...

... In [19], read thresholds are progressively adjusted to minimize hard decoding BER or provide better log-likelihood for soft decoding based on previous reads. In [20], [21], dynamic threshold assignment (DTA) adjusts the read thresholds to match the shifting and widening threshold voltage distributions of the read channel, significantly improving bit error rate (BER) performance. ...

... In [20], repetitive read operations are needed at relatively precise voltages to enable a bisection algorithm to place the read thresholds. In [21], threshold measurements of a certain number of cells are required. ...

The read channel of a Flash memory cell degrades after repetitive program and erase (P/E) operations. This degradation is often modeled as a function of the number of P/E cycles. In contrast, this paper models the degradation as a function of the cumulative effect of the charge written and erased from the cell. Based on this modeling approach, this paper dynamically allocates voltage using lower-voltage write thresholds at the beginning of the device lifetime and increasing the thresholds as needed to maintain the mutual information of the read channel in the face of degradation. The paper introduces the technique in an idealized setting and then removes ideal assumptions about channel knowledge and available voltage resolution to conclude with a practical scheme with performance close to that of the idealized setting.

... (ii) Up to now, various coding techniques have been applied to alleviate the detection in case of channel mismatch, such as, rank modulation [32], balanced codes [33][34][35][36][37], and composition check codes [38]. ...

... The notion of dynamic thresholds based on balanced codes is introduced in [33] for the reading of binary sequences. It is further shown to be highly effective against errors caused by voltage drift in Flash memories [34][35][36]. A balanced code consists of the sequences where the number of ones equals the number of zeros. ...

... If there is an intersection, it corresponds to the 3.2. MAXIMUM LIKELIHOOD DECODING FOR CHANNELS WITH BOUNDED NOISE AND OFFSET 3 35 parametric interval t 1 (r,x) < t 0 (r,x). Note that ψ(r −x) is immediately set to 0 without further computation if t 1 (r,x) > t 0 (r,x). ...

... In many applications, data retention time is more important than flash endurance. Likewise, read disturb, inter-cell interference, and temperature related charge losses occur [25][26][27][28]. Such charge losses result in shifts of the threshold voltages. ...

... Several publications proposed threshold adaptation concepts [25,[30][31][32][33][34][35]. These approaches adjust the read references to minimize bit error rates. ...

... However, the cell threshold voltage distributions of MLC and TLC are actually highly asymmetric with exponential tails [23,36,37] and cannot be estimated with Gaussian distribution. In [25,30], coding methods based on Berger codes are suggested that exploit the asymmetric error probabilities of the channel. Berger codes are used for error detection. ...

The performance and reliability of nonvolatile NAND flash memories deteriorate as the
number of program/erase cycles grows. The reliability also suffers from cell-to-cell interference, long data retention time, and read disturb. These processes effect the read threshold voltages. The aging of the cells causes voltage shifts which lead to high bit error rates (BER) with fixed predefined read thresholds. This work proposes two methods that aim on minimizing the BER by adjusting the read thresholds. Both methods utilize the number of errors detected in the codeword of an error correction code. It is demonstrated that the observed number of errors is a good measure for the voltage shifts and is utilized for the initial calibration of the read thresholds. The second approach is a gradual channel estimation method that utilizes the asymmetrical error probabilities for the one-to-zero and zero-to-one errors that are caused by threshold calibration errors. Both methods are investigated utilizing the mutual information between the optimal read voltage and the measured error values. Numerical results obtained from flash measurements show that these methods reduce the BER of NAND flash memories significantly.

... Constrained coding techniques, such as the rank modulation [12], balanced codes [13], and the constant composition codes [14], have also been proposed which can mitigate the unknown offset of the channel through sorting the channel readback signals. By leveraging on the balanced codes and the constant composition codes, the dynamic threshold schemes [15,16] were proposed for both the SLC and MLC flash memories. However, a major problem with all these schemes is the high code rate loss incurred by the corresponding constrained codes. ...

... where a * i is the center of each interval [b * 2i−1 , b * 2i ] with i = 1, 2, 3. In this way, by using (16), the optimization of {b * 1 , b * 2 , . . . , b * 6 } is converted to the problem of optimization of {W 1 , W 2 , W 3 }, which is a much easier task. ...

... The details of differential evolution optimization process are presented in [42]. to (16). We remark that for extending this work to TLC or QLC flash memories, the above described RNNA dynamic read thresholds design method is still valid. ...

The practical NAND flash memory suffers from various non-stationary noises that are difficult to be predicted. Furthermore, the data retention noise induced channel offset is unknown during the readback process. This severely affects the data recovery from the memory cell. In this paper, we first propose a novel recurrent neural network (RNN)-based detector to effectively detect the data symbols stored in the multi-level-cell (MLC) flash memory without any prior knowledge of the channel. However, compared with the conventional threshold detector, the proposed RNN detector introduces much longer read latency and more power consumption. To tackle this problem, we further propose an RNN-aided (RNNA) dynamic threshold detector, whose detection thresholds can be derived based on the outputs of the RNN detector. We thus only need to activate the RNN detector periodically when the system is idle. Moreover, to enable soft-decision decoding of error-correction codes, we first show how to obtain more read thresholds based on the hard-decision read thresholds derived from the RNN detector. We then propose integer-based reliability mappings based on the designed read thresholds, which can generate the soft information of the channel. Finally, we propose to apply density evolution (DE) combined with differential evolution algorithm to optimize the read thresholds for LDPC coded flash memory channels. Computer simulation results demonstrate the effectiveness of our RNNA dynamic read thresholds design, for both the uncoded and LDPC-coded flash memory channels, without any prior knowledge of the channel.

... In such a case, many studies on the MLC NAND Flash memories have been taken. For example, in [4], the channel model of beta-binomial is investigated; in [5] and [6], LDPC codes are adopted to correct errors; while in [7] and [8], the dynamic threshold is proposed to gain a lower raw error ratio. These traditional studies mainly concentrate on the errors in Earth-based applications. ...

... As our proposed error model is not a regular AWGN channel, the calculation result of the channel LLR doesn't have a simple expression. Specifically, with the modulation of {00, 01, 11, 10}, the LLR of the MSB is derived as (8) while the LLR of the LSB is derived as (9) With the modulation of {11, 10, 00, 01}, the LLRs are derived as (10) (11) Consequently, for the MSB, , the elements of PDF p MSB can be obtained by accurate LLR value. As shown in Fig. 5, we consider two methods of estimations: one is based on the input and output sequences of the LDPC decoder; the other is based on the time interval between adjacent time slots. ...

Utilizing commercial off-the-shelf (COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check (LDPC) coding scheme for improving the reliability of multi-level-cell (MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavy-ion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio (LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.

... To mitigate the effect of charge leakage, a straightforward way is to adopt asymmetric error-correcting codes [9], [10]. Dynamic threshold techniques, introduced by Zhou et al. [11] for SLC and extended to MLC by Sala et al. [12], have been shown to be not only highly effective against asymmetric errors caused by charge leakage but also offer some protection against over-programming. In error-correcting schemes with dynamic threshold, the codes have constant composition, and in particular, the case when the codes have both constant composition and balanced (where the number of times a symbol appears in a codeword is as close as possible) was studied in detail by Zhou et al. and Sala et al. [11], [12]. ...

... Dynamic threshold techniques, introduced by Zhou et al. [11] for SLC and extended to MLC by Sala et al. [12], have been shown to be not only highly effective against asymmetric errors caused by charge leakage but also offer some protection against over-programming. In error-correcting schemes with dynamic threshold, the codes have constant composition, and in particular, the case when the codes have both constant composition and balanced (where the number of times a symbol appears in a codeword is as close as possible) was studied in detail by Zhou et al. and Sala et al. [11], [12]. ...

... Also, coding techniques can be applied to alleviate the detection in case of channel mismatch. Specifically balanced codes [3], [4], [5] and composition check codes [6], [7] preferably in conjunction with Slepian's optimal detection [8] have been shown to offer solace in the face of channel mismatch. These coding methods are often considered too expensive in terms of coding hardware and redundancy when high-speed applications are considered. ...

... For clerical convenience we drop the variable r in (6). A minimum Pearson distance detector operates in the same way as the traditional minimum Euclidean detector, that is, it outputs the codeword x o 'closest', as measured in terms of Pearson distance, to the received vector, r, or in other words ...

We consider the transmission and storage of encoded strings of symbols over a noisy channel, where dynamic threshold detection is proposed for achieving resilience against unknown scaling and offset of the received signal. We derive simple rules for dynamically estimating the unknown scale (gain) and offset. The estimates of the actual gain and offset so obtained are used to adjust the threshold levels or to re-scale the received signal within its regular range. Then, the re-scaled signal, brought into its standard range, can be forwarded to the final detection/decoding system, where optimum use can be made of the distance properties of the code by applying, for example, the Chase algorithm. A worked example of a spin-torque transfer magnetic random access memory (STT-MRAM) with an application to an extended (72, 64) Hamming code is described, where the retrieved signal is perturbed by additive Gaussian noise and unknown gain or offset.

... To mitigate the effect of charge leakage, a straightforward way is to adopt asymmetric error-correcting codes [14], [15]. Dynamic threshold techniques, introduced by Zhou et al. [16] for SLC and extended to MLC by Sala et al. [17], have been shown to be not only highly effective against asymmetric errors caused by charge leakage but also offer some protection against over-programming. In error-correcting schemes with dynamic threshold, the codes have constant composition. ...

... In error-correcting schemes with dynamic threshold, the codes have constant composition. In particular, the case when the codes have both constant composition and balanced (where the number of times a symbol appears in a codeword is as close as possible) was studied in detail by Zhou et al. and Sala et al. [16], [17]. ...

We investigate constant-composition constrained codes for mitigation of intercell interference for multilevel cell flash memories with dynamic threshold scheme. The first explicit formula for the maximum size of a q-ary F-avoiding code with a given composition and certain families of substrings F is presented. In addition, we provide methods to determine the asymptotic rate for F-avoiding codes with any composition ratio and to find the optimal composition ratio that maximize the asymptotic rate. We also give the first efficient encoder/decoder for these q-ary constant-composition codes achieving the channel capacity, for all q.

... Several papers have explored dynamic threshold adaptation concepts [6], [7], [8], which adjust the read thresholds to minimize bit error rates. These dynamic threshold adaptation schemes can significantly reduce the BER. ...

... This assumption may not hold for all flash types, e.g. the cell threshold voltage distributions of MLC and TLC are actually highly asymmetric with exponential tails [9]. In [6], [7], coding schemes are proposed that exploit the asymmetric error probabilities of the channel, e.g. based on Berger codes. This technique requires either long codes for the threshold calibration or is only applicable for very high error rates. ...

... To mitigate the effect of charge leakage, a straightforward way is to adopt asymmetric error-correcting codes [6], [7]. Dynamic threshold techniques were later introduced by Zhou et al. [8] and extended by Sala et al. [9]; and the method is shown to be not only highly effective against asymmetric errors caused by charge leakage but also offer some protection against over-programming. In error-correcting schemes with dynamic threshold, the codes have constant composition, and in particular, the case when the codes are balanced (where the number of times a symbol appears in a codeword is as close as possible) was studied in detail by Zhou et al. and Sala et al. [8], [9]. ...

... Dynamic threshold techniques were later introduced by Zhou et al. [8] and extended by Sala et al. [9]; and the method is shown to be not only highly effective against asymmetric errors caused by charge leakage but also offer some protection against over-programming. In error-correcting schemes with dynamic threshold, the codes have constant composition, and in particular, the case when the codes are balanced (where the number of times a symbol appears in a codeword is as close as possible) was studied in detail by Zhou et al. and Sala et al. [8], [9]. ...

... Jiang et al. [3] addressed a q-ary balanced coding technique, called rank modulation, for circumventing the difficulties with flash memories having aging offset levels. Zhou et al. [4], Immink [5], and Sala et al. [6], [7] investigated constrained codes that enable dynamic reading thresholds in non-volatile memories. Immink & Weber [8] advocated Pearson-distance-based detection, which is intrinsically resistant to offset and gain mismatch. ...

... In order to guarantee unambiguous decoding in the absence of noise, the codebook used in conjunction with the modified Pearson distance must be judiciously chosen. Immink & Weber [8] showed that a codebook S, where if x ∈ S then x + c / ∈ S for all non-zero c ∈ R, can be unambiguously detected using (6). ...

The reliability of mass storage systems, such as optical data recording and non-volatile memory (Flash), is seriously hampered by uncertainty of the actual value of the offset (drift) or gain (amplitude) of the retrieved signal. The recently introduced minimum Pearson distance detection is immune to unknown offset or gain, but this virtue comes at the cost of a lessened noise margin at nominal channel conditions. We will present a novel hybrid detection method, where we combine the outputs of the minimum Euclidean distance and Pearson distance detectors so that we may trade detection robustness versus noise margin. We will compute the error performance of hybrid detection in the presence of unknown channel mismatch and additive noise.

... Jiang et al. [3] addressed a qary balanced coding technique, called rank modulation, for circumventing the difficulties with flash memories having aging offset levels. Zhou et al. [4], Sala et al. [5], and Immink [6] investigated the usage of balanced codes for Kees enabling 'dynamic' reading thresholds in non-volatile memories. Alternative detection methods, such as minimum Pearson distance detection, that are immune to offset and gain mismatch, have been presented in [7]. ...

... These specialize to constant weight codes in the binary case. It was shown in [7] that we may significantly reduce the number of distance computations (5) to the number of constant composition codes, K, that constitute the full set S. For q = 2, since S 1 consists of K = n constant weight codes, instead of 2 n for a full set only n computations are required. For a binary parity-check code the number of constant weight subsets equals (n + 1)/2 for n odd and n/2 for n even, which reduces the number of computations even more. ...

The error performance of optical storage and Non-Volatile Memory (Flash) is susceptible to unknown offset of the retrieved signal. Balanced codes offer immunity against unknown offset at the cost of a significant code redundancy, while minimum Pearson distance detection offers immunity with low-redundant codes at the price of lessened noise margin. We will present a hybrid detection method, where the distance measure is a weighted sum of the Euclidean and Pearson distance, so that the system designer may trade noise margin versus amount of immunity to unknown offset.

... The detector resilience to unknown mismatch by drift can be improved in various ways, for example, by employing coding techniques. Balanced codes [6]- [9] and composition check codes [10], [11], in conjunction with Slepian's optimal detection [12] offer excellent resilience in the face of channel mismatch on a block of symbols basis. These coding and signal processing techniques are often considered too expensive in terms of code redundancy and hardware, in particular when high-speed applications are considered. ...

... However, sinceâ andb are biased estimates of a and b, the above dynamic threshold detector loses error performance with respect to the ideal matched case, especially for larger codeword length n. The detector complexity scales linearly with n as its principal cost is the finding of the maximum and minimum of the n received symbol values using (9) and (10). Alternatively, detection based on the prior art Pearson distance, discussed in the next subsection, improves the error performance, but with mounting hardware requirements. ...

We report on the feasibility of k-means clustering techniques for the dynamic threshold detection of encoded q-ary symbols transmitted over a noisy channel with partially unknown channel parameters. We first assess the performance of k-means clustering technique without dedicated constrained coding. We apply constrained codes which allows a wider range of channel uncertainties so improving the detection reliability.

... For this reason, a nonuniform quantization scheme is adopted in [14], where the quantization levels are obtained at the intersecting region between two adjacent distribution functions by using constant ratio method. Alternative to enhanced precision, hard-decision based dynamic quantization schemes are also reported in [15], [16] where the read-voltage levels are adjusted according to the non-stationary behavior of flash channel. Another important work related to quantization design is presented in [17] in which the quantization levels are obtained by maximizing the mutual-information (MMI) between flash channel's input and output voltage signals. ...

The multi-level-cell (MLC) NAND flash channel exhibits nonstationary behavior over increasing program and erase (PE) cycles and data retention time. In this paper, an optimization scheme for adjusting the read (quantized) and write (verify) voltage levels to adapt to the nonstationary flash channel is presented. Using a model-based approach to represent the flash channel, incorporating the programming noise, random telegraph noise (RTN), data retention noise and cell-to-cell interference as major signal degradation components, the write-voltage levels are optimized by minimizing the channel error probability. Moreover, for selecting the quantization levels for the read-voltage to facilitate soft LDPC decoding, an entropy-based function is introduced by which the voltage erasure regions (error dominating regions) are controlled to produce the lowest bit/frame error probability. The proposed write and read voltage optimization schemes not only minimize the error probability throughout the operational lifetime of flash memory, but also improve the decoding convergence speed. Finally, to minimize the number of read-voltage quantization levels while ensuring LDPC decoder convergence, the extrinsic information transfer (EXIT) analysis is performed over the MLC flash channel.

... Rank modulation schemes address the writing asymmetry within memory where the relative charge among several cells is used to represent the information [5]. Moreover, dynamic threshold setting is employed in flash memories, where the threshold is not fixed, but rather recalculated at every read operation [6], [7]. These problems have become increasingly apparent in conventional designs due to the technology scaling [8] and integration requirements. ...

... While this approach identifies the crucial issue of read latency in adapting the read voltage thresholds, characterization data (see e.g., [Cai et al. 2013] or [Compagnoni et al. 2009]) suggests that the underlying cell threshold voltage distributions are actually highly asymmetric with exponential tails. A third approach is that of Sala et al. [2013], where balanced coding (or the storage of extra metadata) is proposed so that the number of times each MLC level has been programmed in a given word line is either fixed or known a priori. Then, given knowledge of the threshold voltages (levels) of the cells of the word line, it is possible to determine the optimal read voltage thresholds simply by sorting the sequence of levels. ...

NAND flash memory is not only the ubiquitous storagemedium in consumer applications but has also started to appear in enterprise storage systems as well. MLC and TLC flash technology made it possible to store multiple bits in the same silicon area as SLC, thus reducing the cost per amount of data stored. However, at current sub-20nm technology nodes, MLC flash devices fail to provide the levels of raw reliability, mainly cycling endurance, that are required by typical enterprise applications. Advanced signal processing and coding schemes are needed to improve the flash bit error rate and thus elevate the device reliability to the desired level. In this article, we report on the use of adaptive voltage thresholds and cell-to-cell interference cancellation in the read operation of NAND flash devices. We discuss how the optimal read voltage thresholds can be determined and assess the benefit of cancelling cell-to-cell interference in terms of cycling endurance, data retention, and resilience to read disturb.

... In a 4 bit memory cell (16 current levels), for example, a one order of magnitude difference between each level is not achievable, because this would mean a switching ratio as high as 10 15 . Importantly, all methods where a high switching ratio is simply based on a threshold voltage shift (that is, not characterized by a change in charge carrier mobility or current), with the 'read voltage' within a threshold voltage window, are prone to data loss and incorrect reading of the levels in multilevel storage 21,22 . ...

Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices.

... Specifically, balanced codes, where codewords have an equal number (or a fixed ratio) of zeros and ones, have been proposed and used to counter the detrimental effects of charge offset uncertainty [7]. Zhou et al. [8] and Sala et al. [9] investigated constrained codes that enable dynamic reading thresholds in nonvolatile memories such as Flash. Immink and Weber [10] advocated a new detection method based on the Pearson distance, which is intrinsically resistant to offset uncertainty. ...

Flash, already one of the dominant forms of data storage for mobile consumer devices, such as smartphones and media players, is experiencing explosive growth in cloud and enterprise applications. Flash devices offer very high access speeds, low power consumption, and physical resiliency. Our goal in this article is to provide a high-level overview of error correction for Flash. We will begin by discussing Flash functionality and design. We will introduce the nature of Flash deficiencies. Afterwards, we describe the basics of ECCs. We discuss BCH and LDPC codes in particular and wrap up the article with more directions for Flash coding.

... In other words, since a minimum Pearson detector cannot distinguish between the wordsx andŷ = c 1x + c 2 , the codewords must be taken from a codebook S ⊆ Q n that guarantees unambiguous detection with the Pearson distance metric (5). It is a well-known property of the Pearson correlation coefficient, ρ x,x , that ...

The Pearson distance has been advocated for improving the error performance
of noisy channels with unknown gain and offset. The Pearson distance can only
fruitfully be used for sets of $q$-ary codewords, called Pearson codes, that
satisfy specific properties. We will analyze constructions and properties of
optimal Pearson codes. We will compare the redundancy of optimal Pearson codes
with the redundancy of prior art $T$-constrained codes, which consist of
$q$-ary sequences in which $T$ pre-determined reference symbols appear at least
once. In particular, it will be shown that for $q\le 3$ the $2$-constrained
codes are optimal Pearson codes, while for $q\ge 4$ these codes are not
optimal.

... These works were motivated by different considerations -the former aiming to increase the number of possible re-writes between block erasures, and the latter focusing on the advantages of multipermutation coding with respect to cell leakage, over-injection issues, and charge fluctuations. In addition, multipermutation codes were also recently reported for the Chebyshev distance in [18], [19] and for the Kendall τ distance in [20], [21]. ...

We present a multiset rank modulation scheme capable of correcting translocation errors, motivated by the fact that compared to permutation codes, multipermutation codes offer higher rates and longer block lengths. We show that the appropriate distance measure for code construction is the Ulam metric applied to equivalence classes of permutations, where each permutation class corresponds to a multipermutation. The paper includes a study of multipermutation codes in the Hamming metric, also known as constant composition codes, due to their use in constructing multipermutation codes in the Ulam metric. We derive bounds on the size of multipermutation codes in both the Ulam metric and the Hamming metric, compute their capacity, and present constructions for codes in the Ulam metric based on permutation interleaving, semi-Latin squares, and resolvable Steiner systems.

... Most of the existing literature on optimizing the read thresholds for NAND flash assumes that prior information on the noise is available (e.g., [6], [7], [8], [9], [10]). Some methods, such at the one proposed by Wang et al. in [11], assume complete knowledge of the noise and choose the read thresholds so as to maximize the mutual information between the values written and read, while others attempt to predict the noise from the number of program-erase (PE) cycles and then optimize the read thresholds based on that prediction. ...

A primary source of increased read time on NAND flash comes from the fact that in the presence of noise, the flash medium must be read several times using different read threshold voltages for the decoder to succeed. This paper proposes an algorithm that uses a limited number of re-reads to characterize the noise distribution and recover the stored information. Both hard and soft decoding are considered. For hard decoding, the paper attempts to find a read threshold minimizing bit-error-rate (BER) and derives an expression for the resulting codeword-error-rate. For soft decoding, it shows that minimizing BER and minimizing codeword-error-rate are competing objectives in the presence of a limited number of allowed re-reads, and proposes a trade-off between the two. The proposed method does not require any prior knowledge about the noise distribution, but can take advantage of such information when it is available. Each read threshold is chosen based on the results of previous reads, following an optimal policy derived through a dynamic programming backward recursion. The method and results are studied from the perspective of an SLC Flash memory with Gaussian noise for each level but the paper explains how the method could be extended to other scenarios.

... Modern Flash storage solutions employ channel codes [1], [2] to increase reliability, but this approach alone cannot effectively counteract the channel capacity decrease caused by degradation due to recursively program and erase the cells. Signal processing methods such as Dynamic Voltage Allocation (DVA) [3] and Dynamic Threshold Assignment (DTA) [4] actively mitigate channel degradation. Effective decoding of channel codes, possible selection of channel code rate, and adaptive signal processing such as DVA and DTA require channel state information. ...

Current generation Flash devices experience significant read-channel
degradation from damage to the oxide layer during program and erase operations.
Information about the read-channel degradation drives advanced signal
processing methods in Flash to mitigate its effect. In this context, channel
estimation must be ongoing since channel degradation evolves over time and as a
function of the number of program/erase (P/E) cycles. This paper proposes a
framework for ongoing model-based channel estimation using limited channel
measurements (reads). This paper uses a channel model characterizing
degradation resulting from retention time and the amount of charge programmed
and erased. For channel histogram measurements, bin selection to achieve
approximately equal-probability bins yields a good approximation to the
original distribution using only ten bins (i.e. nine reads). With the channel
model and binning strategy in place, this paper explores candidate numerical
least squares algorithms and ultimately demonstrates the effectiveness of the
Levenberg-Marquardt algorithm which provides both speed and accuracy.

... Based on the acquired information from decoding output, dynamic threshold techniques have been proposed to adjust read reference voltages based on metadata implementation and balanced-codes approach [22], [23]. However, the dynamic threshold schemes require to store highly reliable metadata and impose restrictions on the application of arbitrary error-correcting codes. ...

To achieve a low error rate of NAND flash memory, reliable reference voltages should be updated based on the accurate knowledge of program/erase (P/E) cycles and retention time, because those severely distort the threshold voltage distribution of memory cell. Due to the sensitivity to the temperature, however, a flash memory controller is unable to acquire the exact knowledge of retention time, meaning that it is challenging to estimate accurate read reference voltages in practice. In this article, we propose a novel machine-learning-based read reference voltage estimation framework for the NAND flash memory systems without the knowledge of retention time. To establish an unknown input-output relation of the estimation model, we derive input features by sensing and decoding memory cells in the minimum read unit. In order to define the relation between unlabeled input features and a pre-assigned class label, namely label read reference voltages, we propose three mapping functions: 1) k -nearest neighbors-based, 2) nearest-centroid-based, and 3) polynomial regression-based read reference voltage estimators. For the proposed estimation schemes, we analyze that the storage overhead and computational complexity are increasing function of the exploited feature dimension. Accordingly, we propose a feature selection (or dimension reduction) algorithm to select the minimum dimension and corresponding features to reduce the overhead and complexity while maintaining high estimation accuracy. Based on extensive numerical analysis, we validate that the derived features successfully replace unknown knowledge of retention time, and the proposed feature selection algorithm precisely adjusts the trade-off between overhead/complexity and estimation accuracy. Furthermore, the simulation and analysis results show that the proposed framework not only outperforms the conventional estimation schemes but also achieves the near-optimal frame error rate while sustaining low latency performance.

... Philipp et al. [49] considered NVM asymmetries through clustering rather than secondary indexes and used heap organization of block contents to save unnecessary writes from DRAM to NVM. Sala et al. [54] proposed to perform a single read with a dynamic threshold to adapt to time-varying channel degradation for resolving NVM endurance problems caused by asymmetries. NVM is also widely used in building general purpose storage systems [39], storing deep learning models [25], and graph analysis [43]. ...

New memory technologies are blurring the previously distinctive performance characteristics of adjacent layers in the memory hierarchy. No longer are such layers orders of magnitude different in request latency or capacity. Beyond the traditional single-layer view of caching, we now must re-cast the problem as a data placement challenge: which data should be cached in faster memory if it could instead be served directly from slower memory?
We present Chopt, an offline algorithm for data placement across multiple tiers of memory with asymmetric read and write costs. We show that Chopt is optimal and can therefore serve as the upper bound of performance gain for any data placement algorithm. We also demonstrate an approximation of Chopt which makes its execution time for long traces practical using spatial sampling of requests incurring a small 0.2% average error on representative workloads at a sampling ratio of 1%. Our evaluation of Chopt on more than 30 production traces and benchmarks shows that optimal data placement decisions could improve average request latency by 8.2%-44.8% when compared with the long-established gold standard: Belady and Mattson's offline, evict-farthest-in-the-future optimal algorithms. Our results identify substantial improvement opportunities for future online memory management research.

... To ensure MLC operation, writing of data generally requires going into a few program-verify iterations [14], which in-turn calls for extra circuits, e.g., error correcting code (ECC) [15] and redundancy [16][17], increase the overhead on peripheral circuits. Indispensable complex programming cycles can slow down programming speed, increases operation power and might induce long-term reliability issues on data integrity [18]. The read speed of single-level cells (SLC) and MLC devices are almost identical while MLC is almost 3~4 times slower in terms of write performance as compared to SLC [19]. ...

A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell with a narrow-bridging line between two coupling capacitors promotes a localized charging effect at the electron tunneling site, leading to clamping of threshold voltage states. Through this mechanism, the new multi time programmable (MTP) cells exhibit tight threshold voltage distributions for multi-level cells (MLC) operations. Improved cycling reliability and one-shot multi-level programming has been fully demonstrated in this work.

... Alternatively, coding techniques can be applied to alleviate the detection in case of channel mismatch. Specifically balanced codes [5], [6], [7] and composition check codes [8], [9] preferably in conjunction with Slepian's optimal detection [10] offer resilience in the face of channel mismatch. These coding methods are often considered too expensive in terms of coding hardware and redundancy, specifically when high-speed applications are considered. ...

We investigate machine learning based on clustering techniques that are suitable for the detection of encoded strings of q-ary symbols transmitted over a noisy channel with partially unknown characteristics. We consider the detection of the q-ary data as a classification problem, where objects are recognized from a corrupted vector, which is obtained by an unknown corruption process. We first evaluate the error performance of k-means clustering technique without constrained coding. Secondly, we apply constrained codes that create an environment that improves the detection reliability and it allows a wider range of channel uncertainties.

... Philipp et al. [49] considered NVM asymmetries through clustering rather than secondary indexes and used heap organization of block contents to save unnecessary writes from DRAM to NVM. Sala et al. [54] proposed to perform a single read with a dynamic threshold to adapt to time-varying channel degradation for resolving NVM endurance problems caused by asymmetries. NVM is also widely used in building general purpose storage systems [39], storing deep learning models [25], and graph analysis [43]. ...

... Philipp et al. [49] considered NVM asymmetries through clustering rather than secondary indexes and used heap organization of block contents to save unnecessary writes from DRAM to NVM. Sala et al. [54] proposed to perform a single read with a dynamic threshold to adapt to time-varying channel degradation for resolving NVM endurance problems caused by asymmetries. NVM is also widely used in building general purpose storage systems [39], storing deep learning models [25], and graph analysis [43]. ...

New memory technologies are blurring the previously distinctive performance characteristics of adjacent layers in the memory hierarchy. No longer are such layers orders of magnitude different in request latency or capacity. Beyond the traditional single-layer view of caching, we now must re-cast the problem as a data placement challenge: which data should be cached in faster memory if it could instead be served directly from slower memory?
We present CHOPT, an offline algorithm for data placement across multiple tiers of memory with asymmetric read and write costs. We show that CHOPT is optimal and can therefore serve as the upper bound of performance gain for any data placement algorithm.
We also demonstrate an approximation of CHOPT which makes its execution time for long traces practical using spatial sampling of requests incurring a small 0.2% average error on representative workloads at a sampling ratio of 1%. Our evaluation of CHOPT on more than 30 production traces and benchmarks shows that optimal data placement decisions could improve average request latency by 8.2%-44.8% when compared with the long-established gold standard: Belady and Mattson's offline, evict-farthest-in-the-future optimal algorithms. Our results identify substantial improvement opportunities for future online memory management research.

... Since this is done in software this method has the advantage of tight integration with ECC methods, e.g. those described in [2,3]. The software defined nature can allow greater flexibility for allocating cells to almost arbitrary digital states. ...

We discuss a topological method of storing and retrieving information from flash memory. We first present a sensing method where the threshold voltage level, as represented by a sensing time, is extracted in one sensing cycle. The sense time distribution from one set of flash cells, e.g. one physical row, is then processed in software to decode the digital state of each cell. The decoding method uses topological constraints but no rigid or predetermined voltage thresholds to digitize the distribution. The software defined nature of the topologically defined flash (TDF) allows greater flexibility for allocating cells to arbitrary number of digital states.

Multi-permutations and in particular permutations appear in various applications in an information theory. New applications, such as rank modulation for flash memories, have suggested the need to consider error-correcting codes for multi-permutations. In this paper, we study systematic error-correcting codes for multi-permutations in general and for permutations in particular. For a given number of information symbols k, and for any integer t, we present a construction of (k+r,k)systematic t-error-correcting codes, for permutations of length k+r, where the number of redundancy symbols r is relatively small. In particular, for a given t and for sufficiently large k, we obtain r=t+1, while a lower bound on the number of redundancy symbols is shown to be t. The same construction is also applied to obtain related systematic error-correcting codes for any types of multi-permutations.

Codes based on multiset permutations, or multipermutations, have attracted recent attention due to their applications to non-volatile memories. Most of the literature studying multipermutations is focused on codes capable of correcting errors in the Kendall tau and Ulam metrics. In this work, we make a first effort towards studying synchronization errors over multipermutations. We begin by defining the concept of multipermutation deletions. We characterize the nature and effects of such errors. We provide an expression for the number of multipermutations formed by a single multipermutation deletion. Finally, we introduce code constructions which correct one or more multipermutation deletions.

We consider noisy communications and storage systems that are hampered by varying offset of unknown magnitude such as low-frequency signals of unknown amplitude added to the sent signal. We study and analyze a new detection method whose error performance is independent of both unknown base offset and offset’s slew rate. The new method requires, for a codeword length n ≥ 12, less than 1.5 dB more noise margin than Euclidean distance detection. The relationship with constrained codes based on mass-centered codewords and the new detection method is discussed.

A primary source of increased read time on nand flash comes from the fact that, in the presence of noise, the flash medium must be read several times using different read threshold voltages for the decoder to succeed. This paper proposes an algorithm that uses a limited number of rereads to characterize the noise distribution and recover the stored information. Both hard and soft decoding are considered. For hard decoding, this paper attempts to find a read threshold minimizing bit error rate (BER) and derives an expression for the resulting codeword error rate. For soft decoding, it shows that minimizing BER and minimizing codeword error rate are competing objectives in the presence of a limited number of allowed rereads, and proposes a tradeoff between the two. The proposed method does not require any prior knowledge about the noise distribution but can take advantage of such information when it is available. Each read threshold is chosen based on the results of previous reads, following an optimal policy derived through a dynamic programming backward recursion. The method and results are studied from the perspective of an SLC Flash memory with Gaussian noise, but this paper explains how the method could be extended to other scenarios.

Motivated by the rank modulation scheme, a recent study by Sala and Dolecek explored the idea of constraint codes for permutations. The constraint studied by them is inherited by the inter-cell interference phenomenon in flash memories, where high-level cells can inadvertently increase the level of lowlevel cells. A permutation s σ Sn satisfies the single-neighbor k-constraint if |δ(i + 1)-δ(i)| = k for all 1 = i = n-1. In this paper, this model is extended into two constraints. A permutation s σ Sn satisfies the two-neighbor k-constraint if for all 2 = i = n-1, |δ(i)-δ(i-1)| = k or |δ(i + 1)-δ(i)| = k, and it satisfies the asymmetric two-neighbor k-constraint if for all 2 = i = n-1, δ(i-1)-δ(i) < k or δ(i + 1)-s(i) < k. We show that the capacity of the first constraint is (1 + e)/2 in case that k = θ(ne) and the capacity of the second constraint is 1 regardless for any positive k. We also extend our results and study the capacity of these two constraints combined with error-correcting codes in the Kendall t-metric.

The practical NAND flash memory suffers from various non-stationary noises that are difficult to be predicted. For example, the data retention noise induced channel offset is unknown during the readback process, and hence severely affects the reliability of data recovery from the memory cell. In this paper, we first propose a novel recurrent neural network (RNN)-based detector to effectively detect the data stored in the multi-level-cell (MLC) flash memory without the prior knowledge of the channel. However, compared with the conventional threshold detector, the proposed RNN detector introduces much longer read latency and more power consumption. To tackle this problem, we further propose an RNN-aided (RNNA) dynamic threshold detector, whose detection thresholds can be derived based on the outputs of the RNN detector. We thus only need to activate the RNN detector periodically when the system is idle. Moreover, to enable soft-decision decoding of error-correction codes, we first show how to obtain more read thresholds based on the hard-decision read thresholds derived from the RNN detector. We then propose integer-based reliability mappings based on the designed read thresholds, which can generate the soft information of the channel. Finally, we propose to apply density evolution (DE) combined with the differential evolution algorithm to optimize the read thresholds for low-density parity-check (LDPC) coded flash memory channels. Computer simulation results demonstrate the effectiveness of our proposed RNNA dynamic read thresholds design, for both the uncoded and LDPC-coded flash memory channels, without any prior knowledge of the channel.

This thesis explored how, by blending of materials with different electrical characteristics, it is possible to fabricate transistors with new or improved performances. First, organic field-effect transistors based on a single oligothiophene, DH4T, were fabricated and optimized until the measured mobility was superior to that observed in vacuum deposited films. This was achieved through careful tuning of the interfaces using self-assembled monolayers and by strong control of the solvent- evaporation rate. P-type polymers were blended with an n-type polymer. Each resulting solution was used for the fabrication of ambipolar field-effect transistors. These devices were characterized and it was found that for each pair of p- and n-type polymers, a transistor with balanced mobilities and high Ion/Ioff could be fabricated. Finally field-effect transistors based on a blend of P3HT and a photoswitchable diarylethene (DAE-Me) were fabricated. The current was measured during and between irradiations and it was demonstrated that a non-volatile multilevel memory could be fabricated.

In this chapter, we discuss advanced error-correcting code techniques. In particular, we focus on two complementary strategies, asymmetric algebraic codes and non-binary low-density parity-check (LDPC)
codes. Both of these techniques are inspired by traditional coding theory; however, in both cases, we depart from classical approaches and develop new concepts specifically designed to take advantage of inherent channel characteristics that describe non-volatile memories.

This paper proposes tailoring image encoding for an approximate storage substrate. We demonstrate that indiscriminately storing encoded images in approximate memory generates unacceptable and uncontrollable quality degradation. The key finding is that errors in the encoded bit streams have non-uniform impact on the decoded image quality. We develop a methodology to determine the relative importance of encoded bits and store them in an approximate storage substrate. The storage cells are optimized to reduce error rate via biasing and are tuned to meet the desired reliability requirement via selective error correction. In a case study with the progressive transform codec (PTC), a precursor to JPEG XR, the proposed approximate image storage system exhibits a 2.7x increase in density of pixels per silicon volume under bounded error rates, and this achievement is additive to the storage savings of PTC compression.

This paper proposes tailoring image encoding for an approximate storage substrate. We demonstrate that indiscriminately storing encoded images in approximate memory generates unacceptable and uncontrollable quality degradation. The key finding is that errors in the encoded bit streams have non-uniform impact on the decoded image quality. We develop a methodology to determine the relative importance of encoded bits and store them in an approximate storage substrate. The storage cells are optimized to reduce error rate via biasing and are tuned to meet the desired reliability requirement via selective error correction. In a case study with the progressive transform codec (PTC), a precursor to JPEG XR, the proposed approximate image storage system exhibits a 2.7x increase in density of pixels per silicon volume under bounded error rates, and this achievement is additive to the storage savings of PTC compression.

This paper proposes tailoring image encoding for an approximate storage substrate. We demonstrate that indiscriminately storing encoded images in approximate memory generates unacceptable and uncontrollable quality degradation. The key finding is that errors in the encoded bit streams have non-uniform impact on the decoded image quality. We develop a methodology to determine the relative importance of encoded bits and store them in an approximate storage substrate. The storage cells are optimized to reduce error rate via biasing and are tuned to meet the desired reliability requirement via selective error correction. In a case study with the progressive transform codec (PTC), a precursor to JPEG XR, the proposed approximate image storage system exhibits a 2.7x increase in density of pixels per silicon volume under bounded error rates, and this achievement is additive to the storage savings of PTC compression.

Non-volatile memories (NVMs) have emerged as the primary replacement of hard-disk drives for a variety of storage applications, including personal electronics, mobile computing, intelligent vehicles, enterprise storage, data warehousing, and data-intensive computing systems. Channel coding schemes are a necessary tool for ensuring target reliability and performance of NVMs. However, due to operational asymmetries in NVMs, conventional coding approaches - commonly based on designing for the Hamming metric - no longer apply. Given the immediate need for practical solutions and the shortfalls of existing methods, the fast-growing discipline of coding for NVMs has resulted in several key innovations that not only answer the needs of modern storage systems but also directly contribute to the analytical toolbox of coding theory at large. This monograph discusses recent advances in coding for NVMs, covering topics such as error correction coding based on novel algebraic and graph-based methods, write-once memory (WOM) codes, rank modulation, and constrained coding. Our goal in this monograph is multifold: to illuminate the advantages - as well as challenges - associated with modern NVMs, to present a succinct overview of several exciting recent developments in coding for memories, and, by presenting numerous potential research directions, to inspire other researchers to contribute to this timely and thriving discipline.

Codes over permutations and multipermutations have received considerable attention since the rank modulation scheme is presented for flash memories. Deletions in multipermutations often occur due to data synchronization errors. Based on the interleaving of several singledeletion- correcting multipermutation codes, we present a construction of multipermutation codes for correcting a burst of at most t deletions with shift magnitude one for t ≥ 2. The proposed construction is proved with including an efficient decoding method. A calculation example is provided to validate the construction and its decoding method. © 2018 The Institute of Electronics, Information and Communication Engineers.

To recover from the retention noise induced errors in NAND flash memory, a retention-aware belief-propagation (RABP) decoding scheme for low-density parity-check codes is introduced. The RABP is a two-stage decoding scheme in which the memory cell's charge-loss effect is systematically compensated. In RABP decoding, instead of read retries for data recovery, the probable victim cells are first determined with the help of read-back voltage signal and the decoded bit decisions. Then, for such suspected victim cells, their log-likelihood-ratio regions are modified in such a way as to absorb the effect of cell voltage downshift caused by retention noise, and then a second round of belief-propagation (BP) decoding is performed afresh, often with decoding failure recovery. Furthermore, leveraging on the RABP decoded bit-error pattern, an RABP assisted channel update (RABP-CU) algorithm is proposed which re-estimates the latest cell voltage distribution parameters without incurring new memory sensing operations. This is achieved by minimizing the mean squared error between the measured and predicted bit error/erasure values. Through simulations, it is shown that the RABP decoder increases the retention time limit by up to 70% compared with single round of BP decoding. The proposed RABP-CU algorithm further extends the data retention time.

We consider rank modulation codes for flash memories that allow for handling arbitrary charge drop errors. Unlike classical rank modulation codes used for correcting errors that manifest themselves as swaps of two adjacently ranked elements, the proposed translocation codes account for more general forms of errors that arise in storage systems. Translocations represent a natural extension of the notion of adjacent transpositions and as such may be analyzed using related concepts in combinatorics and rank modulation coding. Our results include deriving the asymptotic capacity of translocation rank codes, construction techniques for asymptotically good codes and a simple decoding algorithm.

This paper presents a practical writing/reading scheme in nonvolatile
memories, called balanced modulation, for minimizing the asymmetric component
of errors. The main idea is to encode data using a balanced error-correcting
code. When reading information from a block, it adjusts the reading threshold
such that the resulting word is also balanced or approximately balanced.
Balanced modulation has suboptimal performance for any cell-level distribution
and it can be easily implemented in the current systems of nonvolatile
memories. Furthermore, we studied the construction of balanced error-correcting
codes, in particular, balanced LDPC codes. It has very efficient encoding and
decoding algorithms, and it is more efficient than prior construction of
balanced error-correcting codes.

In NAND Flash memory featuring multi-level cells (MLC), the width of threshold voltage distributions about their nominal values affects the permissible number of levels and thus storage capacity. Unfortunately, inter-cell coupling causes a cell's charge to affect its neighbors' sensed threshold voltage, resulting in an apparent broadening of these distributions. We present a novel approach, whereby the data written to Flash is constrained, e.g., by forbidding certain adjacent-cell level combinations, so as to limit the maximum voltage shift and thus narrow the distributions. To this end, we present a new family of constrained codes. Our technique can serve for capacity enhancement (more levels) or for improving endurance, retention and bit error rate (wider guard bands between adjacent levels). It may also be combined with various programming order techniques that mitigate the inter-cell coupling effects and with decoding techniques that compensate for them.

Flash memory is a non-volatile computer memory comprised of blocks of cells, wherein each cell can take on q different values or levels. While increasing the cell level is easy, reducing the level of a cell can be accomplished only by erasing an entire block. Since block erasures are highly undesirable, coding schemes - known as floating codes or flash codes - have been designed in order to maximize the number of times that information stored in a flash memory can be written (and re-written) prior to incurring a block erasure. An (n, k, t)<sub>q</sub> flash code Â¿ is a coding scheme for storing k information bits in n cells in such a way that any sequence of up to t writes (where a write is a transition 0 Â¿ 1 or 1 Â¿ 0 in any one of the k bits) can be accommodated without a block erasure. The total number of available level transitions in n cells is n(q-1), and the write deficiency of Â¿, defined as Â¿(Â¿) = n(q-1)-t, is a measure of how close the code comes to perfectly utilizing all these transitions. For k > 6 and large n, the best previously known construction of flash codes achieves a write defficiency of O(qk<sup>2</sup>). On the other hand, the best known lower bound on write deficiency is Â¿(qk). In this paper, we present a new construction of flash codes that approaches this lower bound to within a factor logarithmic in k. To this end, we first improve upon the so-called Â¿indexedÂ¿ flash codes, due to Jiang and Bruck, by eliminating the need for index cells in the Jiang-Bruck construction. Next, we further increase the number of writes by introducing a new multi-stage (recursive) indexing scheme. We then show that the write defficiency of the resulting flash codes is O(qk log k) if q Â¿ log<sub>2</sub> k, and at most O(k log<sup>2</sup> k) otherwise.

We explore a novel data representation scheme for multi-level flash memory cells, in which a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The only allowed charge-placement mechanism is a "push-to-the-top" operation which takes a single cell of the set and makes it the top-charged cell. The resulting scheme eliminates the need for discrete cell levels, as well as overshoot errors, when programming cells.
We present unrestricted Gray codes spanning all possible n-cell states and using only "push-to-the-top" operations, and also construct balanced Gray codes. We also investigate optimal rewriting schemes for translating arbitrary input alphabet into n-cell states which minimize the number of programming operations.

Memories whose storage cells transit irreversibly between states have been common since the start of the data storage technology. In recent years, flash memories and other non-volatile memories based on floating-gate cells have become a very important family of such memories. We model them by the Write Asymmetric Memory (WAM), a memory where each cell is in one of q states – state 0, 1, ... , q-1 – and can only transit from a lower state to a higher state. Data stored in a WAM can be rewritten by shifting the cells to higher states. Since the state transition is irreversible, the number of times of rewriting is limited. When multiple variables are stored in a WAM, we study codes, which we call floating codes, that maximize the total number of times the variables can be written and rewritten.
In this paper, we present several families of floating codes
that either are optimal, or approach optimality as the codes get longer. We also present bounds to the performance of general floating codes. The results show that floating codes can integrate the rewriting capabilities of different variables to a surprisingly high degree.

Rank modulation is a way of encoding information to correct errors in flash memory devices as well as impulse noise in transmission lines. Modeling rank modulation involves construction of packings of the space of permutations equipped with the Kendall tau distance. We present several general constructions of codes in permutations that cover a broad range of code parameters. In particular, we show that a code that corrects Hamming errors can be used to construct a code for correcting Kendall errors. For instance, from BCH codes we obtain codes correcting t Kendall errors in n memory cells that support the order of n!/ log<sup>t</sup> n! messages, for any t = 1, 2, .... We also construct families of codes that correct a number of errors that grows with n at varying rates, from Θ(n) to Θ(n<sup>2</sup>).

Phase-change memory (PCM) is an emerging nonvolatile memory technology that promises very high performance.
It currently uses discrete cell levels to represent data, controlled
by a single amorphous/crystalline domain in a cell. To improve
data density, more levels per cell are needed. There exist a number of challenges, including cell programming noise, drifting of
cell levels, and the high power requirement for cell programming.
In this paper, we present a new cell structure called patterned cell, and explore its data representation schemes. Multiple
domains per cell are used, and their connectivity is used to
store data. We analyze its storage capacity, and study its error-correction capability and the construction of error-control codes.

Predetermined fixed thresholds are commonly used in nonvolatile memories for reading binary sequences, but they usually result in significant asymmetric errors after a long duration, due to voltage or resistance drift. This motivates us to construct error-correcting schemes with dynamic reading thresholds, so that the asymmetric component of errors are minimized. In this paper, we discuss how to select dynamic reading thresholds without knowing cell level distributions, and present several error-correcting schemes. Analysis based on Gaussian noise models reveals that bit error probabilities can be significantly reduced by using dynamic thresholds instead of fixed thresholds, hence leading to a higher information rate.

A relatively new model of error correction is the limited magnitude error model. That is, it is assumed that the absolute difference between the sent and received symbols is bounded above by a certain value l . In this paper, we propose systematic codes for asymmetric limited magnitude channels that are able to correct a single error. We also show how this construction can be slightly modified to design codes that can correct a single symmetric error of limited magnitude. The designed codes achieve higher code rates than single error correcting codes previously given in the literature.

We study error-correcting codes for permutations under the infinity norm, motivated by a novel storage scheme for flash memories called rank modulation. In this scheme, a set of n flash cells are combined to create a single virtual multilevel cell. Information is stored in the permutation induced by the cell charge levels. Spike errors, which are characterized by a limited-magnitude change in cell charge levels, correspond to a low-distance change under the infinity norm. We define codes protecting against spike errors, called limited-magnitude rank-modulation codes (LMRM codes), and present several constructions for these codes, some resulting in optimal codes. These codes admit simple recursive, and sometimes direct, encoding and decoding procedures. We also provide lower and upper bounds on the maximal size of LMRM codes both in the general case, and in the case where the codes form a subgroup of the symmetric group. In the asymptotic analysis, the codes we construct outperform the Gilbert-Varshamov-like bound estimate.

We investigate error-correcting codes for a novel storage technology for flash memories, the rank-modulation scheme. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, overcomes overshoot errors when programming cells (a serious problem that reduces the writing speed), and mitigates the problem of asymmetric errors.
In this paper we study the properties of error-correcting codes for charge-constrained errors in the rank-modulation scheme. In this error model the number of errors corresponds to the minimal number of adjacent transpositions required to change a given stored permutation to another erroneous one – a distance measure known as Kendall's τ-distance.
We show bounds on the size of such codes, and use metric-embedding techniques to give constructions which translate a
wealth of knowledge of binary codes in the Hamming metric as well as q-ary codes in the Lee metric, to codes over permutations in Kendall's τ-metric. Specifically, the one-error-correcting codes we construct are at least half the ball-packing upper bound.

We consider codes over the alphabet Q={0,1,..,q-1}intended for the control of unidirectional errors of level l. That is, the transmission channel is such that the received word cannot contain both a component larger than the transmitted one and a component smaller than the transmitted one. Moreover, the absolute value of the difference between a transmitted component and its received version is at most l. We introduce and study q-ary codes capable of correcting all unidirectional errors of level l. Lower and upper bounds for the maximal size of those codes are presented. We also study codes for this aim that are defined by a single equation on the codeword coordinates(similar to the Varshamov-Tenengolts codes for correcting binary asymmetric errors). We finally consider the problem of detecting all unidirectional errors of level l.

Several physical effects that limit the reliability and
performance of Multilevel Flash Memories induce errors that
have low magnitudes and are dominantly asymmetric. This paper studies block codes for asymmetric limited-magnitude errors over q-ary channels. We propose code constructions and bounds for such channels when the number of errors is bounded by t and the error magnitudes are bounded by ࡁ. The constructions utilize known codes for symmetric errors, over small alphabets, to protect large-alphabet symbols from asymmetric limited-magnitude errors. The encoding and decoding of these codes are performed over the small alphabet whose size depends only on the maximum error magnitude and is independent of the alphabet size of the outer code. Moreover, the size of the codes is shown
to exceed the sizes of known codes (for related error models), and asymptotic rate-optimality results are proved. Extensions of the construction are proposed to accommodate variations on the error model and to include systematic codes as a benefit to practical implementation.

A detailed investigation of the reliability aspects in nonvolatile phase-change memories (PCM) is presented, covering the basic aspects related to high density array NVM, i.e., data retention, endurance, program and read disturbs. The data retention capabilities and the endurance characteristics of single PCM cells are analyzed, showing that data can be stored for 10 years at 110°C and that a resistance difference of two order of magnitude between the cell states can be maintained for more than 10<sup>11</sup> programming cycles. The main mechanisms responsible for instabilities just before failure as well as for final device breakdown are also discussed. Finally, the impact of read and program disturbs are clearly assessed, showing with experimental data and simulated results that the crystallization induced during the cell read out and the thermal cross-talk due to adjacent bits programming do not affect the retention capabilities of the PCM cells.

This paper introduces a new combinatorial construction for q-ary constant-weight codes which yields several families of optimal codes and asymptotically optimal codes. The construction reveals intimate connection between q-ary constant-weight codes and sets of pairwise disjoint combinatorial designs of various types

This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

This paper gives some new theory and design of codes capable of correcting/detecting errors measured under the Lee distance defined over m-ary words, m ∈ IN. Based on the elementary symmetric functions (instead of the power sums), a key equation is derived which can be used to design new symmetric (or, asymmetric) error control algorithms for some new and already known error control codes for the Lee metric. In particular, it is shown that if K is any field with characteristic char(K) = p, p odd, and u, h, n, m = uph, t ∈ IN are such that n ≤ (|K| - 1)/2 and t ≤ (ph - 1)/2 then there exist m-ary codes C of length n and cardinality |C| ≥ mn/|K|t which are capable of, say, correcting t symmetric errors (i. e., the minimum Lee distance of C is dLee (C) ≥ 2t + 1) with t steps of the Extended Euclidean Algorithm. Furthermore, if t ≤ (p - 1)/2 then some of these codes are (essentially) linear and, hence, easy to encode.

Based on the elementary symmetric functions, this paper gives a new wide class of Goppa like codes capable of correcting/detecting errors measured under the (symmetric) L1 distance defined over the m-ary words, 2 ≤ m ≤ +∞. All these codes can be efficiently decoded by algebraic means with the Extended Euclidean Algorithm (EEA). In particular it is shown that if K is any field with characteristic char(K) ≠ 2, m ϵ IN U {+∞} and n, t ϵ IN then there exist m-ary codes C of length n ≤ (|K|- 1)/2 and cardinality |C| ≥ mn/|K|t which are capable of, say, correcting t errors (i. e., the minimum L1 distance of C is dL1 (C) ≥ 2t + 1) with t steps of EEA. Also, if K is a finite field and 2t + 1 ≤ char(K) ≠ 2 then some of these codes are (essentially) linear and, hence, easy to encode.

Codes that correct limited-magnitude errors for multi-level cell nonvolatile memories, such as flash memories and phase-change memories, have received interest in recent years. This work proposes a new coding scheme that generalizes a known result [2] and works for arbitrary error distributions. In this scheme, every cell's discrete level ℓ is mapped to its binary representation (bm-1, ..., b1,b0), where the m bits belong to m different error-correcting codes. The error ε in a cell is mapped to its binary representation (em-1, ..., e1, e0), and the codes are designed such that every error bit ei only affects the codeword containing the data bit bi. The m codewords are decoded sequentially to correct the bit-errors e0,e1, ..., em-1 in order. The scheme can be generalized to many more numeral systems for cell levels and errors, optimized cell-level labelings, and any number of cell levels. It can be applied not only to storage but also to amplitude-modulation communication systems.

Balanced bipolar codes consist of sequences in which the symbols '-1' and '+1' appear equally often. Several generalizations to larger alphabets have been considered in literature. For example, for the q-ary alphabet {-q + 1, -q + 3, ..., q - 1}, known concepts are symbol balancing, i.e., all alphabet symbols appear equally often in each codeword, and charge balancing, i.e., the symbol sum in each codeword equals zero. These notions are equivalent for the bipolar case, but not for q > 2. In this paper, a third perspective is introduced, called polarity balancing, where the number of positive symbols equals the number of negative symbols in each codeword. The minimum redundancy of such codes is determined and a generalization of Knuth's celebrated bipolar balancing algorithm is proposed.

Let S be a subset of a group G. We call S a Sidon subset of the first (second) kind, if for any x, y, z, w ∈ S of which at least 3 are different, xy ≠ zw (xy⁻¹ ≠ zw⁻¹, resp.). (For abelian groups, the two notions coincide.) If G has a Sidon subset of the second kind with n elements then every n-vertex graph is an induced subgraph of some Cayley graph of G. We prove that a sufficient condition for G to have a Sidon subset of order n (of either kind) is that (❘G❘ ⩾ cn³. For elementary Abelian groups of square order, ❘G❘ ⩾ n² is sufficient. We prove that most graphs on n vertices are not induced subgraphs of any vertex transitive graph with <cn²/log²n vertices. We comment on embedding trees and, in particular, stars, as induced subgraphs of Cayley graphs, and on the related problem of product-free (sum-free) sets in groups. We summarize the known results on the cardinality of Sidon sets of infinite groups, and formulate a number of open problems. We warn the reader that the sets considered in this paper are different from the Sidon sets Fourier analysts investigate. © 1985, Academic Press Inc. (London) Limited. All rights reserved.

This paper extends some earlier results on difference sets andB
2 sequences bySinger, Bose, Erdös andTuran, andChowla.

Codes for rank modulation have been recently proposed as a means of protecting flash memory devices from errors. We study basic coding theoretic problems for such codes, representing them as subsets of the set of permutations of n elements equipped with the Kendall tau distance. We derive several lower and upper bounds on the size of codes. These bounds enable us to establish the exact scaling of the size of optimal codes for large values of n. We also show the existence of codes whose size is within a constant factor of the sphere packing bound for any fixed number of errors.

Systematic q-ary ( q > 2) codes capable of correcting all asymmetric errors of maximum magnitude l , where l Â¿ q - 2, are given. These codes are shown to be optimal. Further, simple encoding/decoding algorithms are described. The proposed code can be modified to design codes correcting all symmetric errors of maximum magnitude l , where l Â¿ ( q -2)/2.

The number of comparisons required to select the i-th smallest of n numbers is shown to be at most a linear function of n by analysis of a new selection algorithm—PICK. Specifically, no more than 5.4305 n comparisons are ever required. This bound is improved for extreme values of i, and a new lower bound on the requisite number of comparisons is also proved.

High-capacity NAND flash memory can achieve high density storage by using multi-level cells (MLC) to store more than one bit per cell. Although this larger storage capacity is certainly beneficial, the increased density also increases the raw bit error rate (BER), making powerful error correction coding necessary. Traditional flash memories employ simple algebraic codes, such as BCH codes, that can correct a fixed, specified number of errors. This paper investigates the application of low-density parity-check (LDPC) codes which are well known for their ability to approach capacity in the AWGN channel. We obtain soft information for the LDPC decoder by performing multiple cell reads with distinct word-line voltages. The values of the word-line voltages (also called reference voltages) are optimized by maximizing the mutual information between the input and output of the multiple-read channel. Our results show that using this soft information in the LDPC decoder provides a significant benefit and enables us to outperform BCH codes over a range of block error rates.

Coding schemes in which each codeword contains equally many zeros and ones are constructed in such a way that they can be efficiently encoded and decoded.

We consider lattice tilings of $\R^n$ by a shape we call a
$(\kp,\km,n)$-quasi-cross. Such lattices form perfect error-correcting codes
which correct a single limited-magnitude error with prescribed
maximal-magnitudes of positive error and negative error (the ratio of which is
called the balance ratio). These codes can be used to correct both disturb and
retention errors in flash memories, which are characterized by having limited
magnitudes and different signs.
We construct infinite families of perfect codes for any rational balance
ratio, and provide a specific construction for $(2,1,n)$-quasi-cross lattice
tiling. The constructions are related to group splitting and modular $B_1$
sequences. We also study bounds on the parameters of lattice-tilings by
quasi-crosses, connecting the arm lengths of the quasi-crosses and the
dimension. We also prove constraints on group splitting, a specific case of
which shows that the parameters of the lattice tiling of
$(2,1,n)$-quasi-crosses is the only ones possible.

We study codes over GF(q) that can correct t channel errors
assuming the error values are known. This is a counterpart to the
well-known problem of erasure correction, where error values are found
assuming the locations are known. The correction capabilities of these
so-called t-location correcting codes (t-LCCs) are characterized by a
new metric, the decomposability distance, which plays a role analogous
to that of the Hamming metric in conventional error-correcting codes
(ECCs). Based on the new metric, we present bounds on the parameters of
t-LCCs that are counterparts to the classical Singleton, sphere packing
and Gilbert-Varshamov bounds for ECCs. In particular, we show examples
of perfect LCCs, and we study optimal (MDS-Like) LCCs that attain the
Singleton-type bound on the redundancy. We show that these optimal codes
are generally much shorter than their erasure (or conventional ECC)
analogs. The length n of any t-LCC that attains the Singleton-type bound
for t>1 is bounded from above by t+O(√(q)), compared to length
q+1 which is attainable in the conventional ECC case. We show
constructions of optimal t-LCCs for t∈{1, 2, n-2, n-1, n} that
attain the asymptotic length upper bounds, and constructions for other
values of t that are optimal, yet their lengths fall short of the upper
bounds. The resulting asymptotic gap remains an open research problem.
All the constructions presented can be efficiently decoded

Introduction to flash memory

- R Bez
- E Camerlanghi
- A Modelli
- A Visconti