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Residual doping concentration estimation in a separation by IMplanted OXygen film using current measurements
IET Science, Measurement & Technology
Abstract
In situ measurements of static characteristics for an ad-hoc silicon-on-insulator (SOI) device represent an important method for SOI technologies characterisation. The Separation by IMplanted OXygen (SIMOX) technique is based on oxygen ions implantation into Si-film. After annealing, an increased doping concentration was reported, because of the residual oxygen clusters within the film, giving rise to oxygen thermal donors. Therefore this study offers an original algorithm for doping concentration estimation in these SOI films. A specific device used for in situ electrical characterisation of SOI wafers is the pseudo-metal oxide semiconductor (MOS) transistor. In this study, the doping concentrations extraction is based on graphical solution of a non-linear equation and third-order derivative zeroing of the measured static characteristics. In this scope, experimental curves ID-VG, in inversion and accumulation were experimentally measured for a pseudo-MOS transistor made in SIMOX technology. In this situation, the threshold and flat-band voltage are extracted, free of classical conventions. The extracted doping concentration in film is roughly 5.8 × 1015 cm- 3; also the conductivity is changed from p to n in film, as the literature predicted.
... The ITO electrode has been used as Gate contact. This configuration (Fig. 5a) that contains two probes onto the active layer has been also involved in the pseudo-Metal-Oxide-Semiconductor (pseudo-MOS) transistor [34][35][36] or OTFT with bottom gate top contacts (BGTC) [37]. Three films of PABA-NCS material with different thickness values of 200, 400 and 600 nm has been deposited on the same substrate previously covered by 100 nm polystyrene (Fig. 5b). ...
... Hence, the regime at positive gate voltage has to be assigned to the depletion regime that corresponds to each PABA-NCS film thickness of 200, 400, or 600 nm. Similar characteristics of the pseudo-MOS transistors with Si-films, were previously reported [35][36][37]. ...
... An important discussion envisages a comparison among the static characteristics of our fabricated PABA-NCS organic transistor, the I D -V GS curves of an experimental transistor with pentacene [41] and some experimental picked points of a similar pseudo-MOS transistor with 200 nm Sin-type film on 400 nm SiO 2 [35]. To emphasize some novel aspects, the transfer characteristics are compared at logarithmic scale for current (Fig. 8). ...
We report the first successful green synthesis route for organic transistors based on para-aminobenzoic acid (PABA) grafted to ferrite nanoparticles, at room temperature. The obtained core–shell nanoparticles (NCS) have been investigated by DLS, FT-IR, SEM, TEM. Both average hydrodynamic diameter and zeta potential of synthesized PABA-NCS nanoparticles has been identified, indicating a good stability of this nano-compound. SEM analysis proved a heterogeneous structured material with quasi-uniform granular formations in size, while TEM revealed a ferrite core of 20 nm. The measurements of output characteristics in the saturation regime and transfer characteristics at negative gate voltages have proved that an organic transistor based on PABA-NCS has been accomplished. The current increasing over a negative threshold voltage demonstrated an accumulation channel onset in the PABA-NCS thin film. This is a final argument for the p-type behavior of the PABA-NCS film.
... The transfer characteristics show increasing currents with |V GS|, indicating an accumulation channel onset for V GS < −0.3V , Fig. 3b. The origin of leakage current for 0V < |V G| < 0.3V in Fig. 3b is explained by the partially depleted film with a conductive neutral region [23][24][25]. Similar shapes of the static characteristics of the pseudo-MOS transistors with Si-films were recorded by other authors, too [13,14,26]. ...
Organic thin film transistors are alternative candidates to classical electronics, due to the success of organic semiconductors with a carriers mobility more than 0.1cm 2 /Vs. The purpose of this paper is to offer an electrical characterization of some organic thin film transistors, based on a classical characterization method. Silicon On Insulator (SOI) wafers are classically characterized by the pseudo-MOS transistors. Hence, this paper at the outset presents main technological steps for the fabrication of an organic Semiconductor On organic Insulator, which is still a SOI structure. The fabricated organic structure is aided by nanotechnologies and uses non-toxic precursors, opening new directions for green organic electronics. The experimental current-voltage static characteristics are measured. The measurements of the transfer characteristics indicate an increasing drain current with the gate voltage in modulus. So, the p-type organic layer is working in accumulation. By electrical characterization, some of the device parameters are extracted: doping concentration around 8×10 13 cm − 3, holes mobility of 0.2cm 2 /Vs in the organic film and a global interface charge of 6×10 10 e/cm 2 .
... The Fe3O4-SSA film was contacted by two probes, i.e., the source and drain, and the ITO film was contacted by a third probe, i.e., the gate. This point-contact transistor, also named pseudo-MOS (Metal Oxide Semiconductor) or Ψ-MOSFET (Metal Oxide Semiconductor Field Effect Transistor)transistor, is specifically used for the in-situ electrical characterization of the conduction in thin semiconductors on insulators [17,18], including organic biomaterials [19,20]. The next paragraph presents the synthesis and microphysical characterization of Fe3O4-SSA. ...
A disadvantage of the use of pentacene and typical organic materials in electronics is that their precursors are toxic for manufacturers and the environment. To the best of our knowledge, this is the first report of an n-type non-toxic semiconductor for organic transistors that uses sulpho-salicylic acid-a stable, electron-donating compound with reduced toxicity-grafted on a ferrite core-shell and a green synthesis method. The micro-physical characterization indicated a good dispersion stability and homogeneity of the obtained nanofilms using the dip-coating technique. The in-situ electrical characterization was based on a point-contact transistor configuration, and the increase in the drain current as the positive gate voltage increased proved the functionality of the n-type semiconductor.
... The carrier concentrations of a-IGZO layers or SOI films are usually obtained by Hall measurements or current measurements [19]- [23]. However, these techniques are difficult to be applied to exactly measure the carrier concentrations in S/D contact regions and/or a patterned a-IGZO layer in a fabricated TFT. ...
In this work, a technology computer-aided design (TCAD) device model based on an fabricated amorphous InGaZnO thin-film transistor (a-IGZO TFT) was established to study the correlation between carrier concentration distribution, current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a-IGZO TFTs. The equilibrium carrier concentration of the a-IGZO layer influenced by defect states, interface fixed charges, gate and S/D electrodes were studied systematically and quantitatively. The a-IGZO thickness was varied from 10 nm to 140 nm. The doping concentration in the bulk a-IGZO layer and source/drain (S/D) contact regions were changed from 10(10) cm(-3) to 10(20) cm(-3). The physical mechanisms underlying the I-V and C-V variation caused by above-mentioned parameters were explored by analyzing the energy band diagram and carrier concentration distribution in the a-IGZO layer. The total number of electrons in the channel region of the TFT was calculated by numeric integration for further investigation of its correlation with the a-IGZO thickness, I-V, and C-V characteristics of the a-IGZO TFTs.
In the industrial chain of the nanomaterials for electronic devices, a main stage is represented by the wafer characterization. This paper is starting from a standard SOI wafer with 200 nm film thickness and is proposing two directions for the SOI materials miniaturization, indexing the static characteristics by simulation. The first SOI nanomaterial is a sub-10 nm Si-film with a rectangular shape. The influence of the buried interface fixed charges has to be approached by the distribution theory. The second proposal studies the influence of the vacuum cavity in a “U” shaped SOI nanofilm. In all cases, with rectangular or “U” shape film, the simulations reveal transfer characteristics with a maximum and output characteristics with a minimum for sub-10 nm thickness of the SOI film.
This paper presents a study of the effect of the gate-voltage-dependent mobility on the threshold voltage (V TH) extraction in long-channel MOSFETs by the transconductance change method and recently proposed transconductance-to-current ratio change method, using analytical modeling and ex-perimental data obtained on advanced silicon-on-insulator (SOI) FinFETs and ultrathin-body SOI MOSFETs with ultrathin high-k gate dielectrics. It is shown that, at vanishingly small drain voltage and constant mobility, both methods yield the same V TH val-ues, coinciding with the position of the maximum of the second derivative of the inversion carrier density in respect to the gate voltage. However, such is not the case anymore when considering gate-voltage dependence of mobility around threshold. Analytical expressions for the errors in the V TH values obtained by both methods due to mobility variation around threshold are obtained. Based on analytical modeling and experimental data, it is demon-strated that, for the same mobility variation, the resulting error on the V TH extraction caused by the gate-voltage-dependent mobility is much smaller for the transconductance-to-current ratio change method than for the transconductance change method. Index Terms—Mobility, MOSFET threshold voltage extraction, transconductance change method, transconductance-to-current ratio change method, unified charge control model (UCCM).
The application of an unconditionally stable locally one-dimensional finite-difference time-domain (LOD-FDTD) method for the full-wave simulation of semiconductor devices is described. The model consists of the electron equations for semiconductor devices in conjunction with Maxwell's equations for electromagnetic effects. Therefore the behaviour of an active device at high frequencies is described by considering the distributed effects, propagation delays, electron transmit time, parasitic elements and discontinuity effects. The LOD-FDTD method allows a larger Courant'Friedrich'Lewy number (CFLN) as long as the dispersion error remains in the acceptable range. Hence, it can lead to a significant time reduction in the very time consuming full-wave simulation. Numerical results show the efficiency of the presented approach.
Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics. © 2003 American Institute of Physics.
The fabrication, characterisation and quality factor control of a microelectromechanical system resonator with differential drive and readout is reported. The differential drive results in a linear relationship between the AC drive voltage and the applied force. Furthermore, the static DC force and the undesirable force at the second harmonic frequency (introduced by other driving methods) are also reduced. Differential readout is employed in order to minimise undesirable common-mode signals in the detection electronics. The device has been fabricated in silicon on insulator (using the Integram high aspect ratio micromachining process at QinetiQ) and fully characterised. The ability to track the resonant frequency with fine resolution is related to the quality factor of the resonant system. Commonly used detection techniques such as slope detection and phase detection both require a high quality factor, however, resistance to motion caused by air damping results in a low quality factor - degrading the performance of the sensor. The low-pressure quality factor is measured as being >5500 and reduces to ~10 at atmospheric pressure. The linear relationship between AC drive voltage and resultant force is exploited in conjunction with an electronic readout architecture yielding the device velocity to implement a force feedback technique - increasing the quality factor of the resonator.
1. Introduction. 2. Methods of Forming SOI Wafers. 3. SOI Devices. 4. Wafer Screening Techniques. 5. Transport Measurements. 6. SUS Capacitor Based Characterization Techniques. 7. Diode Measurements. 8. Transistor Characteristics. 9. Transistor Based Characterization Techniques. 10. Monitoring the Transistor Degradation. Index.
The dedicated application of the pseudo-MOS transistor is the SOI materials electrical characterization, with the advantage of a nondestructive technique. Also, the pseudoMOS transistor is an excellent tool for new tests revealed in the SOI devices development. This paper presents an infrequent work regime, encountered in some special biases conditions of the pseudo-MOS transistor. Whether the gate voltage is applied so that the SOI film begins to be depleted, before the inversion onset, a continuous source-drain neutral channel exists at the upper part of the film. The drain current is depending on the drain-source voltage and simultaneously is modulated by the gate action. Consequently, this work regime is a JFET-like behavior. The paper brings some original arguments to highlight this particular work regime.
At presentmetal oxide arresters find limited applications against very fast transient overvoltages (VFTOs). To enable these arresters to function effectively against VFTOs, it becomes necessary to study its design aspects and improve it. With this in view, modelling of arrester under VFTO has been performed. Experimental studies have been conducted to determine the behaviour of one 12 kV arrester assembly under VFTO. It is observed that there is a delay in the initial response of the arrester, which increases with steepness of the current surge because of stray capacitance effect. Based on this study, an innovative arrester model ( 198 kV) with distributed parameters for VFTO is proposed by incorporating the block and stray capacitance values, which are calculated using finite element method (FEM). The dynamic performance of arrester is successfully obtained using electromagnetic transient program (EMTP) for current surges of different front times. A dynamic hysteresis curve is constructed using proposed arrester model to verify the relative delays between the residual voltage and current surge. A few modifications in the arrester have been suggested to improve the dynamic performance and also for the new testing procedure of arrester under VFTO.
An original improved linearity multifunctional structure de-signed for VLSI applications will be further presented. The core of the circuit is represented by a differential amplifier based on an original linearization tech-nique. The great advantages of the increased modularity and controllability and of the reduced design costs associated represent an immediate consequence of the multiple functions realized by the proposed structure: amplifying, multiply-ing or simulating positive and negative resistances. The frequency response and the linearity are strongly increased by implementing original techniques, while the silicon occupied area per function is reduced as a result of the multifunction-ality. The simulation confirms the estimated results, showing a linearity error less than a percent for a small value of the supply voltage ±3 V and for an extended input range ±500 mV.
Today’s SOI technologies are able to produce buried oxides with a thickness spectrum from 400nm in the
standard HTA SIMOX, down to tens of nm in Unibond technique. In the SOI structures, two oxidesemiconductor interfaces exist, with specific associated charges. Conventional models ignore the charges situated at the buried oxide-substrate interface, being focused just on the front and back channels
conduction in the silicon film. All these fixed charges, classically expressed in e·cm-2, are physically
spread into a small volume that becomes significant in very thin films (nanofilms). This paper presents a
new model of the flat-band voltage using δ–distribution generator strings. The model accuracy increases
in the SOI nanofilms domain, accordingly with our theory and numerical simulations. On the other hand,
an experimental setup is presented for the spreading parameters extraction, in the case of a HTA SIMOX
wafer.
Indexed in ISI Thomson Reuters, Science Direct, Elsevier, Web of Science Categories: Engineering, Electrical & Electronic; Nanoscience & Nanotechnology, IDS Number: 081AR, WOS:000240290100016.
The SOI transistors permanently offer new candidates as nanodevices. The nothing on insulator
NOI transistor was recently derived from the nano SOI–MOSFET family. Their output
characteristics were theoretical modelled with an exponential law, validated by simulations.
The transfer characteristics presented sometimes increasing and others times
decreasing monotony. This phenomenon was put directly into a relationship with the gate
tunnelling breakdown. This paper has three final targets: the breakdown limitation
through the back-gate terminal, the real effects including in the NOI transistor architecture
– like interface charges or metal-semiconductor work function and quantum effects corrections
in simulations, in order to produce a better correlation between simulations and a
real behaviour. These simulations represent a milestone in the NOI nanotransistor manufacturing,
establishing some parameters that link the device to the real work regime.
Web of Science Categories: Computer Science, Interdisciplinary Applications; Computer Science, Software Engineering, IDS Number: 635WY, WOS:000280689500008.
Among the nanodevices, the vacuum nanotransistors are intensively studied in the last decade. A recent novel device was proposed as the NOT - Nothing On Insulator - nanotransistor, inspired from ultrathin SOT devices. Therefore, this new device preserves some properties from the SOT structures. Obviously, the NOT nanotransistor is a vacuum tunnel device among the vacuum field emission devices. But the main target, in this paper, is to prove that its particularity comes from affiliation to the FETs family, monitoring the gate-control on the drain current. The drain current is activated by the V-DS voltage under tunneling conditions. But the gate terminal modulates the carriers concentration and consequently the drain current flow, accordingly with its inherent included SOT structure. Also, a new model parameter comes to complete the NOT theory. The third order derivative was used for the extraction of a threshold drain-source voltage that splits the work domain in two conduction regions.
This paper presents the results of a study on the effect of alumina nano-fillers on electrical tree growth in epoxy insulation. Treeing experiments were conducted at a fixed ac voltage of 15 kV, 50 Hz on unfilled epoxy samples as well as epoxy nanocomposites with different loadings of alumina nano-fillers. Time for tree inception as well as tree growth patterns were studied. The results show that there is a significant improvement in tree initiation time with the increase in nano-filler loading. Different tree growth patterns as well as slower tree growth with increasing filler loadings were observed in epoxy nanocomposites. The nature of the tree channel and the elemental composition of the material on the inner lining of the tree channels have been studied using SEM imaging and EDAX analysis respectively of the cut section of the tree channels. It has been shown that the type of bonding at the interface has an influence on the electrical tree growth pattern. The nature of the bonding at the interface between the epoxy and the nano-filler has been studied using FTIR spectrometry. Finally the influence of the interface on tree growth phenomena in nanocomposites has been explained by a physical model.
Separation by implanted oxygen (SIMOX) wafers and bonded wafers are commercially available silicon-on-insulator (SOI) wafers. In particular, SIMOX process technologies have become important in system-on-a-chip (SoC) fabricated on SOI/Bulk hybrid substrates composed of SOI region for the logic circuits and bulk region for the dynamic random access memories (DRAMs) in recent years. However, we found that low-dose SIMOX wafers have energetically localized acceptor-like and donor-like trap states with the density of 1011 cm-2 at the SOI/buried oxide (BOX) interface by back-gate characteristics. In addition, we estimated that the high-density trap states are distributed within about 30 nm from the SOI/BOX interface in SOI layer by front-gate characteristics in MOSFETs with SOI layers of different thicknesses. Furthermore, we speculated that the distribution of the trap states in the SOI layer is attributed to nano-scale roughness at the SOI/BOX interface, which is peculiar to the SIMOX process. In this paper, we discuss the origins of the high-density trap states in SOI layer of SIMOX wafers considering the roughness at the SOI/BOX interface.
In this article, silicon on insulator (SOI) was fabricated by separation by implanted oxygen (SIMOX) layer transfer process. The thickness uniformity of the top Si (superficial Si of the SOI) evaluated by spectroscopic ellipsometry remains constant through the etch-stop thinning process. A defect-free top Si was observed by transmission electron microscopy, as well as its atomic-scale sharp interface that was adjacent to the buried oxide (BOX) layer. The top Si/BOX interface properties, including upper BOX surface roughness and interface state density, were investigated by atomic force microscopy (AFM) and pseudo-metal-oxide-semiconductor method, respectively. In addition, the surface morphology of the square pit and square hole defect of the top Si were observed. Using AFM, it is found that the morphology depends on the top Si/BOX interface morphology of the donor wafer and can be improved by optimizing the annealing process. The square hole defect caused by anisotropic etching is discussed in detail, and it is proven to originate from the defects in the SIMOX BOX.
The miniaturisation of the electronic devices pushes the semiconductor physics toward quantum physics. Some thinner SOI devices were studied, reaching from 200 nm to uni-atomic layer of Silicon placed On Oxide. Frequently, the insulator underneath the nanotransistor body serves as a mechanical support.This paper firstly proposes a generalisation of the “silicon on insulator” concept into “semiconductor on insulator”, with the same “SOI” acronym. The investigated device is a “diamond on insulator”, DOI-MISFET with two architectures, having 100 and 1 nm diamond film thicknesses. The simulations reveal a quantum well forming between source and drain when the film thickness decreases at 1 nm. The electrical characteristics preserve the classical shape in the case of 100 nm film thickness and presents special shapes in the case of DOI-MISFET with 1-nm diamond film thickness and a cavity.
Fe-doped PbTiO3 nanoparticles have been synthesized by chemical route using polyvinyl alcohol as a surfactant. The results indicate that the dielectric constant and magnetization value of these nanoparticles depends upon their size and Fe dopents. The x-ray diffraction analysis, and transmission and scanning electron microscopies show that the particle’s sizes in the specimens lie in the range of 19–30 nm. It is observed that the magnetization is enhanced with reduction in particle size. The largest value of saturation magnetization (Ms = 41.6×10−3 emu/g) is observed for 1.2 mol % Fe dopents. Dielectric constant and dielectric losses are controlled up to 15 MHz at room temperature.
Silicon on insulator-separation by implantation of nitrogen (SOI-SIMNI) films were formed by standard and multiple-step implantation methods. The Hall-effect measurements (4–400 K) show that the multiple-step implanted SIMNI films have a lower sheet resistance and higher carrier mobility than those in standard SIMNI films. The deep level transient spectra (DLTS) results indicated that there is a deep level defect in the surface silicon layers of standard SIMNI films and no deep level defects in the multiple-step implanted SIMNI films.
Nano sized zero valent iron (nZVI) can be used for the in-situ remediation of ground water contaminations by halogenated hydrocarbons or other contaminants. A novel approach is presented to detect nZVI and measure the concentration of nZVI in-situ during the remediation process. The presented inductive measurement system makes use of the magnetic material properties of nZVI. A specified magnetic field is generated locally in the aquifer and the magnetic flux density, which depends on susceptibility, is measured. Since the total susceptibility is very small, highly accurate measurements are necessary. Here, accuracy along with sensitivity is significantly improved by post-processing the measured data. Numerical simulations of magnetic fields and 3D visualisation techniques have been applied for development of the measurement technique. Finally, an experiment has been performed to verify the presented measurement method.
A major field of artificial neural networks (ANN) application is function estimation because of its useful properties, such as non-linearity and adaptivity particularly when the equation describing the function is unknown. In this study, the partial discharges (PD) breakdown voltage of five insulating materials under AC conditions has been predicted as a function of four input parameters, such as the thickness of the insulating sample t , the thickness of the void t 1, diameter of the void d and relative permittivity of materials ∈r by using two different ANN models. The requisite training data are obtained from experimental studies performed on a cylinder-plane electrode system. The voids are artificially created with different dimensions. Detailed studies have been carried out to determine the ANN parameters which give the best results. Studies have also been carried out to assess the extrapolation capabilities of the networks considered here. On completion of training, it is found that the ANN models are capable of predicting the breakdown voltage V b= f ( t , t 1, d , ∈r) very efficiently and within a small value of mean absolute error with the multi-layer feedforward neural network (MFNN) model marginally better than the radial basis function network (RBFN) model.
This paper presents a new methodology for the transient analysis of nanointerconnects, modeled as lossy and dispersive multiconductor transmission lines. The proposed model is derived from the solution of the Telegrapher's equations in the framework of the Sturm-Liouville theory. The open-ended impedance matrix is expressed in a series form as a sum of infinite rational functions, derived by the series form of the Green's function. Hence, a pole-residue rational model can be synthesized and a reduced-order model to be generated by a simple selection of dominant poles. The spectral form of the Green's function also allows to generate a rational model for the transient voltage sensitivity as well. The numerical results confirm the robustness of the proposed technique and its suitability to be adopted in the design flow of next generation nanointerconnects for signal integrity and electromagnetic compatibility purposes.
The recent increase in the number of failures during the installation and insulation of gas-insulated switchgear (GIS) has led to a need for a reliable risk assessment technique. Accordingly, in this study, a fundamental database of UHF partial discharge (PD) patterns corresponding to different types of defects is presented for risk assessment and for the observation and diagnosis of the state of insulation of GIS at field sites; the patterns have been obtained by modelling a number of defects that have been reported to be the most critical in GIS. For the realisation of a system that can simultaneously detect and analyse UHF PD (it is internationally accepted that the use of such a system is the most effective method to diagnose GIS insulation), a wideband UHF sensor and amplifier are designed and fabricated. The system operation is then investigated. In addition, a chaotic analysis of partial discharge (CAPD) is proposed. This analysis can identify the type of defect by means of PD pattern classification without employing the phase information of the applied voltage signal. The proposed CAPD can replace the conventional phase-resolved partial discharge (PRPD) analysis and can be employed at field sites when the phase information is unavailable. Especially, the PD patterns of free-moving conducting particles, known to be very important in GIS, can be distinguished from those of other defects when using the CAPD method, which is not the case when the PRPD analysis is being performed.
The breakdown mechanism of dielectric-covered rod/plane air gaps under positive lightning impulse voltages is investigated. Several gap lengths, varying between 2.5 and 15 cm, were employed and the simple air gaps were regarded as reference. The basic characteristics of coronas, namely inception time and voltage, were measured at applied voltages just sufficient for their inception up to voltages causing breakdown. Multiple level tests were conducted; thus, corona inception and breakdown probability distributions were obtained and time to breakdown was measured at several voltage levels. Interpretation of the results was made based on oscillograms of the electric field strength at the earthed plane, which was monitored through a capacitive probe, geometric field calculations and still photographs of the discharge at breakdown. In the dielectric-covered rod/plane gaps, breakdown occurs at higher applied voltages as a result of increase in both corona inception voltages and discharge path. The development of the discharge depends on the electric field distribution as modified by both space and surface charges associated with coronas preceding breakdown. Surface charge accumulation may affect the discharge path at breakdown.
As the size of semiconductor devices continues to shrink, the normally random distribution of the individual dopant atoms within the semiconductor becomes a critical factor in determining device performance--homogeneity can no longer be assumed. Here we report the fabrication of semiconductor devices in which both the number and position of the dopant atoms are precisely controlled. To achieve this, we make use of a recently developed single-ion implantation technique, which enables us to implant dopant ions one-by-one into a fine semiconductor region until the desired number is reached. Electrical measurements of the resulting transistors reveal that device-to-device fluctuations in the threshold voltage (Vth; the turn-on voltage of the device) are less for those structures with ordered dopant arrays than for those with conventional random doping. We also find that the devices with ordered dopant arrays exhibit a shift in Vth, relative to the undoped semiconductor, that is twice that for a random dopant distribution (- 0.4 V versus -0.2 V); we attribute this to the uniformity of electrostatic potential in the conducting channel region due to the ordered distribution of dopant atoms. Our results therefore serve to highlight the improvements in device performance that can be achieved through atomic-scale control of the doping process. Furthermore, ordered dopant arrays of this type may enhance the prospects for realizing silicon-based solid-state quantum computers.
Results concerning streamer propagation along cylindrical insulators coated with room-temperature-vulcanised silicon rubber coatings are presented. Experiments were carried out in a three-electrode arrangement consisting of a 12 cm long parallel-plane gap with an auxiliary needle in the earthed anode. Insulators could be inserted between the plane electrodes adjacent to them and almost in contact with the needle. Positive streamers were initiated by applying at the needle electrode a pulse voltage variable in amplitude and propagated over the insulators towards the upper plane electrode which was stressed by a negative DC voltage. The streamer propagation field at conditions from threshold up to the stable streamer propagation and the associated velocity were measured. The dependence of the streamer velocity on the electric field was investigated with the type of coating as parameter. Both the streamer propagation field and the associated velocity of propagation are higher, when a streamer propagates along the coated insulators, than the reference bare nylon insulator depending on the coating employed. Streamers might be used as an effective probe for studying the surface dielectric behaviour of coated insulators hence also for evaluating the various coatings used to improve the contamination performance of outdoor high-voltage insulators.
The degradation of the electrical performance of 2-MeV electron-irradiated thin gate oxide FD-SOI MOSFETs fabricated on ELTRAN and UNIBOND wafers is reported. The difference of the degradation is examined by analyzing the extracted MOS-transistor parameters. The degradation of the performance is discussed taking into account the front-back gate coupling effect and the floating body effect
The pseudo-MOS transistor (Ψ-MOSFET) is a surprising and
useful technique for the rapid evaluation of SOI wafers, prior to any
CMOS processing. We review the static and dynamic modes of operation as
well as the main models and methods for electrical parameter extraction.
Selected numerical simulations are presented in order to clarify the
optimal conditions of operation. Finally, practical applications are
exemplified which illustrate the efficiency of the Ψ-MOSFET
technique for in situ characterization of SOI technologies and processes
Non-linear electrical conduction in semiconductor structures
- A Rusu
Rusu, A.: 'Non-linear electrical conduction in semiconductor structures' (Bucharest House Publishing of the Romanian Academy, Romania, 2000)