978-1-4577-1343-9/12/$26.00 ©2014 IEEE
Fast Real-Time Hardware Engine for Multipoint Text Steganography
Ammar Odeh, Khaled Elleithy, and Miad Faezipour
Dept. of Computer Science and Engineering
University Of Bridgeport
Bridgeport, CT 06604, USA
email@example.com, firstname.lastname@example.org, email@example.com
Different strategies were introduced in the literature to
protect data. Some techniques change the data form
while other techniques hide the data inside another
file. Steganography techniques conceal information
inside different digital media like image, audio, and
text files. Most of the introduced techniques use
software implementation to embed secret data inside
the carrier file. Most software implementations are not
sufficiently fast for real-time applications. In this
paper, we present a new real-time Steganography
technique to hide data inside a text file using a
hardware engine with 11.27 Gbps hidden data rate.
The fast Steganography implementation is presented in
Different strategies are used to protect sensitive data
during transmission over unsecure channel. Some
algorithms suggest changing plain text into cipher text,
which is called cryptography. On the other hand, new
algorithms were presented to protect secret information
by hiding it which is called Steganography.
Steganography is a security mechanism which is used
to hide data inside a carrier file such as image, sound,
video, or text . Secret information can be inserted
inside a carrier file using different strategies where
each one of them has its own advantages and
disadvantages. The first insertion technique is injection
where data is injected inside a carrier file, and this
increases the file size, and sometimes changes the file
format. The second approach is substitution where
sensitive information is replaced by other data from a
carrier file. In the substitution method, a search is
conducted for bits that have the lowest effect in the
carrier file to apply exchange operation on them. In
this technique, the main advantage is that the Stego
object size is the same as the carrier file. This feature
avoids an attacker’s suspicion. The main idea is to hide
the data inside the carrier file and then transmit the
Stego file using any communication channel.
Stegoanalysis starts by analyzing the data to find if
there is any suspicious feature about the carrier file.
Some file properties can be used by the analyzer to
discover the hidden data. The file size and file format
are examples of such properties. As shown in Figure 1,
Steganography is classified into four categories
depending on the type of the carrier file, i.e. image,
audio, video, or text. Moreover, Text Steganography
can be classified into different categories depending on
the file application.
Most of Steganography algorithms are applied on
images which contain large and redundant data. The
Least Significant Bit replacement algorithm (LSB) is
one such Steganography algorithm . Other complex
algorithms have also been introduced to be applied on
images. However, the main problems are:
1. File Size:- Image file sizes are relatively large
compared to other files.
2. Image Distortion: - The replacement of some
bits may destroy/distort the image, and this
empowers the Stegoanalysis method to
discover the hidden data .
3. Deterministic Changes: The same
deterministic algorithm produces the same
distribution bits over the image which results
the same hidden style. In other words, if we
try to replace white pixels by red ones, all
white pixels will be converted to red, and this
way, the original file could be easily
Audio carrier files also have some weak points as
any audio signal can be converted and processed in the
frequency domain. Computing the lower control limit
and upper control limit it will be possible to deduce if
there is any hidden data in that file. Video carrier files
combine the advantages and disadvantages of images
and audio carrier files. [5, 6].
Text files represent the smallest files in terms of size
that can be used to transfer data from the sender to the
receiver, when compared with the other carrier files
. Moreover, the existence of huge amount of textual
data over the Internet enables us to hide data over
different websites and update those websites with a
new style of the hidden information that can be
embedded within the files. On the other hand, text files
represent the most difficult Steganography carrier files
since they do not have redundant patterns like audio or
image carrier files  .
B. Main Contributions and Paper Organization
A promising text steganography algorithm is
presented in this paper. The main approach is to use the
Multipoint steganography over Unicode text presented
in . Arabic letters contain some multipoint letters
that can be employed to hide data by shifting the points
vertically and horizontally. The main advantage of this
algorithm is the number of bits that can be hidden in
each letter , where most of the presented algorithms in
literature can hide only one bit per letter . In this
paper, we present an efficient hardware
implementation for the multipoint algorithm. In our
algorithm, we also suggest optimization techniques to
offer the highest degree of performance to achieve
“Magic Triangle Concepts” for Steganography; that is,
the function ability to achieve transparency,
robustness, and hiding capacity.
The rest of this paper is organized as follows. In
Section II we discuss previous text Steganography
techniques. The implementation of the Multipoint Text
Steganography is discussed in Section III. Discussion
and analysis of the implementation are also provided in
the same Section. Finally, concluding remarks are
offered in Section IV.
In , a novel hardware design was proposed for
image steganography using the least significant bit
(LSB) algorithm. The implementation was carried out
using Cyclone II FPGA of the ALTERA family. The
technique employed 2/3LSB design to produce a good
image quality to avoid any attacker doubt. Meanwhile,
it provided a high memory access performance to
speed up the system performance. In , an FPGA
hardware architecture was introduced to hide the secret
information by exploiting the noise regions in an
image. This strategy improved system transparency
which made it hard to realize the hidden data. In ,
an implementation of audio or video Stenography
using FPGAs was discussed. The proposed algorithm
speeds up the secret data embedding rate at the
hardware implementation for real-time Steganography.
Another hardware architecture was introduced in 
to simulate the ability to hide information inside image
and video carrier files. Two schemes were applied to
speed up real-time video applications. The main
drawback of this system is its need for a high speed
memory buffer. In , the proposed algorithm
employed image as carrier file by using multilayer
embedding in parallel with three-stage pipeline on
FPGA. Promising results showed high throughputs
while maintaining the image quality. In  and ,
authors employed perturbed quantization to hide data
inside JPEG image. The main feature of perturbed
quantization is that it is undetectable with current
As can be seen, most of the presented algorithms
that are implemented in hardware focus on image,
video, or audio as the carrier file for the secret
message. Meanwhile, text steganography has not been
considered for implementation in hardware engines
and/or digital signal processors.
In this paper, a novel hardware engine
implementation is presented over text as a carrier file.
The process is carried by the algorithm presented in 
to hide data in multipoint Arabic/Persian letters like (
ث, tha). In the Arabic language, there are five
multipoint letters, and in Persian there are eight. Each
character can be used to hide 2 bits to determine the
shifting and distance between letter points.
The Hiding Data Algorithm describes the scenario
at the hidden stage. Software implementation of this
technique would consist of two steps. The first stage is
the searching process and the second stage is
processing. Searching and processing are slow and
depend on the best and worst cases. Sequential search
applied in this algorithm has an average time O(N/2),
and this might increase the ability of the attackers to
capture a secret message. In the hardware
implementation, a high speed performance can be
achieved while increasing Steganography’s robustness
A. Hiding Data Algorithm
The algorithm used in this implementation is
presented in , where complete details are provided.
For the purpose of this discussion, we show here a
simple sketch of the algorithm.
Inputs: - Carrier file, hidden bits file
Output: - Stego file (updated multipoint letters)
Step1:- Choose any document
Step 2: Repeat while! (EOF)// repeat until the end of
the hidden file
Step3 check if Multipoint Letter then
Step 3a. Pack out the first two hidden bits
If hidden data ="00" then call Nochange ();
Else if hidden data= "01" then call distance ();
Else if hiddendata ="10" then call shifting ();
Else if hiddendata="11" then call
Step 4: Go to step 2
Step 5: Save file as PDF, then send it to receiver.
B. Hardware Implementation
For implementing this algorithm in hardware, a
state transition diagram must be constructed that
reflects the algorithm procedure. Figure 1 shows the
state diagram of the system. This system consists of
five states, where each state depends on the input value
(e.g. character in the text file) and the hidden data.
State A represents the initial state of the search. The
hidden information represents an input data to transfer
from one state to another.
Figure 2 represents the main components of the
hardware engine in RTL view. The system consists of
four comparison units to check the hidden information
in order to choose a suitable data path based on what
the hidden data bits are. Table I provides a list of the
used components representing the device utilization of
the FPGA for this hardware engine.
Furthermore, the system checks the input file data
too. It searches in the carrier file to insert remarks
depending on the hidden data. In other words, two sets
of inputs decide the next state transition in the state
In our implementation, we process the hidden file
two bits in each step to hide it and then a transition of
the current state to another state based on the
conditions. Figure 3 shows the signal analysis of data
inserted and the system states transformation using a
The state transitions occur based on the conditions
of the input data characters and the hidden data bits.
The critical path time reported by Quartus II
1.42ns. We process 16 bits in each clock
704.22 MHz .
Therefore, the system has an overall throughput of
11.27Gbits/second. This is while software simulations
would require O(n) time to process any file, and is
controlled by the file size and processor speed.
TABLE I. DEVICE UTILIZATION OF THE FPGA.
Family Cyclone DE II
Met timing requirements Yes
Total Logic elements 12/10570 (<1%)
Total pins 20/336 (6%)
Total virtual pins 0
Timing Models Final
Table II provides a comparison between our
implementation and 5 other hardware implementations
reported in the literature.
TABLE II. STEGANOGRAPHY HARDWARE ENGINES.
Algorithm Strategy/Carrier file
 2/3 Image Steganography
 Noisy region of image
 Audio, video
 Image, Video
 Multilayer and parallel
Proposed System Text file/ without change
TABLE III. CAPACITY OF WEBPAGE FOR DIFFERENT ARABIC
aljazeera.net 23.8 1245 105 2.11
daralhayat.com 15.4 968 126 1.37
salahws.com 10.3 535 104 9.14
holyquran.net 13.8 516 75 1.22
khayma.com 21.8 499 46 1,93
All the presented hardware implementations
process audio, image or video files. To the best of our
knowledge, there is no hardware systems reported in
the literature for processing text. The multipoint
Algorithm hardware implementation represents one of
the unique text Steganography algorithms, as it
provides very high speed processing of real-time
applications while maintaining a minimum memory
CONCLUSIONS AND FUTURE DIRECTIONS
In this paper, we presented a fast and real-time
hardware implementation for secure and safe
communications over networks. We have presented the
hardware implementation of the multipoint algorithm.
The proposed design represents one of the fastest Text
Steganography techniques in hardware. Previous
implementations provided efficient hardware
implementations over other carriers such as image,
video or audio files. This is the first hardware
implementation presented in literature for text
Steganography. In the future, we are planning to
present a parallel processing design to optimize the
system encryption speed and power consumption for
the multipoint algorithm as well as other text
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Figure 1. Finite State Machine Diagram.
Figure 2. RTL view of the hardware engine.
Figure 3. Timing Simulation of the hiding data algorithm and state transitions.
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