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... Mapping of the algorithm to event logical based on the procedure given in [11,12] . In realizing the CRCW sorting algorithm in event logic, the following assumptions are made: 1. ...
In this paper we present a method to estimate the layout area of
DSP algorithms that are designed using the standard cell methodology.
The circuit description is given as a netlist of standard cell library
modules. The area occupied by the circuit can be estimated prior to the
actual layout phase. Area estimation before final layout is important
for design evaluation and for the prediction of the chip floorplan
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October 2003 · IEEE Design and Test of Computers
What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system operation frequency. They demonstrate that there can be a high correlation between frequencies
... [Show full abstract] resulting from structural testing and those resulting from functional testing. Read more November 1981 · Bell Labs Technical Journal
In this paper, we compare four different methods of fault simulation in terms of their handling of arbitrary numbers of logic values, modeling levels, and detailed timing. The methods considered are parallel, deductive, multilist, and concurrent simulation methods. Since some of the methods, in their current forms, are unable to handle all the problems under consideration, we have proposed
... [Show full abstract] extensions to the methods wherever necessary before making the comparisons. While all the methods considered are capable of solving the problems with the same degree of accuracy, the concurrent simulation method appears to be the simplest and most flexible. Read more March 2006 · Digest of Technical Papers - IEEE International Solid-State Circuits Conference
A microprocessor featuring 2 Hammer cores and an on-chip DDR2 memory controller implements Pacifica architectural support for virtualization. It is fabricated in a 90nm triple-V<sub>t</sub> partially-depleted SOI process with 9 layers of copper interconnect. The chip achieves a clock frequency of 2.6GHz at 1.35V while dissipating 95W
Read more July 2018
Imprecision in timing can sometimes be beneficial: Metric interval temporal logic (MITL), disabling the expression of punctuality constraints, was shown to translate to timed automata, yielding an elementary decision procedure. We show how this principle extends to other forms of dense-time specification using regular expressions. By providing a clean, automaton-based formal framework for
... [Show full abstract] non-punctual languages, we are able to recover and extend several results in timed systems. Metric interval regular expressions (MIRE) are introduced, providing regular expressions with non-singular duration constraints. We obtain that MIRE are expressively complete relative to a class of one-clock timed automata, which can be determinized using additional clocks. Metric interval dynamic logic (MIDL) is then defined using MIRE as temporal modalities. We show that MIDL generalizes known extensions of MITL, while translating to timed automata at comparable cost. Read more January 1994
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in comparison with all other approaches, since these are based on approximations of this criterion. Timing verification is an important aspect in chip design. However, the growing complexity of combinational circuits increases the
... [Show full abstract] total number of false paths, which demands fast and accurate false path elimination methods. Several approaches have been presented in literature, but all are based on approximations of the exact criterion, and offer no exact results. This paper presents the first implementation of the exact criterion. Experiments show that this tool is much more accurate in comparison with other approaches. The rest of this paper is organized as follows. Section 2 discusses the exact and other criteria. A description of the proposed algorithm is given in section 3. Then the two steps responsible for eliminating false paths will be described in section 4. Section 5 discusses the results obtained by the proposed tool. Finally we will finish this paper with the conclusions of section 6. 1. Introduction The maximum operational frequency of a circuit is determined by the maximum propagation delay of its combinational parts, which is defined as the longest delay it takes for a signal to propagate from a primary input to a primary output. In other words, the maximum delay of a combinational part is equal to the length of its critical paths. A straightforward approach to compute the length of the critical paths is to simulate the combinational circuit for all possible input vectors (vector dependent approach). However, since the number of different input vectors increases exponentially with the number of inputs, this approach is only feasible for to circuits with only a few primary inputs. The first approach to compute the length of the critical paths, without simulating all input vectors (vector independent approach), was based on the PERT (Program Evaluation and Review Technique) algorithm (1). Since this approach determines the longest path without taking the logical dependencies into account, it is very likely to find a false path. The PERT delay was therefore used as an upper bound for the length of the critical paths. However, the growing complexity and integration of combinational circuits started to demand tighter bounds. This has resulted in different timing analysis (or critical path finding) approaches, each one based on a different path sensitization criterion. The static criterion (2) provides a lower bound, while others (3-6) offer an upper bound. The viability criterion (7) gives the exact delay of the critical paths. Read more April 2014 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
This paper presents a new asynchronous design theory and a novel template for single-track handshaking that targets medium-to high-performance applications. Unlike other single-track templates, the proposed work supports multiple levels of logic per pipeline stage, improving area efficiency by sharing the control logic among more computation logic while at the same time providing higher
... [Show full abstract] robustness to timing variability. The proposed template also yields higher throughput than most four-phase templates and lower latency than bundled-data templates. The template was incorporated into the asynchronous ASIC flow Proteus, and experiments on ISCAS benchmarks show significant improvement in achievable throughput per area. Read more February 1987 · International Journal of Project Management
A recurring problem in precedence project planning networks is the time analysis of hammock activities. It is common practice in network logic drawings to ‘bridge’ some points with hammock activities as a flexible means to accommodate work of unknown duration, at least during the initial planning stage. In the past, hammocks were accounted for in such a way that, on some occasions, they consumed
... [Show full abstract] the float of preceding or succeeding activities unnecessarily. Thus, depending on their location within the network, erroneous results could be generated. The time analysis of hammocks has never been based on a set of solid rules justifying the algorithmic determination of their start and finish times. This paper proposes an algorithm which only makes hammock activities comply with the ‘behaviour’ of the path they belong to, leaving the rest of the network timing and resulting barcharts unaffected by them. The proposed method has also been implemented in a computer application that treats hammock activities consistently with the timing of the entire project. Finally, some examples of hammocks placed in various locations of network charts are presented. Read more Article
Full-text available
February 2019 · Mobile Networks and Applications
Node mobility, as one of the most important features of Wireless Sensor Networks (WSNs), may affect the reliability of communication links in the networks, leading to abnormalities and decreasing the quality of service provided by WSNs. The mCWQ calculus (i.e., CWQ calculus with mobility) is recently proposed to capture the feature of node mobility and increase the communication quality of WSNs.
... [Show full abstract] In this paper, we present a proof system for the mCWQ calculus to prove its correctness. Our specifications and verifications are based on Hoare Logic. In order to describe the timing of observable actions, we extend the assertion language with primitives. And terminating and non-terminating computations both can be described in our proof system. We also give some examples to illustrate the application of our proof system. View full-text September 1996
Defying the timing defects and limitations imposed on traditional
asynchronous circuits, the externally asynchronous internally clocked
(EAIC) system provides the digital designer with a new tool for
constructing self-timed circuits. Based on revolutionary memory unit,
the EAIC architecture lends itself nicely to sequential design, where a
typical EAIC system may require less power, use less
... [Show full abstract] hardware, and
operate at much greater speeds than comparable synchronous designs. This
paper describes the analysis of several circuits and culminates with a
comparison of EAIC systems versus synchronous designs Read more September 2009 · Microelectronics Reliability
A new Jitter Mitigation feature in the latest generation laser voltage probing (LVP) tool effectively removes PLL jitter from LVP waveforms [Ng Yin S, Lo W, Wilsher K. Next generation laser voltage probing. In: Proceeding, international symposium on testing and failure analysis; 2008. p. 249]. It facilitates the probing of phase-locked loop (PLL) driven circuitry inside of integrated circuits
... [Show full abstract] (ICs). In particular, it allows the detection of small amounts of excess jitter that would normally be masked by the much larger jitter of the PLL. To demonstrate the practical application of this Jitter Mitigation feature, we report on the jitter analysis of a PLL-generated clock signal as it propagates, through buffers and logic circuitry, to an external I/O pad of an IC. The IC was a 0.9V, 65nm technology graphics processing unit (GPU). The analysis was to determine where excess jitter was introduced into the clock path when the GPU was electrically stressed. Details of the jitter analysis, including Jitter Mitigation methodology, probing setup, and results of the timing measurements, will be presented in this paper. Read more December 2014 · IEEE Transactions on Device and Materials Reliability
This paper utilizes device-level eye-diagram measurements to examine negative bias temperature instability (NBTI)-induced changes in timing jitter at circuit speeds. The measured jitter is examined for a variety of ring oscillator and pseudorandom gate patterns. The ring oscillator patterns were chosen to mimic typical NBTI reliability characterizations, whereas the pseudorandom patterns act as
... [Show full abstract] an approximation for real-world random logic. Our observations indicate that NBTI-induced jitter is gate pattern dependent and most severe for the pseudorandom case. Collectively, this paper strongly suggests that typical NBTI ring oscillator characterization methods are insensitive to random logic timing jitter. Read more March 2009
Due to the notable change of channel width, supply voltage; and clock frequency, CMOS IC technologies are rapidly approaching their ultimate limits. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable error rates and make further nanometer scaling increasingly difficult. The error detection scheme based on GRAAL architecture
... [Show full abstract] (Global Reliability Architecture Approach for Logic) combines latch-based design and time redundancy techniques to achieve high detection efficiency for temporary faults (timing faults, SEUs, and SETs) at low area, power and speed penalties. In this paper, we use a finite state machine (FSM) circuit as test vehicle to validate the error detection architecture. The experimental results validate the claimed high error detection efficiency. Read more Last Updated: 05 Jul 2022
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