Conference Paper

Self Timing of Event Logic Data-Paths

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... Mapping of the algorithm to event logical based on the procedure given in [11,12]. In realizing the CRCW sorting algorithm in event logic, the following assumptions are made: 1. ...
Conference Paper
Full-text available
In this paper we present a method to estimate the layout area of DSP algorithms that are designed using the standard cell methodology. The circuit description is given as a netlist of standard cell library modules. The area occupied by the circuit can be estimated prior to the actual layout phase. Area estimation before final layout is important for design evaluation and for the prediction of the chip floorplan
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