Conference Paper

Formal Verification of DSP VLSI Architectures

December 1994

Conference: International Conference on Electronics, Circuits and System
At: Cairo, Egypt,

Authors:

Khaled Elleithy

University of Bridgeport

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Article

On the specification for VLSI systolic arrays

April 1993

Fuyau Lin

Formal verification has become an increasing prominent technique towards establishing the correctness of hardware designs. We present a framework to specifying and verifying the design of systolic architectures. Our approach allows users to represent systolic arrays in Z specification language and to justify the design semi-automatically using the verifier. Z is a notation based on typed set ... [Show full abstract] theory and enriched by a schema calculus. We describe how a systolic array for matrix-vector multiplication can be specified and justified with respect to its algorithm.