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Board implementation and its performance for IR-UWB IEEE.802.15.4a from multiple ASIC chips

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One energy efficient way of ASIC implementation for the standard IEEE802.15.4a was considered in greater detail. The main focus was on developing a solution for short range communication based on impulse radio ultra wideband. The ASIC implementation is performed with the 250 nm SiGe technology from IHP, Germany. The current system consists of three chips: radio frequency frontend, digital baseband and an integrating analogue digital converter. All the chips were fabricated and designed at IHP. A non-coherent energy detection receiver was realised which collects energy over 16 ns in analogue fashion. The performance of the complete system was evaluated bringing the chips on a board. Our multiple ASIC approach was a necessary step towards a complete integration of the system into a single chip. This paper discusses the function of individual chips and their interaction on a board. The performance was assessed by frame error rates, approximate coverage and waveforms at certain points. Initial laboratory tests and measurements suggest that the implemented system can support wireless communications in a distance of up to five meters and consume reasonable power.
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1
Board implementation and its performance for IR-UWB IEEE.802.15.4a from
multiple ASIC chips
IHP
S. Olonbayar, D. Kreiser, D. Martynenko, G. Fischer, O. Klymenko, R. Kraemer
Im Technologiepark 25
15236 Frankfurt Oder, Germany
sonom@ihp-microelectronics.com
Abstract: One energy efficient way of ASIC
implementation for the standard IEEE802.15.4a was
considered in greater detail. The main focus was on
developing a solution for short range communication
based on impulse radio ultra wideband. The ASIC
implementation is performed with the 250 nm SiGe
technology from IHP, Germany. The current system
consists of three chips: radio frequency frontend,
digital baseband and an integrating analogue digital
converter. All the chips were fabricated and designed
at IHP. A non-coherent energy detection receiver was
realised which collects energy over 16 ns in analogue
fashion. The performance of the complete system was
evaluated bringing the chips on a board. Our multiple
ASIC approach was a necessary step towards a
complete integration of the system into a single chip.
This paper discusses the function of individual chips
and their interaction on a board. The performance was
assessed by frame error rates, approximate coverage
and waveforms at certain points. Initial laboratory tests
and measurements suggest that the implemented
system can support wireless communications in a
distance of up to five meter and consume reasonable
power.
Key words Digital baseband, RF frontend, ADC,
non-coherent energy detection, frame error rate,
communication coverage
I. Introduction
In the past decade wireless communication industry
has experienced tremendous breakthrough in their data
rates, coverage, compatibility to existing systems and
energy efficiencies. As a consequence wireless
systems have been used extensively everywhere
providing competitive quality as their counterpart
wired ones making communication easy, portable,
affordable and comfortable ever. This trend will
obviously continue intensively covering more and
more applications. Today there exist mainly two sorts
of wireless communications: narrowband and
wideband. Narrowband systems usually occupy
smaller bandwidth being under 100 MHz and the
transmission is likely to be of high radiation power
and wireless systems are assigned different frequency
band for avoiding interference. An example of which
includes a large number of standards currently in use
such as a mobile standard GSM and its variations,
short range wireless Bluetooth and WLANs. These all
operate at the bands reserved for them radiating the
energy allowed. Whereas wideband systems are
assigned a much larger bandwidth exceeding 500 MHz
that permits not only huge data rates but a greater
degree of signal processing for avoiding possible
distortions. Such standards are allowed a lower
transmit power as they can restore the signal spread
over a large bandwidth with a high processing gain.
One good example of such wideband system is an
impulse radio ultra wideband (IR-UWB) which
exhibits a bandwidth larger than 500 MHz. It is
characterised by its extremely short duration pulses to
be measured in few hundred nanosecond. Moreover,
the transmit power is dictated to be under -
41dBm/MHz. This promises an excellent coexisting
capability with other standards and calls at the same
time for challenging implementation especially if the
energy consumption is of importance. Another
prevailing feature of IR-UWB is its shortest latency
amongst others which can guarantee it huge
application potential for indoor localisation and delay
sensitive communications. With IR-UWB very
accurate localisation in the range of few cm is possible
[10]. This work concentrates on the implementation of
the standard IEEE802.15.4a based on IR-UWB. The
paper is structured into five sections. In the first three
sections parameters, transmitter and receiver
architecture and their working principle are discussed.
A Board solution of the IR-UWB consisting three
chips was treated in the section IV. Finally, test
procedure and test results are presented followed by a
summary.
II. Implemented IR-UWB parameters
The operating frequency band was chosen to be
7.9872 GHz. The data rate is 850 Kbit/s, the
bandwidth is 499.2 MHz and the duration of the
Gaussian impulse is approximately 2ns. The preamble
2
(PA) length is made variable as 16, 64, 1024 and 4096.
The start of frame delimiter (SFD) is constructed from
eight preambles. The preamble is made up from
ternary sequences with the length of 31 consisting of -
1, 0 and 1. 15 zeros are inserted between the elements
of the preamble sequence. An extensive specification
of the IR-UWB as a standard IEEE.802.15.4a is
presented in [2].
III. IR-UWB IEEE802.15.4a transmitter
The main task of the transmitter is to generate well
shaped Gaussian pulses fitting to the standard
IEEE802.15.4a spectrum mask. A combination of a
burst position modulation (BPM) and binary phase
shift keying (BPSK) is used for transmitting data. A
burst of 16 chips is positioned either in the first or
second half of symbols with a duration of 1024 ns
representing one bit of data. The polarity of the burst
carries the second bit within a symbol delivering the
data rate of 850 Kbit/s. As in many other standards,
the transmit signal comprises preamble part, SFD,
PHY header (PHR) intended for informing the
receiver the packet length, data rate and several other
bits for improving link performance. It is followed
finally by a payload occupying only 32 ns time
window as a burst of a complete symbol. It shows low
duty cycling of IR-UWB. For energy saving reasons,
the transmitter could be turned off for the rest of the
time. Transmit signal at the input to the antenna takes
the waveform that appears in Figure 1. It is the
waveform that was generated from the transmit board
built. It can be observed that a frame containing
preamble phase, SFD and data field is clearly
recognisable.
Figure 1. Waveform of IR-UWB compatible to the
standard IEEE.802.15.4a displayed with Tectronics
The transmitter consists of mainly two parts: digital
baseband and high frequency analogue frontend. At
the baseband common baseband operations such as
channel coding, decoding (half rate convolutional
coding, Reed Solomon coding), linear phase shift
register, burst position modulation and binary phase
shift keying and their demodulation are performed. For
making the implementation energy efficient, the
digital baseband was chosen to operate at the clock
rate of 31.2 MHz. By doing so the ASIC solution
becomes simpler with the intended technology as
digital hardware generation tools like cadence used for
synthesis, simulation and layout can support this speed
regardless the complexity of the algorithm to be
implemented. Furthermore, this lower speed digital
baseband allows simpler interfacing between the HF
frontend and itself. Keeping the interfacing slower was
advantageous due to the following two reasons.
Firstly, the board design for testing the chips becomes
affordable secondly packaging of dies with low
frequency pins is easier and more reliable. At the
transmitter 499.2 MHz bandwidth signal is obtained
digitally by using a serialiser which converts 16 bit
31.25 MHz signal into a 499.2 MHz serial stream. The
conversion is done by progressing through four stages
doubling the clock rate every time. This was initially
the hardest part to realise as 500 MHz was much faster
than the supporting clock rate of the chosen
technology and providing pins with this frequency for
the connection to the HF presented challenges too. To
tackle it, the serialiser running at 499.2 MHz was
placed in the HF frontend wiring it to other HF
components after it has been implemented and tested
digitally. This approach can ease the interfacing and
permit simpler testing of the baseband and HF
implemented as separate chips. The digital baseband is
designed in a way to be controlled with a SPI interface
and it contains two memory elements one is for
transmitter and the other is for receiver each with 128
bytes. The data to be transmitted is loaded first to the
transmit memory and sent from there. The baseband
can be configured with the SPI interface in a number
of operation modes. Possible configurations are
transmit, receive and several test modes for operating
and testing components individually. The parts of the
HF frontend can be switched on and off too through
this interface. The baseband ASIC implementation
consumes currently less than 20mW occupying a
silicon area of 5 mm
2
. More detailed discussion on the
implemented baseband is given in [7].
The baseband delivers HF frontend two bits at the
same time at the rate of 499.2 MHz. One signals the
HF to generate a Gaussian impulse with the duration
of 2 ns and the other informs it the polarity of the
impulse. Some authors refer to these two signals as an
on-off-keying (OOK) and BPSK respectively.
Therefore, the main objective of the HF transmitter is
Preamble
SFD
Data
3
to generate well shaped 2 ns duration pulses with
correct polarity at the required positions. The more
accurate is the shape, the better it will be detected at
the receiver. Within a symbol period, in our case 1024
ns, a burst of 16 pulses is sent with changing polarities
carrying two bits of information. The block diagram of
the implemented IR-UWB appears in Figure 2. With
the aid of digital to analogue converter (DAC) three
states are generated: positive and negative pulses and
zeros indicating the need of 1.5 bits. Such a pulse
generation scheme with differential signalling adopted
for the HF frontend is considered in [8].
Figure 2. Block diagram of transmitter for IR-UWB
The pulses at the output of the DAC are shaped with
the following low pass filter (LPF) with the bandwidth
of 250 MHz fitting to the spectrum mask dictated. The
design and performance of the designed filter is treated
in detail in [9]. With the power amplifier (PA) the
signal is amplified to the level suitable for the
transmission through the antenna. The final stage of
the transmitter is the up-converter which translates the
baseband signal to the radio frequency of 7.9872 GHz.
The current design can provide around 54mV peak-
peak differential voltage to the input of the antenna
which corresponds nearly to -80 dBm.
IV. IR-UWB IEEE802.15.4a receiver
As stated previously, non-coherent energy detection is
adopted due to its affordable complexity and
corresponding power efficiency. Such non-coherent
detection does not perform phase recovery for the HF
signal and it rather squares it delivering only positive
pulses for the detection. As a consequence, polarity
information is lost forcing the baseband receiver to
rely on only +1 and 0 not on -1 degrading the
synchronisation performance. The correlation property
here can diminish too compared to the original
preamble sequence. For the data, part through this
squaring circuitry, 16 pulses positioned somewhere
within a symbol, are all turned positive. This can allow
the receiver to detect larger energy making the signal
to be better differentiated from the noise. A block
diagram of the receiver showing main components of
it is illustrated in Figure 3.
Figure 3. IR-UWB receiver block diagram
The receiver should be designed in a way to possess a
good sensitivity and be able to receive signal as low as
-70 dBm for covering larger distance. Hence the
antenna needs to couple maximum possible energy. As
in many other systems, low noise amplifier (LNA)
with the gain of around 20 dB is used for amplifying
weak receive signal. LPFs are placed afterwards for
suppressing high frequency components and passing
499.2 MHz baseband signal. The variable gain
amplifier (VGA) can provide up to 45 dB gain having
a step of 16 each with 3-4 dB and it is controlled
automatically by 4 bit input from the baseband. The
operation and performance simulation of the automatic
gain controlling (AGC) used for this project are
reflected in [1]. Once the proper gain is set and the
signal is brought to the level high enough above the
noise background, the digitisation is carried out for the
baseband reception. Ideally and theoretically 499.2
MHz baseband analogue signal should be digitised at
least at the 998.4 MHz which could lead to very
elevated power consumption figure for the whole
system. As the goal of the implementation was to keep
the consumption as low as possible, before digitising
certain analogue integrating circuit over the time span
of 16 ns was incorporated. With this integrator, the
analogue signal is voltage integrated over 16 ns and
the result of the integration is then digitised with the
analogue to digital converter (ADC) at the sampling
rate of only 62. 4 MHz. The resolution of this ADC
was chosen to be 6 bits by performing simulation
assuming certain UWB channel model [3]. Since 15
zeros are inserted in the preamble after each of its
elements, such integration over 16 ns will not result in
the loss of impulses. Between consecutive elements of
the preamble therefore, there is a gap of zero for 30 ns.
With this analogue integration every single impulse
should be detected as long as the average noise voltage
within the interval stays below the accumulated signal
voltage. The only concern is that single impulses may
fail to be detected in an increased distance of
communication due to their high attenuations. The
integrator is built from a RC network with the time
constant of 16 ns. For better discharging performance,
two parallel operating integrators are realised
switching between them every 16 ns as illustrated in
LPF
DAC
PA
insert
BPM
BPSK
LFSR
(1.5 bit
fs=0.5GHz)
BW=250 MHz
Conv
R
-
S
Serialize
16:1
Baseband Clock 31.2 MHz
Serializer
Clock
499.2 MHz
Data
MAC
PA
HF Frontend
7.9872 GHz
4
Figure 4. Whilst one is integrating, the other sends its
integrated voltage to the ADC and discharges (reset)
itself completely. An advantage of having two
integrators is to leave enough time for discharging so
that integration can start always from zero with no
remaining from the previous interval.
a) b)
Figure 4. Differential RC integrator and its timing
diagram
This way accumulated and averaged voltage within 16
ns is digitised by the following ADC with no dead
time. The HF receiver supplies 2V peak-peak
differential 499.2 MHz bandwidth signal with the
common mode voltage of 1.9V at the input of the
integrator. Differential signalling is usually preferred
for high frequency circuits due to its immunity to
interference. Since there is a squarer involved in the
HF part, only positive impulses arrive at the
differential integrator. Therefore, the ADC operates in
positive half of its full scale due to its differential
signalling.
The ADC can resolve 1000mV/6415mV implying
that transiting from one digital value to the next is
equivalent to 15 mV. The digitised signal at the
sampling rate of 62.4 MHz is received with the digital
baseband. The digital baseband starts by adjusting the
gain and at the same time the synchronisation
algorithm performs correlation of receive signal with
the known preamble sequence. The synchronisation is
achieved with the accuracy of 16 ns. Two correlators
are used at the baseband receiver one is delayed by 16
ns or one sample to the other. This correlation
procedure guarantees a capture at least half of the
energy contained within a time window of 32 ns. As
there is one 2 ns impulse in the preamble phase
followed by zeros lasting for 30 ns, the adopted
correlation method can therefore detect it through the
integrator independent of initialising moment for the
correlation. As soon as synchronisation is achieved,
data detection commences by comparing the energy
received at expected positions at the first and second
half of a symbol deciding as “1” if more energy is
found in the first half and vice versa. Since the
implementation is non-coherent the polarity of
impulses is not recovered. Therefore, every second bit
produced as redundancy by the half rate convolutional
encoder is not received. Detailed consideration of the
signal detection and synchronisation are given in [6].
V. Board implementation for IR-UWB
IEEE802.15.4a
As stated and discussed in previous sections, the
complete IR-UWB system supporting wireless
communication at the speed 850 Kbit/s consist of three
chips: HF frontend, integrator and digitiser and the
baseband as shown in Figure 5.
Figure 5. A solution for IR-UWB from three chips
The HF Frontend occupies an area of around 5 mm
2
consuming approximately 150 mW. Silicon area
requirement for the baseband is 5.6 mm
2
and the
power dissipation amounts to 19 mW. Integrating and
ADC chip needs an area 0.93 mm
2
consuming less
than 5 mm
2
area. Hence the overall consumption for
this three chips system totals to around 175 mW. It is
worth to note that this figure refers only to the case
where all the components are activated. There is a
huge room for reducing the energy since the first test
version encompasses some test circuitries and it is not
optimised with respect to energy efficiency. A
complete integration of the system i.e these three chips
into a single chip has been conducted at IHP and it is
currently under testing. Better performance is expected
from the fully integrated single chip implementation.
Figure 6. Board diagram containing three components
of the IR-UWB
For testing and measuring the interaction of the
components developed a board was constructed (See
Figure 6). It was a necessary step to carry out before
5
starting full integration. Apart from the three
components, the board contains some distributing
circuitries for generating the needed clocks 31.2 MHz,
62.4 MHz and 499.2 MHz differential and single
ended and power supplying and stabilising part.
Reference quartz clock generator was placed on the
board from which the other clocks are produced
through division. A differential 499.2 MHz clock was
generated using MAX3674 clock synthesiser from
Maxim.
Figure 7. A photo of the board containing three chips
and supporting bidirectional wireless communication
The photo of the board appears in Figure 7. The board
can be used for both transmitting and receiving
supporting bidirectional communication.
VI. Test and measurement of board
After standalone test of components, board test and
measurement was started. For making the components
to work, proper clock amplitudes with certain DC shift
was required. Apparently, extensive testing should be
conducted to prove the functionality of such wireless
system. The performance of the implemented IR-
UWB wireless system can depend on the following
factors.
Transmit signal is not well shaped and the
bandwidth is not exactly 499.2 MHz due to
improper filtering, clocking and amplification.
Antenna coupling loss at both the transmitter and
receiver can limit the range and degrade the
performance.
The antenna itself may fail to radiate in desired
direction and capture required energy.
Variable gain amplifier at the receiver may show a
nonlinear behaviour distorting the signal
Imperfect DC cancellation at the output of the HF
can cause the ADC to go out of range at a lower
gain lowering the coverage
Integrating and ADC component can fail to
discharge fully when transiting to the next interval
causing errors in synchronisation and data
detection
The synchronisation performance can degrade at
increasing distances as single short duration (2 ns)
impulses become hard to differentiate from the
noise
The first objective was to establish if the individual
components can interact as they are supposed to be
and investigate achievable communication range the
current system can support. For this purpose, frames
consisting of 17 bytes of data were transmitted with
the constant interval between them. Labview graphical
user interface (GUI) was developed and used to
generate continuous transmission and reception and
evaluate frame error rate (FER) and the obtainable
range (See Figure 8). A Vivaldi antenna suitable for
ultra wideband signals is used for the measurement.
Figure 8. Labview Graphical user interface for
evaluating performance of the developed IR-UWB
Through this GUI memories built in the digital
baseband with the capacity of 128 bytes can be
accessed by writing some bytes into it and reading
them at both the transmitter and receiver side. Apart
from this, a certain test procedure is introduced with
which the digital transmit baseband signal at the rate
of 31.2 MHz is applied back to the digital receiver
internally without leading it as pins to the outside
world. This serves to guarantee the functionality of the
digital baseband as the clock is perfectly synchronous
everywhere. Once this test runs, real receive signal
from the integrating and ADC circuits can be applied.
If this signal in the form of frame is received correctly
the detection is considered reliable. The frame error
rate test was carried out in the following way. The
bytes to transmit were first written to the transmit
memory with a certain command from the computer
6
acting as a master for a SPI communication. As SPI,
Aardvark I
2
C/SPI Adapter was used. With a next
command from the master, the bytes written in the
memory are sent through the antenna. For doing this,
not only send command but also several other control
and chip select signals are sent to turn on the HF
components such as PLL and several others. Once a
frame is transmitted or transmission is complete, the
receiver is checked if it received the signal correctly or
not. This way the FER is determined by dividing the
number of correctly received frames to the total
number of frames sent. Given the imperfect antenna
directivity and high loss and other signal losses
occurring on board through coupling, the developed
IR-UWB can offer currently a wireless communication
range of around 2.5 m (See Figure 9). The quality of
this wireless connection was quite reliable showing
100% correct frame reception for even highly
attenuated signals.
Figure 9. Developed board supporting IR-UWB
wireless communication according to the
IEEE.802.15.4a
An approximate FER was measured for the differential
transmit signal of 54 mV peak-to-peak at the input to
the antenna firstly with the cable connection. As can
be seen in Figure 10, for the attenuations up to 20 dB,
all the 10000 frames sent received correctly indicating
good stability and functionality of the components and
their reliable interaction. For higher attenuations,
frame error rate increases as expected however, still
more than 92 % of the frames received with no error
for the attenuation exceeding 30 dB. It shows
reasonable sensitivity of the designed receiver being
near to -80 dBm. It was calculated from 54 mV peak-
peak voltage at the antenna input applied across 50 Ω
impedance. There is a good linear relation between the
attenuation introduced and the gain needed at the
receiver for the detection as illustrated with the Figure
10. Every time attenuation is increased by around 6
dB, the gain of the receiver needed to climb by two
steps which equals approximately to 6-8 dB. For
example, 30 dB attenuated receive signal required
nearly 36 dB gain (gain step=12) for achieving 94 %
correct detection.
10 15 20 25 3 0
92
94
96
98
100
Attenuation (dB)
Correctly received frame percentage
frame reception percentage
3
6
9
12
receiver gain step
Figure 10. Frame reception percentage for varying
attenuation of transmit signal and the receiver gains
needed
The synchronisation performance was shown to be
very satisfactory irrespective of the voltage averaging
integrator used at the receiver. It is always desirable to
have a reference signal with which the transmit signal
can be compared. For this reason, arbitrary waveform
generator N8242A from Agilent was used for
generating 499.2 MHz bandwidth analogue signal
comprising 2 ns Gaussian impulses fitting to the
standard under consideration. An external clock
generator was used since the required sampling
frequency is 998.4 MHz. A Matlab script which uses
rcosflt function for producing 2 ns Gaussian pulses
was applied to the generator. The generated signal
exhibits required shape and bandwidth making it
suitable to use as a reference for testing and
measurements. This baseband signal was then up-
converted to the frequency 7.9872 GHz with the
generator E8267D Agilent technologies the amplitude
of which can vary in a range of -130 dBm to 25 dBm.
Figure 11 visualises the generators used for producing
reference signal which radiated through antenna for
receiving it. This reference signal having the
amplitude of -30 dBm was received in distance over
5.5 m with the receiver developed showing again its
good sensitivity. Since the generator signal possesses a
bit larger amplitude around 70 mV than the developed
IR-UWB non-coherent receiver at IHP, it achieved
improved range in comparison to it.
Receiver gain step
7
Figure 11. Experimental setup used for generating
standard compatible reference signal
VII. Conclusion
An ASIC solution for IR-UWB supporting short range
wireless communication according to the standard
IEEE.802.15.4a was introduced. The complete system
consisting of three chips developed with the 250 nm
SiGe at IHP, Germany was tested on a board. The
components are high frequency frontend, integrator
and ADC and baseband. The board contains clock
distributing and power supplying circuitries. Initial
laboratory tests reveal that the ASIC implementation is
fully functional and can support currently wireless
communication in a distance of around 2.5 meter
showing an acceptable error rate performance. Up to
16 dB attenuated signal was received 100 % error free.
Even highly attenuated signals by more than 30 dB
were received with tolerable frame error rates. The
necessary gain for detecting the signal was depending
on the attenuation quite linearly.
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... A bit counter (PHR_bits, data_bits) increases by one after every symbol. The detection of the two bits within a symbol is made first looking at the energy level as a whole at the expected position without receiving every individual pulse [11]. Secondly, the received PN sequence at the located position is correlated with the newly generated one to resolve the polarity bit. ...
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A digital baseband was designed and implemented according to the standard IEEE802.15.4a both in FPGA and as well as ASIC. The baseband supports data rates 850 Kb/s, 6.81 Mb/s and 27.24 Mb/s running at the clock speed of 31.2 MHz. The transmitter and receiver were tested by introducing various distortions to the signal being received. The baseband was shown to be fully functional being able to receive even under heavy distortion. Both the synchronization and data detection performance are robust. The baseband tested with a FPGA was further made as an ASIC in the 250 nm BiCMOS technology from IHP, Germany.
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A voltage integrator which is followed by a successive approximation register (SAR) analog-to-digital converter (ADC) for an impulse-radio (IR) ultra-wideband (UWB) receiver is presented in this paper. A sequence of wideband impulses carries information in IR-UWB systems which are used for short-range wireless communication and localization. The radio frequency (RF) frontend provides baseband impulses to the input of the proposed circuit. The first stage is an in-tegrator that senses the impulses. Its output voltage depends on the number of received impulses and is converted to a digital code. The sequence of codes is passed to a digital processor that is able to retrieve the transmitted data. The integrating analog-to-digital converter operates with a sampling frequency of 62.4 MS/s i.e. the integration period is about 16 ns. The core consumes 16.2 mA from a 2.6 V supply. The integrated circuit is fabricated in the 250 nm SiGe BiCMOS technology SGB25V from IHP.
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Impulse Radio Ultra-Wideband (IR-UWB) communication system according to the standard IEEE.802.15.4a supporting non-coherent reception is discussed with the focus on the automatic gain controller (AGC). The performance of the transceiver is evaluated under noisy and common multipath channel environments. Simulation results confirm that a simple non-coherent, low power IR-UWB receiver can achieve the sensitivity of -70 dBm for the input signal with 250 MHz analogue using a 6 bit analogue to digital converter with a sampling frequency of 62.4 MHz. It presents the maximum achievable performance from the system under consideration where integrating circuit and slower analogue to digital converter are incorporated. The sensitivity of the receiver can be further improved by using a higher resolution ADC where -100 dBm received signal is still detected with 12 bit ADC.
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Using UWB for wireless short range, low rate communication is attracting growing interest due to its low power consumption and very high bandwidth. Moreover, it is able to offer accurate localization in the range of few centimeters. Considering these qualities, it is desirable to design an IR-UWB transceiver which consumes as small power as possible when it is applied for battery driven wireless sensors. For this reason, an IR-UWB transceiver based on the standard IEEE.802.15.4a was investigated in this paper with particular emphasis on its implementation, power consumption and area need for both FPGA and ASIC solutions. This paper presents results obtained with real hardware.
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This paper describes a monolithic integrated transceiver chipset intended for impulse radio (IR) Ultra-wide band (UWB) applications including indoor communication and indoor localization. The chipset operates in the higher UWB band centered at 7.68 GHz and it is optimized for a pulse bandwidth of about 1.5 GHz. The average pulse repetition rate of 60 MHz and an octagonal pulse position modulation (8-PPM) allow for raw data rates up to 180 MBit/sec. The available high bandwidth is used for precise indoor localization employing a dedicated time-of-arrival (TOA) measurement extension. This unit runs with an on-chip system clock of 3.84 GHz, which allows a measurement accuracy of 260 picoseconds. As demonstrated this UWB transceiver chipset is well suited for two-way ranging (TWR) in potentially harsh RF propagation environments. Under perfect line-of-sight conditions a spatial resolution of about 3.9 centimeter could be achieved.
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This paper describes an ultra-low power differential 7th order active-RC low pass filter (LPF). The proposed filter is ready for the use in Impulse-Radio (IR) Ultra-Wideband (UWB) IEEE 802.15.4a standard compliant transceivers. The circuit is composed of three biquadratic and one first order filter sections. The structure of the operational amplifier (op amp) is adopted to ensure high linearity demands of the design. The evaluation of the LPF was done both for the stand alone version and with the cooperation of other transceiver components inside the IR UWB receiver and the transmitter test circuits. The designed LPF can handle the signals with the peak-to-peak amplitude of 680 mV, has corner frequency of 180 MHz and consumes 3.2 mA from 2.6 V supply. The circuit is fabricated in 0.25 μm SiGe:C BiCMOS technology of the IHP. The chip size is 130×430 μm2.
Conference Paper
Using UWB for wireless short range, low rate communication has been attracting growing interest due to its low power consumption and very high bandwidth. Moreover, it is able to offer accurate localization in the range of few centimeters. Recognising these qualities, it is desirable to design IR-UWB transceiver which can draw minimum possible power when it is applied for battery driven wireless sensors. For this reason, in this paper, baseband design and performance of IR-UWB transceiver based on the standard IEEE.802.15.4a was investigated with particular emphasis on reducing power consumption. Synchronization algorithm that achieves 16 ns is presented and its performance is very promising offering nearly 100% synchronization for as low SNR as 8 dB. Different resolutions of analogue to digital converter (ADC) are investigated to find out the optimum with respect to power consumption and performance. 4 bit ADC was found to be the most optimal for the sample rate of 62.4 MHz. BER performance of pulse position modulation was evaluated under realistic channel conditions with multipath components.
Conference Paper
Ultra Wideband (UWB) has been gaining growing research and industry interests in many different areas of wireless communications. Among them using UWB as a radio interface for wireless sensor network is of high interest due to its precise localisation and low power consuming capabilities. In this paper we carry out quantitative analysis into the synchronisation performance of UWB when it operates under usual wireless channel environments. Simulation results confirm that coherent receiver needs around 10 dB less signal to noise ratio to achieve synchronisation compared to the noncoherent detection. Higher spreading factors lead to noticeable improvement for both coherent and noncoherent detection.
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This paper presents a fully differential baseband pulse generator intended for Impulse-Radio Ultra-Wideband (IR-UWB) direct up-conversion transmitter architectures. The generator provides impulse related binary phase shift keying (BPSK) and on/off keying (OOK) modulation in accordance with the IEEE 802.15.4a standard. The logic part of the generator runs on a clock of 499.2 MHz allowing direct generation of single preamble impulses as well as data impulse bursts. While the pulse generator is digitally controlled at the input, the output provides an analogue signal ready to be shaped by a low-pass filter (LPF) and up-converted to the desired channel.
Evaluation and optimisation of robustness in the IEEE
  • J Hund
  • S Olonbayar
  • R Kraemer
  • C Schwingenschloegel
J. Hund, S. Olonbayar, R. Kraemer, C. Schwingenschloegel " Evaluation and optimisation of robustness in the IEEE.802.15.4a standard ", ICUWB10, Sep. 2010, Nanjing, China
An ultra low power 7 th order PC- LPF for IEEE.802.15.4a standard compliant transceiver
  • O Klymenko
O. Klymenko, " An ultra low power 7 th order PC- LPF for IEEE.802.15.4a standard compliant transceiver ", 7th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2011