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... The architectures produced by this methodology can be classified as uniprocessor architectures. To exploit the parallelism in a given algorithm the methodology has been generalized so that it can be applied t o the simultaneous recursion form [15,16] . I n this paper the methodology is applied to the following forms: [2] Fixed nested recursion. ...

In this paper, we introduce a formal approach for synthesis of array architectures. Four different fovms are used t o express the input algorithm: simultaneous recursion, recursion with respect t o dsferent vari-ables, fixed nesting and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multi-plication algorithm is used t o obtain four different optimal architectures. The dtfferent architectures of this example are compared in terms of area, time, broadcasting and required hardware.

... The architectures produced by this methodology can be classified as uniprocessor architectures. To exploit the parallelism in a given algorithm the methodology has been generalized so that it can be applied t o the simultaneous recursion form [15,16] . I n this paper the methodology is applied to the following forms: [2] Fixed nested recursion. ...

In this paper, we introduce a formal approach for synthesis of array architectures. Four different fovms are used t o express the input algorithm: simultaneous recursion, recursion with respect t o dsferent vari-ables, fixed nesting and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multi-plication algorithm is used t o obtain four different optimal architectures. The dtfferent architectures of this example are compared in terms of area, time, broadcasting and required hardware.

... The architectures produced by this methodology can be classified as uniprocessor architectures. To exploit the parallelism in a given algorithm the methodology has been generalized so that it can be applied t o the simultaneous recursion form [15,16]. I n this paper the methodology is applied to the following forms: ...

The authors introduce a formal approach for synthesis of array architectures. The methodology provides two main features: completeness and correctness. Completeness means the ability to use the approach for any general algorithm. Correctness is achieved by using a set of transformations that are proved to be correct. Four different forms are used to express the input algorithm: simultaneous recursion, recursion with respect to different variables, fixed nesting, and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multiplication algorithm is used to obtain four different optimal architectures. The different architectures of this example are compared in terms of area, time, broadcasting, and required hardware

A formal design methodology is used to design a residue Number
System (RNS) processor. An optimal architecture for the residue decoding
process is obtained through this design approach. The architecture is
modular, consists of simple cells, and is general for any set of moduli

In this paper a formal design methodorogy is used to design a Residue Number System (RNS) processor. An optimal architecture for the residue decoding pro-cess is obtained through this design approach. The architecture is modular, con-sists of simple cells, and is general for any set of moduli. -1. Introduction A novel approach for synthesizing digital architectures has been introduced in[l-4]. The approach is supporting two essential features: completeness and correctness. Completeness means the abil-ity to use the approach for any general algorithm. Correctness is achieved through a unified formal set of transformations that transforms a high level algorithmic description to an RTL level architecture. A given algorithm is modeled using a new developed language termed Algorithm specif-ication language(ASL). The realization for-mat is based on representing the architec-ture by another developed language called Realization Specification Language (RSL). In order to support parallel architec-tures, the approach have been extended to include different forms of recursion[5-7]. Other forms of recursion such as: simul-taneous recursion, recursion with respect to several variables, nested recursion with fixed number of nestings and nested recur-sion with variable number of nestings are used for designing parallel architectures. In this paper, we use this formal design methodology for designing a Residue Number System (RNS) processor. Section 2 gives a brief description of the design methodology. Section 3 describes the formal design of a residue decoder. Section 4 offers conclusions.

The authors introduce a formal approach for synthesis of parallel
architectures. Four different forms are used to express the given
algorithms: simultaneous recursion, recursion with respect to different
variables, fixed nesting and variable nesting. Four different
architectures for the same algorithm are obtained. As an example, a
matrix-matrix multiplication algorithm is used to obtain four different
optimal architectures. The different architectures of this example are
compared in terms of area, time, broadcasting and required hardware. The
approach is providing two main features: completeness and correctness

A formal behavioral synthesis framework is introduced for
specification, simulation, and synthesis of digital signal processing
(DSP) algorithms. The given algorithm is represented using a newly
developed language called the algorithm specification language (ASL).
The components and connectivity of the synthesized architecture can be
represented in three different forms: a language called the realization
specification language (RSL), schematic captures, and PROLOG. PROLOG is
used as a user interface language between the user subsystem and the
synthesis subsystem. Algorithms of linear time complexity are introduced
for transferring between different representations

An approach is presented for high-level synthesis of digital
signal processing (DSP) algorithms. Two features are provided by the
approach: completeness and correctness. A given algorithm is represented
in a newly developed language termed the algorithm specification
language (ASL). ASL had the ability to describe any general algorithm.
An automatic procedure is used to transform an ASL representation into a
specific realization specification using a correctness preserving set of
transformations. The realization format is based on representing the
digital architectures by another language called the realization
specification language (RSL). Logic programming is used as a user
interface for the synthesis procedure

The major drawback of reported high level synthesis techniques is their limited applicability to a specific class of algorithms without extendibility to general algorithms and the lack of a formal approach to prove the correctness of the such techniques. In this paper, we introduce a novel approach for high level synthesis from μ-recursive algorithms. Two features are provided by the approach: completeness and correctness. Completeness means the ability to use the approach for any general algorithm. Correctness is achieved by using a set of transformations that are proved to be correct. A formal framework for the synthesis procedure has been developed which can be easily automated. A given algorithm will be represented in a new developed language termed Algorithm Specification Language (ASL). ASL has the ability to describe any general algorithm. An automatic procedure is used to transform an ASL representation into a specific realization specification using a correctness preserving set of transformations. The realization format is based on representing the digital architectures by a Realization Specification Language(RSL).