Conference Paper

Formalization of DSP Architectural Synthesis

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Conference Paper
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A formal design methodology is used to design a residue Number System (RNS) processor. An optimal architecture for the residue decoding process is obtained through this design approach. The architecture is modular, consists of simple cells, and is general for any set of moduli
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In this paper a formal design methodorogy is used to design a Residue Number System (RNS) processor. An optimal architecture for the residue decoding pro-cess is obtained through this design approach. The architecture is modular, con-sists of simple cells, and is general for any set of moduli. -1. Introduction A novel approach for synthesizing digital architectures has been introduced in[l-4]. The approach is supporting two essential features: completeness and correctness. Completeness means the abil-ity to use the approach for any general algorithm. Correctness is achieved through a unified formal set of transformations that transforms a high level algorithmic description to an RTL level architecture. A given algorithm is modeled using a new developed language termed Algorithm specif-ication language(ASL). The realization for-mat is based on representing the architec-ture by another developed language called Realization Specification Language (RSL). In order to support parallel architec-tures, the approach have been extended to include different forms of recursion[5-7]. Other forms of recursion such as: simul-taneous recursion, recursion with respect to several variables, nested recursion with fixed number of nestings and nested recur-sion with variable number of nestings are used for designing parallel architectures. In this paper, we use this formal design methodology for designing a Residue Number System (RNS) processor. Section 2 gives a brief description of the design methodology. Section 3 describes the formal design of a residue decoder. Section 4 offers conclusions.
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