Conference Paper

Formal Hardware Verification of VLSI Architecture Current Status and Future Directions

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Conference Paper
In this tutorial we present the area of formal verification of systems on Chips. The paper discuses the following topics: different approaches of formal logic such as first order bgic, high order logic, temporal logic. A case study of object-oriented paradigm is presented. A survey of the current research status is presented. The paper concludes with a section on the future directions.
Data
In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verification at different levels of hardware specification. The rule-based framework has been tested on the design of high speed adders.
Data
In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verification at different levels of hardware specification. The rule-based framework has been tested on the design of high speed adders.
Data
In this tutorial paper the area of formal verification of DSP VLSI architectures is presented. The paper discuses the following topics: production systems, formal logic, the equational approach, and the signal flow graph approach. Each approache is explained using one or more of the current available systems.
Conference Paper
Full-text available
In this paper a new formal hardware verification approach based on object oriented techniques is presented. The HOOVER system (Hardware Object Oriented VERification) is described. A cell library of different hardware components has been implemented as classes. Components in the cell library are described at the transistor level, gate level, logical level, and functional level. The verification of a CMOS inverter and 1-bit CMOS adder using HOOVER is given in the paper
Conference Paper
Full-text available
In this paper, the verification strategy of the PROVER environment is presented. The PROVER system (PROduction system for hardware VERification) uses CLIPS (C Language Integrated Production System). PROVER is a rule-based framework for formal hardware verification. The environment supports verification at different levels of hardware specification. The verification strategy is illustrated in this paper using a carry select adder as a case study
Conference Paper
Full-text available
In this tutorial paper the area of formal verification of DSP VLSI architectures is presented. The paper discuses the following topics: production systems, formal logic, the equational approach, and the signal flow graph approach. Each approach is explained using one or more of the currently available systems
Conference Paper
Full-text available
In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verification at different levels of hardware specification. The rule-based framework has been tested on the design of high speed adders
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