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Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications

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Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications

Abstract

Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications is a collection of world class paper articles addressing the following topics: Computer Networks: Access Technologies, Medium Access Control, Network architectures and Equipment, Optical Networks and Switching, Telecommunication Technology, and Ultra Wideband Communications. Coding and Modulation: Modeling and Simulation, OFDM technology , Space-time Coding, Spread Spectrum and CDMA Systems. Wireless technologies: Bluetooth , Cellular Wireless Networks, Cordless Systems and Wireless Local Loop, HIPERLAN, IEEE 802.11, Mobile Network Layer, Mobile Transport Layer, and Spread Spectrum. Network Security and applications: Authentication Applications, Block Ciphers Design Principles, Block Ciphers Modes of Operation, Electronic Mail Security, Encryption & Message Confidentiality, Firewalls, IP Security, Key Cryptography & Message Authentication, and Web Security. Control Systems and automation: Advanced and Distributed Control Systems, Automation, Expert Systems, Robotics, Factory Automation, Intelligent Control Systems, Man Machine Interaction, Manufacturing Information System, Motion Control, and Process Automation. Electronics and Power Systems: Actuators, Electro-Mechanical Systems, High Frequency Converters, Industrial Electronics, Motors and Drives, Power Converters, Power Devices and Components, and Power Electronics New trends in Automation and Communications: Biometric Authentication, Computer Forensics, Machine Vision, MEMS Sensors, Stenography, and Support for Mobility.
2007, XVI, 552 p.
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T. Sobh, University of Bridgeport, Bridgeport, USA; K. Elleithy, University of Bridgeport,
Bridgeport, USA; A. Mahmood, University of Bridgeport, Bridgeport, USA; M. Karim (Eds.)
Innovative Algorithms and Techniques in Automation,
Industrial Electronics and Telecommunications
Provides a virtual forum for presentation and discussion of the state-
of the-art research on computers, information and systems sciences
and engineering
Innovative Algorithms and Techniques in Automation, Industrial Electronics and
Telecommunicationsis a collection of world class paper articles addressing the following
topics:
Computer Networks: Access Technologies, Medium Access Control, Network architectures
and Equipment, Optical Networks and Switching, Telecommunication Technology, and
Ultra Wideband Communications.
Coding and Modulation: Modeling and Simulation, OFDM technology , Space-time
Coding, Spread Spectrum and CDMA Systems.
Wireless technologies: Bluetooth , Cellular Wireless Networks, Cordless Systems and
Wireless Local Loop, HIPERLAN, IEEE 802.11, Mobile Network Layer, Mobile Transport
Layer, and Spread Spectrum. Network Security and applications: Authentication
Applications, Block Ciphers Design Principles, Block Ciphers Modes of Operation,
Electronic Mail Security, Encryption & Message Confidentiality, Firewalls, IP Security,
Key Cryptography & Message Authentication, and Web Security. Control Systems and
automation: Advanced and Distributed Control Systems, Automation, Expert Systems,
Robotics, Factory Automation, Intelligent Control Systems, Man Machine Interaction,
Manufacturing Information System, Motion Control, and Process Automation.
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Article
Cyber-physical systems (CPS) are integrations of computation and control with sensing and actuation of the physical environment. Typically, such systems consist of embedded computers that monitor and control physical processes in a feedback loop. While modern electronic systems are increasingly characterized as CPS, their design and synthesis still rely on traditional methods, which lack systematic and automated techniques for accomplishment. Recently, IEC 61499 has been proposed as a standard for designing industrial process-control and measurement systems. It prescribes a component-based approach for developing industrial automation software using function blocks. Executable code can then be automatically generated and simulated from these function blocks. This bodes well for designers of CPS, who are more likely to be experts in specific industrial domains, rather than in computer science. The intuitive graphical nature and automatic code synthesis of IEC 61499 programs will alleviate the programming burden of industrial engineers, while ensuring more reliable software. While software synthesis from IEC 61499 programs is not new, the generation of efficient code from them has been wanting. This has made it difficult for function blocks to be used in software development for resource-constrained embedded controllers commonly employed in CPS. To address this, we present an approach that can generate very efficient code from function block descriptions. Experimental results from a benchmark suite shows that our approach produces substantially faster and smaller code compared to existing techniques.
Article
Our previous work on combining switches multistage interconnection network (CSMIN) makes use of distance tag routing algorithm to provide two correct disjoint paths for every source-destination pair. Our algorithm backtracks a packet to the previous stage and takes the other disjoint path in the event of a fault or a collision in the network. To eliminate the backtracking penalties of CSMIN, we propose a new design called fully-chained combining switches multistage interconnection network (FCSMIN). FCSMIN has the similar characteristics of 1-fault tolerance and two disjoint paths between any source-destination pair but it can tolerate at least one link or switch fault at each stage without backtracking. Our comparative analysis and results show that FCSMIN has the added advantages of destination tag routing, lower hardware costs than CSMIN, strong reroutability and lower pre-processing overhead.
Conference Paper
Full-text available
A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates multiprocessors, multiple memories, and other heterogeneous intellectual properties and interconnection with 51mW and 1.6GHz on-chip networks. The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. A network-in-package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications
Conference Paper
Full-text available
With the increasing complexity of system-on-chips, networks on chip (NoC) using multi-hop switching require low end-to-end latency for QoS guarantees. An arbitration look-ahead scheme is proposed to reduce the end-to-end packet latency in the NoC. Its packet arbitration at each switch is completed a few cycles in advance of the packet arrival. As a result, a packet bypasses the switch without the latency of input queuing and arbitration. This scheme is analyzed on a 4×4 mesh topology. A maximum 65% and average 26% latency reduction are obtained under random traffic. Latency reduction up to 36% is achieved under multimedia traffic.
Conference Paper
Full-text available
As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for Systems-On-Chip (SoCs) are rapidly increasing due to the inefficiency of traditional CAD tools. Relaxing the requirement of 100% correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires that SoCs be designed with some system-level fault-tolerance. In this paper, we introduce a new communication paradigm for SoCs, namely stochastic communication. The newly proposed scheme not only separates communication from computation, but also provides the required built-in fault-tolerance to DSM failures, is scalable and cheap to implement. For a generic tile-based architecture, we show how a ubiquitous multimedia application (an MP3 encoder) can be implemented using stochastic communication in an efficient and robust manner. More precisely, up to 70% data upsets, 80% packet drops because of buffer overflow, and severe levels of synchronization failures can be tolerated while maintaining a low latency.
Conference Paper
Full-text available
There are two types of models useful in the study of worm propagation for a given number of terminals in a trusted network i.e. deterministic and stochastic model. The deterministic models, also known as compartmental models are in the form of epidemic models. These epidemic models consist of different states called compartments so these models are also known as compartmental models. A closed (no inflow and outflow) donor control based compartmental model can be converted in to the stochastic model which is more realistic and also enables us to compute the transition probability from one state to other state. In this paper authors have presented a method for stochastic modeling of worm or virus propagation in trusted networks.
Article
Full-text available
An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-chip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 /spl times/5 mm/sup 2/ chip containing all the above features is fabricated by 0.18-/spl mu/m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.
Article
Increasing communication demands of processor and memory cores in Systems on Chips (SoCs) necessitate the use of Networks on Chip (NoC) to interconnect the cores. An important phase in the design of NoCs is the mapping of cores onto the most suitable topology for a given application. In this paper, we present SUNMAP a tool for automatically selecting the best topology for a given application and producing a mapping of cores onto that topology. SUNMAP explores various design objective such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints. The tool supports different routing functions (dimension ordered, minimum-path, traffic splitting) and uses floorplanning information early in the topology selection process to provide feasible mappings. The network components of the chosen NoC are automatically generated using cycle-accurate SystemC soft macros from xpipes architecture. SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs. Several experimental case studies are presented in the paper, which show the rich design space exploration capabilities of SUNMAP.
Book
From the Publisher: This is a new advanced reference work presenting compartmental models or flow models, from an applications perspective. Key applications discussed are: ecosystem models, fluid transfer, competition models, tracer kinetic experiments, and network flows. All important topics are presented in an accessible and integrated style: directed graphs, differential equations, Markov chains, and compartmental model constructions.
Conference Paper
Increasing communication demands of processor and memory cores in Systems on Chips (SoCs) necessitate the use of Networks on Chip (NoC) to interconnect the cores. An important phase in the design of NoCs is he mapping of cores onto the most suitable opology for a given application. In this paper, we present SUNMAP a tool for automatically selecting he best topology for a given application and producing a mapping of cores onto that topology. SUNMAP explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints. The tool supports different routing functions (dimension ordered, minimum-path, traffic splitting) and uses floorplanning information early in the topology selection process to provide feasible mappings. The network components of the chosen NoC are automatically generated using cycle-accurate SystemC soft macros from X-pipes architecture. SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs. Several experimental case studies are presented in the paper, which show the rich design space exploration capabilities of SUNMAP.
Article
The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.