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Formal design of RNS processors
Abstract
A formal design methodology is used to design a residue Number
System (RNS) processor. An optimal architecture for the residue decoding
process is obtained through this design approach. The architecture is
modular, consists of simple cells, and is general for any set of moduli
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A formal behavioral synthesis framework is introduced for
specification, simulation, and synthesis of digital signal processing
(DSP) algorithms. The given algorithm is represented using a newly
developed language called the algorithm specification language (ASL).
The components and connectivity of the synthesized architecture can be
represented in three different forms: a language called the realization
specification language (RSL), schematic captures, and PROLOG. PROLOG is
used as a user interface language between the user subsystem and the
synthesis subsystem. Algorithms of linear time complexity are introduced
for transferring between different representations
An approach is presented for high-level synthesis of digital
signal processing (DSP) algorithms. Two features are provided by the
approach: completeness and correctness. A given algorithm is represented
in a newly developed language termed the algorithm specification
language (ASL). ASL had the ability to describe any general algorithm.
An automatic procedure is used to transform an ASL representation into a
specific realization specification using a correctness preserving set of
transformations. The realization format is based on representing the
digital architectures by another language called the realization
specification language (RSL). Logic programming is used as a user
interface for the synthesis procedure
The major drawback of reported high level synthesis techniques is their limited applicability to a specific class of algorithms without extendibility to general algorithms and the lack of a formal approach to prove the correctness of the such techniques. In this paper, we introduce a novel approach for high level synthesis from μ-recursive algorithms. Two features are provided by the approach: completeness and correctness. Completeness means the ability to use the approach for any general algorithm. Correctness is achieved by using a set of transformations that are proved to be correct. A formal framework for the synthesis procedure has been developed which can be easily automated. A given algorithm will be represented in a new developed language termed Algorithm Specification Language (ASL). ASL has the ability to describe any general algorithm. An automatic procedure is used to transform an ASL representation into a specific realization specification using a correctness preserving set of transformations. The realization format is based on representing the digital architectures by a Realization Specification Language(RSL).
The authors introduce a formal approach for synthesis of array architectures. The methodology provides two main features: completeness and correctness. Completeness means the ability to use the approach for any general algorithm. Correctness is achieved by using a set of transformations that are proved to be correct. Four different forms are used to express the input algorithm: simultaneous recursion, recursion with respect to different variables, fixed nesting, and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multiplication algorithm is used to obtain four different optimal architectures. The different architectures of this example are compared in terms of area, time, broadcasting, and required hardware
A θ(1) algorithm for large modulo addition for
architectures based on the residue number (RNS) is proposed. The
addition is done in a fixed number of stages which does not depend on
the size of the modulus. The proposed modulo adder is much faster than
previous adders and more area efficient. The implementation of the adder
is modular and is based on simple cells, which leads to efficient VLSI
realization
DSP Architectures from Behavioral specifications: A Formal Approach0.0) (9.0) (u.0)(u.0) 1 2 3 4 Stage 3 Stage flog n1
- M A Bayoumi
and M. A. Bayoumi, DSP Architectures from Behavioral specifications: A Formal Approach,” Proceedings of the IEEE International symposium on Circuits and systems, pp. 1131-1134, May 1990. (0.0) (9.0) (u.0)(u.0) 1 2 3 4 Stage 3 Stage flog n1