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Synthesizing
DSP
Architectures from Behavioral Specifications:
A
Formal Approach
Khaled M. Elleithy and Magdy
A.
Bayoumi
The Center For Advanced Computer Studies
University of Southwestern Louisiana
Lafayette,
LA
70504,
U.S.A.
Abstract
This
paper introduces
a
formal behavioral synthesis frame-
work for spccifying, simulating and synthesis
of
Digital Signal
Pro-
cessing
(DSI’)
algorithms. The given algorithm
is
represented using
a.
iiew dcveloped language termed Algorithm Specification
1,n.rlgirn.ge (ASL). The components and connectivity of the syn-
t,lic,sised architecture can be represented in three different forms:
a
new
tlevcloped language termed Realization Specification Language
(RSI,),
schematic captures and Prolog. Prolog is used
as
a user
irIi,dacc In.nguage between
the
user subsystem and the synthesis
stilwyst,em. Algorithms
of
linaer time complexity to transfer
Iwtwren dill’erent representations are introduced.
Synthesising correct architectures
is
a
major problem. Ad-hoc
inetliods
were proved to rarely result in
a
totally correct design
spc~i:rlly
for
huge architectures. Testing
is
a
popular method that
is
tisrd
t,o
prove the correctness of systems for specific sets
of
iiiptit,s and outputs. With the current advances in VLSI circuits,
1,lic:rc is no I.csting procedure that
is
capable of accomplishing an
cxlin.ustive examination of complex circuits. Chips that may be
discovered to be faulty in future is
a
major consequence
of
testing
procedures'
limitations. Verification is another trend to prove
corrrcl,ness of an architecture. Verification techniques have some
irnplrmcntation problems in
a
practical environment due to the
tJimr
required even to verify the simplest architectures and
most.
I.rchniques are tailored
fcr
a specific class of architectures.
Ihly
works
in synthesis field were basically require the input
t,o
11:ivc
a
st,ructural description. CMU-DA
[l-31
require the input
I,O
l)c described using Instruction Set Processor Specification
(ISl’S)[‘l].
The
problem with such approachs
is
the requirement to
kiinw
t,he
Larget, architecture in advance in order to have the struc-
[,ti
r:i.l
tlcscrip
tion.
Synthesising
a
DSP
algorithm from a behavioral description
tising
a
programming like language have been reported in
[5-91.
I~l:inie1[5]
uses Pascal
as
a
behavioral description language.
A
nurnbrr
of rcstrict,ions are imposed on the input description: the
clcsrriptioii
should be parameterless and nonrecursive, certain data
t.yprs
a.rr
only allowed, and certain arithmetic operations are not
:illowcd IIARP[G] uses Fortran
as
the behavioral description
1:ingiiagc. The designer is responsible for determining the facility’s
word length and the composition
of
units. Restrictions are
impos(d
on the input specification such
as:
only certain data types
arc
allowcd, subroutine and fiinction calls are not allowed, and cer-
t,a.in functions are omitted. Communicating Sequential Processes
(CSI’)
is
uscd
as
a
description language by Philips [7,8]. Using a
CSP
:IS
a
description language means that the designer
is
responsi-
1)Ir
for specifying the operatians sequencing and commtmications
aniong
different units. Applif,ative languages have been used
for
lwli;i,vioral description
of
an algorithm. JohnsonlS] has presented
;III
;i.pproa,rh
for
transforming
a
system described in thc: form
of
Iinmr recursion equations to digital designs.
Tlie scope of this paper
is
a
formal synthesis framework
for
IHI’
architectures. Those sysi.ems have special features to be con-
sidrrcd
such
as:
[I]
12)
I>SP
architectures are based on fixed functions.
Algorithms are data-independent,
so
control can be hard-
wired. The most efficient hardware solutions directly reflect
the
data-flow inherent in the algorithm.
[J]
Processor throughput is more important than processor
latency. Throughput
is
achieved by pipelining and functional
parallelism.
Several systems has been developed for high level synthesis of
VLSI architectures from
DSP
algorithms[l0-16]. Those approaches
have concentrated on resolving and optimizing several architectural
issues such
as
using
a
single fixed architecture with
a
pakameteriz-
able data path and control unit, selecting one from
a
set of these
units,
or
trying to use kind
of
multiprocessor systems.
Also,
most
of
these systems are only applicable
to
special class of algorithms.
Our
new approach addresses two issues:
Completeness
and
Correct-
ness.
This paper presents
a
formal high level synthesis framework
which
is
applicable to
a
wide and general class of algorithms. The
synthesis system is composed of two subsystems: synthesis subsys-
tem and user-interface subsystem
as
shown in Figure
1.
Prolog
output
4°F
Product
ransiurmatio
w
Schematic
LI
brary
Fig.
1.
System Overview
The given algorithm
is
specified in
a
new language, termed
ASL, which
is
based on precursive functions. ASL is capable of
specifying any algorithm using
a
limited number
of
constructs.
Several researches have been reported for specifying the input algo-
rithm. Imperative languages have been used such
as:
Fortran[6],
Pascal[5],
ISPS[l,2],
and VHDL[17]. Applicative langusges have
CH2868-8/90/0000-1131$1.00
0
1990
IEEE
Authorized licensed use limited to: University of Bridgeport. Downloaded on February 24,2010 at 12:54:43 EST from IEEE Xplore. Restrictions apply.
been used such
as:
Recursion equation based specification[g] and
Temporal Logic[l8,19].
The design specification language must be simple and semant-
irally well characterized. It must permit writing specifications using
a few predefined objects and concepts
as
possible. Specifications
must not be prematurely committed to particular implementations.
Current hardware specification languages are far from this ideal.
The idea of representing an algorithm using
a
functional
representation was introduced by Kleene[SO] in which any function
from numbers(strings) to numbers(strings) can be ccnstructed
using very primitive functions and combining them in a specific
manner. Our approach for specifying an algorithm depends on
using
p-
recursive junctions
as
a frame-work.
The Language consists of
Initial Functions
and
Opera-
tions.
Initial functions are:
zero, projection,
and
successor
functions. The zero
function returns the value zero. The
pro-
jection
function has a
K
argument and
is
used to choose argu-
ment
i.
The
successor
function which increments its input by
one. The three operations are
Composition, Recursion,
and
Unbounded minimization.
Although the constructs are very
primitive, complex constructs can be used through
a
developed cell
library. Units that have been designed through this design metho-
dology can be added to the cell library. ASL has the following
characteristics:
(1)
Simple and semantically well characterized.
(2)
It permits writing specifications using a few predefined objects
and concepts.
(3)
It is a suitable tool for formal synthesis.
(4)
It supports
a
hierarchical design methodology.
(5)
It supports formal verification of the initial specification.
(6)
It is complete.
A complete description of the language syntax can be found in[21].
A
transformation technique is developed to transform an
algorithm represented in ASL to a specific realization language,
termed RSL. The RSL version specifies the components and con-
nectivity of the digital architecture that realizes the algorithm.
Every construct in ASL has zn isomorphic representation in RSL,
which is the basis
of
the automated transformation. That transfor-
mation algorithm is proved
t,o
be correct. Everything in the
sys-
tem
is
built from certain primitives. The proofs of correctness are
applied to these primitives.
A
hierarchical proof is used for ensur-
ing correctness at different levcls.
The realization introduced here
is
described
at
the arcliit,ec-
tural level. The physical parameters of the circuit are
not.
addressed at this level of specification. The tjiming
is
not expressed
explicitly, but implicitly in terms of registers
.
The symbol
p
is
used to represent a register. If it is required to initialize the register
to
a
certain value
p,
then this
is
represented
as
pg.
(I)
If
unit
is
a
certain component that is used
in
t2he system, and
znp
is
any input for unit, then we can use this input explicitly
using the following syntax: unitinp
Also an output(out) of unit can be used as follows:
unit
Out
(2) Identifiers starting with upper case letters are used to represent
units that will be further expressed at lower levels. Identifiers start-
ing with lower case letters wiil be used to express Basic functions.
Identifiers starting with lower case letters are used
also
to represent
constants, while those starting with upper case letters are used to
represent temporary variables used in computation.
(3)
Register: If it
is
required to use a register
a
that
is
initialized to
a value
p,
then this is expressed as
pa*.
As
an Example the expres-
sion pisuc(I) means that suc unit has the register
1
connected to
its input with a value 2
as
the register initial value. hit statement
is
a
RSL
expression that can be used separately to express that
register
alhpa
is
initialized to value
p
as follows:
Another version of Init can be used to denote the initialization of
Init
(aJ)
more than one register at the same time, this is represented
as
fol-
lows:
The previous statement means that
n
registers are initialized
in
parallel such that register
cy1
is
initialized with the value
9,,
regis-
ter
cvl?
is
initialized with the value
p2,
etc
...
Notice that using regis-
ters
is
the only way to represent time in our circuits. It is assumed
that
all
registers are synchronized using
a
global clock.
(4)
Constant values are expressed using registers. If it
is
required
to have
a
constant value (c) in the circuit, then this is represented
as
pc.
If it is required to represent the zero function directly the
following specification
is
used:
Result
=
zero
zeroReody
=
zeroControl
InifP
(@l,P,
;
%PZ
;
'
'
'
;
a,
,Pn
1
23TransformationJlm
A
transformation algorithm is based on using
a
one-to-one
mapping procedure. The algcrithm takes an ASL representation
and transform each of ASL constructs to an equivalent RSL
representation and an equivalent architecture implementation. The
algorithm has
a
Q(n)
time complexity where
n
is the number of
ASL constructs used to represent the algorithm. Table
I
shows the
relation between each ASL ronstruct and equivalence RSL con-
structs. The complete algorithm
is
given in[?l].
24
Cell
Librazy
A
library of the basic functions
is
defined starting from the
initial functions to be used in the definition of larger fuiictions.
This approach is
useful
for
building
a
cell library
to
support the
automated synthesis system. All the basic functions that hay?
been designed using the proposed approach can be used for specify-
ing other functions. This technique supports a hier?rchical design
methodology in the sense th,it. the specification can lie stopped at
any level
as
long
as
the lower levels were previously dcfined. \\hen
Bcisic
fuuctions are used to represent another functions,
each
Basrc
Junction
i>
written in
a
LZi.
F,uamnle
POU!(12
,O)
=
qC(1).
If
we consider that pro
is
a
basic function, then the factorial
(potu(n
,772))
is
defined as follows:
rol
(arg1,arg2>arg3)
=
&(sa(
arg
1,
av2,
arg3),1/33( Q'gl,arg2, w3))
pou!(n
,112
+I)
=
pro
13(
12
,m
,pow(n
,m)).
From the previous definition we see that, we do not express the
function
pow
in terms of inifial Junctions, but we use
a
as
a
basic
function, which may
be
expressed explicitly in a library
of
basic functions.
-
The user interface environment that
is
used for the synthesis
process will be implemented
as
a
logic programming environment.
The logic programming environment supports specifying, simulat-
ing, and testing Digital Signal Processing
(DSP)
systems[22]
Backtracking and pattern matching of Prolog are employed for
simulation and testing, respectively. Prolog provides homogeneity
to the developed system
as
it supports hierarchical development
and mixing
of
description at various hierarchical levels.
Prolog
has
powerful facilities
for
simulation. Using the same code without any
modifications we can perform different types of simulation: for-
ward, backward
or
bidirectional. Simulation can be performed on
different levels and it can be mixed. Circuits specified in Prolog can
be specified at different levels, mixed levels and any degree of
details without too much complexity.
Two transformation algorithms are used to link the synthesis
subsystem and the user interface subsystem. The purpose of these
two algorithms is to allow the user to use the syst'em through the
logic programming environment without the need to know the
details of ASL and RSL. The two algorithms are
as
follows:
(1)
The first algorithm is used to transform between Prolog and
ASL. This transformation algorithm allows the user to specify
his
algorithm in terms of Prolog. Table I1 shows the transformation
i\le;orithm.
(2)
The second algorithm
is
used
to transform hetween
1132
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Name
zero
Projection
Successor
CO
m
p
osi
t
ion
Recursion
U
n
bounded
hfinimization
ASL
l(n)
=
n+l
f
(argljarg2,
. . .
,awn)
=
min
m
(s.t
z(argl,arg2,
.
.
.
,argn,m)
=
0)
=
0
if
m
does not
ezists
RSL
Result
=
mux(arg,,
....
,
argt
#
i)
"JZControi
mUZR~od~
=
Initp(O,m
;
I,argl
;
2,arg2;
. . .
;
n,argn)
SllCcontro~
=
g(W)'cady
I
=
p;+'
suc(1)
Ready
=
eq?(1,
m)
Result
=
comp(G,I,pgiEl Result
#
y)
Initp(0,m
;
l,argl
;
2,arg2
;
. . .
;
n,argn)
Result
=
po
suc(Result)
Ready
=
eq?(O,
g(G,Result))
Table
I.
Transformation Algorithm bwtween
ASL
and
RSL.
1,11(~
I1SI,
:md
prolog.
This
algorithm allows us
to
have the output
(.irciiiI.
specifcd
in
Prolog.
111
t,l~is paper a framewo1.k
for
synthesising
DSP
systems from
lwli:iviora,l descriptions has ken introduced. The proposed frame-
work
II:IS
t,lic.
following ad~a~~tages: It
is
suitable for lerge prob-
I(*IIIS,
1.11e
tr:~nsformation algorithms are linear, it does not require
1.0
k
iiow
(.he
t,arget,
architect,ure in advance, there are no restric-
I
ionh
iniposd
on t,he input tl:script,ion, the technique can be fully
:iiit,oii~:i~ed,
the designer
is
not responsible
for
specifying thc
oper:it
1011s
sequeiiciiig and communications among different un~ts,
:1nd
I'Iic
approach
is applicable to any general algorithm.
R.eferences
/I]
I,.
.I.
Ilafer and A. C. Parker, "Automated Synthesis
of
Digi-
hl
Ilardware,"
IEEE
Trans. Computer,
Vol.
(3-31,
pp.
93-109,
lpel),
1982.
T.
J.
Iiowalski and D.
E.
Thomas, "The VLSI Design Auto-
innt,ion Assistant: Prototype System," Twenty Design Auto-
~n;it,ion
Conf. Proc., Miami,
pp.
479-483, 1983.
131
'r.
-1.
Iiowalski, "The
VLSI
Design Automation Assistant:
A
I\iiowlc,tlgc-ba.sed Expert System," Ph.D. thesis, CMU, 1984.
1.1)
hl.
R.
Darbacci, "Instruction Set Processor Specifications
(ISI'S):
The Notation and its applications," IEEE Trans.
(!ornput.ers,
Vol.
C-30,
pp.
24-40,
Jan. 1981.
1'11
Steps
2
2
2
2
5
3
-
151
H.
Trickey, "Flamel: A High Level Hardware Compiler," IEEE
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T.
Tanaka,
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to Silicon," IEEE Trans. on computer-aided design, vol.
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no. 6.,
pp.
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M.
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pp.
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1988.
C.H.
van Berkel,
M.
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'VLSI
Program-
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and processors, pp. 152-156, Oct. 1988.
S.
D. Johnson, "Synthesis
of
Digital Designs from Recursion
Equations," Ph.D. Dissertation, Comp. Sc. Dept., Indiana
Uni., 1983.
[lo]
J.
Rabaey,
Ss.
Pope, and
R.
Broderson, "An Integrated
Automatic Layout Generation System," IEEE Trans.
Computer-Aided Design, vol. CAD-4, July 1985, pp. 285-296.
[11]
P.
Rutez et al., "Computer Generation
of
Digital Filter
Banks," IEEE Trans. Computer-Aided Design, vol. CAD-5,
pp.
256-265,
Apr.
1986.
1121
J.
Schuck,
M.
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[13]
B. Petersen, B. White, D Solomon, and
M.
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[6]
[7]
[S]
[9]
ICCAD, pp. 500-503, NOV. 1986.
1133
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Name
Zero
Projection
Successor
Composition
Recursion
Unbounded Minimization
z1
code
z,
code
y
code
code
for
z
code
for
y
t(Arg,,
. . .
,Arg,,O,Result)
I-
z(Argl,
.
.
,Arg,,Result).
z(Argl,
.
. .
,Arg,,M,Result)
I-
All
is
Af-1
,
z(Arg,,
.
. .
,Arg,,Afl,Temp),
y(Arg,,
.
,Arg,,iUl,Temp).
7'.i11e
11.
Transformation Algorithm bwtween ASL and Prolog.
[I41 G. Goesens et al., "A CAD Methodology for Mapping DSP
algorithms onto MP castom Architectures,"
P~oc.
IEEEl
CCAS 86, May 1986.
(151
J.
Rabaey,
H.
De Man,
J.
Vanhoof, G. Goosens, and
F.
Catthoor, "CATHEDRAL-11: A Synthesis System for Mul-
tiprocessor DSP systems," in Silicon Compilation, D. Gajsk,
Ed., Addison-Wesley, pp. 311-360, 1988.
1161
B.
Haroun and
M.
I.
Elmasry, "Architectural Synthesis for
DSP Silicon Compilers," IEEE Trans. on Computer-Aided
Design, Vol.
8,
Apr..1989, pp. 431-447.
[17]
L.
F.
Saunders, "The
IBM
VHDL Design System," Twenty
Fourth Design Automation Conf., pp. 484-490, 1987.
[18]
G. V. Bochmann, "Hardware Specification with Temporal
Logic: An Example," IEEE Transactions on Computers,
Vol.
C-31,
March 1982.
[I91 B. Moszkowski,
"A
Temporal Logic for Multilevel Reasoning
about Hardware," Compt. ter, Vol. 18, pp. 10-19, Feb. 1985.
[20]
S.
C. Kleene, "Genera: Recursive Functions of Natural
Numbers," Mathematische Annalen, pp. 727-742, 1936.
Vumber Of Steps
3
:21]
I<.
RI.
Elleithy and
M.
A.
Bayoumi
"A
Frame-work for High
Level Synthesis of Digital Architectures from precursive
Algorithms Using
A
L06;'c
Programming Interface." Accepted
for inclusion in the
ACM
1990 Computer Science Conf.,
Washington, DC, Feb. 1990.
[22]
M.
A.
Bayoumi and K. M. Elleithy, "A Logic Programming
Approach
for
DSP architectures Design," Proc. of the
22nd
IEEE Asilomar Conf. on Signals, Systems and Computers,
vol.
2,
pp. 753-757, Nov. 1988.
1134
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