Conference PaperPDF Available

Area Estimation for DSP Algorithms

Authors:

Abstract

In this paper we present a method to estimate the layout area of DSP algorithms that are designed using the standard cell methodology. The circuit description is given as a netlist of standard cell library modules. The area occupied by the circuit can be estimated prior to the actual layout phase. Area estimation before final layout is important for design evaluation and for the prediction of the chip floorplan
Area
Estimation
for
DSP
Algorithms
Khaled
M.
Elleithy
Computer Sc.
&
Eng. Department
University of Bridgeport
Bridgeport, CT 06601
elleithv@ bridseDort.edu amin@ccse.kfupm.edu.sa
Alaa A. Amin
Computer Eng. Department
King Fahd University
Dhahran
3
1261, Saudi Arabia
Abstract-- In this paper we present a method to estimate the layout area of
DSP
algorithms that are designed using the standard cell methodology. The circuit
description
is
given
as
a
netlist of standard cell library modules. The area occupied
by the circuit can be estimated prior to the actual layout phase. Area estimation
before final layout is important for design evaluation and for the prediction of the
chip floorplan.
THE MATHEMATICAL
FRAMEWORK
Constructive and analytical approaches can be used to estimate the area
occupied
by
a standard
cell
design. In constructive approach, the design
is
modeled
as
a data structure on which partitioning algorithms are applied to
estimate the total area. In analytical approach, probabilistic models for the
behavior of the wiring different between cells are used [I-2]. Analytical
approach is much faster
in
terms
of
computation requirement and easier
to
program.
The analytical model used
in
this work is an extension of
the
work
in
[2].
For
the wire average length estimation, there are also constructive and
analytical approaches for its estimation.
For
the analytical case the estimation of
the average wire-length
[3]
and its distribution have been published
[4].
For
the
constructive case there also published results
[5].
For
this work, analytical
approach for the wire length estimation is also used.
Earlier work on area estimation
has
been done through analytical,
nondeterministic models. One
of
the early attempts was the observation of E.
F.
Rent of IBM who developed an empirical formula, which relates the number of
components in partitioned subcircuit to the number
of
external components
of
that subcircuit. The relation is
known
as
Rent's rule [6] and is given by:
where
P
is the number of external connections to the subcircuit,
K
is the average
number of pins per block, and
r
is Rent's constant and B is the number
of
components in the subcircuit.
Heller et
al.
[7],
developed a stochastic model for the prediction
of
the
wiring space needed for a
1-D
placement of cells. The model predicts the
successful routability
of
the placement. They proposed a heuristic
to
extend the
model for
2-D
placement.
Donath
[SI
has
shown
from simple theoretical considerations that the
distribution
f,
of
the wire lengths
for
a good two-dimensional placement on
a
square Manhattan grid is
of
the form:
P=
KB'
(1)
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__
f,
=g/kY,(15k<-
L)andfL
=:O(k>L).
(2)
2p+y
-3. (3)
where
’)’
is
related
to
the Rent partitioning exponent
p
giver!
by the relation
Feuer
[3
J
predicted the wire length distribution and estimated the averagc
wire length in an
IC
laid
out
with Standard Cell approach. The main results
of
his work
is
that if the partitioning of a logic graph follows Rent’s rule, then the
average wire length distribution takes the forms:
I
a(5-a)
cp--2
z,
=53-a)(4-a)
(1-cp-‘)
(4)
(I-a)(S-a)
;
Le=&
C
(5)
(3
-
a)(4
-
a)
where
p
is Rent’s constant and
C
is the number of components in a subcircuit
contained in a region of radius
R
and
a
=
2(1-
p).
L,
and L,are the average
wire lengths
for
internal and external connections respectively. The average wire
length including both internal and external connections
is
given by:
(6)
I
(2-a)(5-a)
CP-:
E
=
Jz
(3
-
a
)(4
-
a
) (
1
+
c p-1
)
El-Gama1
[
1
J
has extended the
work
of
Heller
et
al.,
to accommodate
2-D
gate arrays.
A
two-dimensional stochastic model for gate array channel wiring
is
studied. The gate array
is
modeled as
a
2-D
lattice. Wire segments emerge from
lattice points and assumed to follow a Poisson distribution
of
the form:
Ak
e
-A
k!
PJX=k]
=-
,
k=0,1,2..
(7)
’where
X
is the number
of
wires emanating from a grid point, is the Poisson
parameter and
k
is
the number of wires emanating from
a
grid point. Wires are
assumed
to
travel either horizontally
or
vertically with no jogging or diagonal
runs. The direction taken by each wire is determined by flipping a fair coin.
Many wire length distributions such as Poisson, exponential and geometric have
been suggested in the literature.
Sastry [9] proved that the “ideal” distribution in the limiting case of
optimum placement is the exponential distribution in the continuous domain.
Since the geometric distribution
is
the counter part
of
the exponential
distribution in the discrete case:
-
P(L=I)=
pq‘-‘,
with
I/p=/
and
q=l-p
(8)
-
where
1
is the average wire length. Based on these assumptions the upper bound
on the channel density is:
-
.“
-
1A
W=-
L
-
where
1
is
the average wire length and
distribution.
is the parameter for the Poisson
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Sastry
[4]
modeled a gate array as a grid of channel intersection and the
problem
of
wiring space requirement estimation is reduced to the estimation
of
the dimension
of
these intersections. This was achieved by classifying the wires
at an intersection into six different types, each modeled as a Poisson distributed
random variable. He also established an equivalence relation between Rent’s
rule and the wire length. The distribution was found to be
of
Weibull family
given by:
I
-
11-
1
PY
P
L=-(-yr(-)
where p is Rent’s constant,
Y
is the average number of pins per cell, and
r(x
+
1)
=
x!
is the gamma function. The asymptotic channel width
for
N
was found to
be:
OQ,
(N
is the number
of
logic modules
in
the array)
Y
where
p
=
j-(E[L’]-
1)
and
is the second moment of the wire
length random variable
L.
The routability is defined as the probability that
neither the vertical nor the horizontal channel width requirements are exceeded.
These statistically dependent events are approximated events modeled by two
independent events and an asymptotic probability is derived for each of them.
The vertical routability is found to be:
w-2p
wherea
=
-
fi‘
The horizontal routability is symmetrically defined.
Kurdahi
[2]
proposed a model
for
standard cell area estimation, which is
accurate within
10
percent
of
the actual areas
of
designs.
AREA ESTIMATION
FOR
STANDARD CELL LAYOUTS
The estimation
of
the layout area occupied by standard cell design is
1.
The active area which is readily known from the netlist description
of
the
2.
The area of the pads which are also known from the circuit description.
3.
The area of the interconnect, which is not trivial and need needs a
composed
of
three parts:
circuit.
probabilistic modeling approach to be estimated.
Placement
The standard cell layout consists
of
two phases:
1.
Partitioning
the design by assigning cells to row.
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2. Placement by assigning locations to cells.
There are two phases in placement:
a)
Initial placement phase.
b)
Iterative improvement phase.
Examples
of
the placement techniques such as row assignment, pair linking,
clustering, force directed, bipartioning and row folding are reported in literature.
In this work,
row
folding is used for area estimation. The placement is done as
follows:
1.
Perform I-D placement as an initial placement such that the average wire
2. Fold the single row placement such that area and shape constraints are
length is minimized.
satisfied.
Cells are placed in rows of roughly the same size.
Equivalent pins are available on both sides of each row.
All cells have equal distance between two consecutive equivalent pins
or
pin pitch.
The cell width is a multiple of pin pitches.
All nets are two-pin nets. An n-pin net can be decomposed in an n-1 two
pin nets
or
an appropriate wire length distribution is used such as negative
binomial.
The total number of cells in the block is
N.
The total number
of
pin slots in the block is
w.
Placement
is
done using the
I-D
place and fold technique.
The model assumptions are as follows:
0
The Single
Row
Case
The following assumptions are done for single row placement:
Pin slots are numbered 1,
2,
3,
...,
w
from left to right.
Wires travel from left to right.
The length of a wire is assumed to be a random variable
L,
with geometric
probability density functionp,
(I)=
Pr{L=I)=pq'-'.
The density at point x, d(x) is defined as the number of wires crossing a vertical
cutline. The expected value of the density function is given by
N
WP9
E
(d(x)
=
-
(1
-
q"
)(1
-
q
*-+I))
(13)
The maximum local density occurs at
X,,,
=
The Multiple
Row
Model
The single row model is extended to multiple row placement by folding the
I-D placement to n row 2-D placement. The initial row is "snacked" into
IZ
rows. The number of pin slots per row is
Y
=
-.
The average value,
E{W,J)}
of track density at x is given by:
W
n
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For
n
even,
For
n
odd,
.................
(14)
The above equations give an estimate for
dn(x)
at a cutline
x.
The track
requirement is approximated by:
ma
(
W,,
(4)
1
(15)
ISxSr
The maximum density is done
by
setting the derivative
of
E{Wj)}
to zero
and solve
for
x. The derivation that will follow is
for
n
even. The same steps can
be followed for the case where
n
is odd.
g(x)=
-[E(
Wn(x)}]
can be expressed
as:
d
d(x)
g(,t)=k,&
+
k2q2"
+
k3
q2r-lr+2
+
k4
q2r-lr+2&
(I
6)
where:
kl =kj(I-qW-q2r+qwq2'
kZ=ks(-2
+n-nq2r+2q2nqrqw-2r)
k3=-ks(2q2r+2qw-n-2qwq2r+nq2r-2q2rq"2r)
k4=ks(i
-q2r-qw+qwq2r)
-2
~gqi
npq(-l+
q2y
k5
=
The solution for the equation
where
p
is the root
of
the equation:
which can be reduced to:
k,z3 +k2z4 +k3(qr)2q2 +uc,q2(qr)2=o
(18)
k22
+
klZ3
+
a2
+
b
= 0
(19)
where:
a
=
k4q
S+b
b
=
kH2'**
This equation can be solved using Newton-Raphson
(slope)
search method
or
any other numerical method such
as
the
Bisecriott
method. Parameters
k,,
kh
k3
and
k4
depend on the design
for
which the area has to be estimated. Once this
equation is solved
for
x, it is substituted
in
Equation
14
to
find
ma
[E,,{x)]*
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Estimating the Feedthroughs Space
The Feedthroughs account for space needed in the horizontal direction.
A
feedthrough cell is inserted in
a
row when a wire runs more than one row. The
estimation of the space by the vertical wires requires estimating the number of
Feedthroughs in the cell rows. The expected number of feed through in row
k
is
given by:
The maximum number of Feedthroughs
max[E{FJ]
occurs in row
k,,=
The maximum number of Feedthroughs is given by:
The maximum width contributed by the feedthrough cells is given by:
Where
F&,,id,h
is
the width of the feedthrough cells which are assumed to be the
same for all cells.
W{FT)=FTwidth
"[E{Fi}]
(23)
CHIP
TOTAL
AREA
The chip total area is given by:
Chb-Area
=
Active-Area
+
RoutinCArea
(24)
The IO-Area is readily known from the circuit netlist and is not counted for in
the area estimation. The chip area is given by:
Chip-Area
=
H.
W
(25)
As an approximation the channel width and cell width are equal. In that case, the
height of the chip is given by:
H=
d.max[E{W,,(x))]
+
n.Cell-Height
(26)
where
d
is the track width,
n
the number of rows and Cell-Height is the height
of
standard cells. The width of the chip is given by:
Where Cell-Pitch is the distance between two consecutive inputJoutput pins of a
cell. This distance is assumed to be constant for all cells. For a square shape:
W
=H
When this condition is satisfied, the number of rows is given by:
W
=
W{FT}
+I:
Cell-Pitch
(2
7)
(W{Fg
-d.maxEKl(x)
}I&
\I(w(F7)
-
d.maxE{&(x)}
15
+
4wCel~HeigM?ell_Pitc9
2CelLHeigh
t
n=
(28)
The area of the chip is
Chip-Area
=
[d.(E{W,,(x)))
+
n.Cell-Height].[ W{FT}+r.Cell-Pitch]
(29)
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The unknown parameters in this expression are:
d
The physical track width.
Cell-Height:
The cell height is given in the input netlist.
Cell-Pitch:
The cell pitch
is
given
in
the input netlist.
Max[E{
W,,(x)}]
is the maximum channel density.
The unknown parameters, which are used indirectly in the expression, are:
P:
Rent's constant which
is
assumed
to
take the same value in each design
P=0.65.
L
:
The average wire length.
-
1
a
=2(1-P)
p==
q=
1-p.
(30)
L*
N:
The total number
of
cells in the design.
w:
The total number
of
pin slots in the design.
n
:
The number
of
rows in the design
W
r=
-
:
The number
of
pin slots per row.
C:
The total number
of
standard cells in the design.
n
AREA
ESTIMATION
ALGORITHM
The algorithm to estimate the area occupied by a design
starts
with
extraction
of
the parameters specific to the design.
Extract-Circuit-Parameters( C)
Intput:
Circuit netlist
C
Output:
Number
of
cells
N,
the total number
of
pin
slots
w,
Average wuelength
L
,
Cell-Height,
Cell-Pitch,
the physical track width
d.
-
Read the circuit netlist
C;
Record the total number
of
cells
N,
Compute the number pin slots
w;
Record the cell height
(Cell-Height);
Record the cell pitch
(Cell-Pitch);
Record the physical track dimension
d
Extract-Rent-Parameter(C);/*
P
assumed to be
0.65)
Calculate the average wire length
Z
Rent's parameter
P
is
assumed to be constant
for
all designs
(P=0.65).
For
proper
area estimation, a procedure
Extract-Rent-Parameter
is devised
to
extract
P
for
each design. The procedure
to
estimate the total area
of
the design
is given below.
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-
~~
Zstimate-Area(N,
w,
L
,
Cell-Pitch, Cell-Height,
d,
FTh
WO)
nput:
Number
of
cells
N,
the total number
of
pin slots
w,
Average
virelength
z,
Cell-Height, Cell-Pitch,
the physical track width
d,
An
nitial estimate of the track
he number
of
density
WO,
and an initial estimate
of
Feedthroughs FTo,
in
the layout.
Calculate
p
and
q;
max[{E{Fl}]= FTo;
Compute the initial Number of rows /*Equation
29
*/
/*The Objective is to have a square layout
*/
While
H
#
W
/*Equations
26
and
27
*/
Find
x,~;
/*equation
17
*/
Find max[E{W,,(x))] ./*equation
14*/
Compute max[{E{Fl}]
/*
Equation
22
*/
Compute
H
/*Equation
26
*I
Compute
W
/*Equation
27
*I
/*use equation
30
*/
maxlE{W,fx)l1
=
WO
end /*While
*/
CASE
STUDY
The following algorithm
for
Concurrent Read Concurrent Write (CRCW)
sorting of
N
elements is based on
the
idea of sorting by enumeration
[lo].
The
position
of
a given element of
S
in the sorted sequence is determined by
computing ci, the number
of
elements smaller than
si.
If two elements si and s,
are equal, then si is taken to be the larger of the two if i
>
j
;
otherwise sj is the
larger. Once
all
the ci have been computed for all elements, each element si is
placed in the (1
+
ci
)@
position of the sorted sequence.
CRCW
Algorithm
SteD
1:
for
i=l
to
N
do
in
parallel
for
j=l
to
N
do
in parallel
P(i,j) writes 1 in
ci
P(i,j) writes
0
in
ci
if(Si
>
Sj)
or
(Si
=
Sj and I
>
j)
then
else
end-if
end-for
end-for
Stee
2:
for
i=l
to
n
do
in parallel
P(i,l) stores
Si
in position l+ci of
S
end-for
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VLSI
Mapping
to
Event
Logic
Mapping of the algorithm to event logical based on the procedure given
in
[11,12]. In realizing the CRCW sorting algorithm
in
event logic, the following
assumptions are made:
1. The algorithm is realized for the case of four 4-bit numbers.
2.
The inputs of the circuit are:
0
Four 4-bit numbers
(
Ext. <1..4>.
<5..8>,
<9..12>, <13..16>
)
A
global reset signal is routed to all “CLR’ inputs of various elements, e.g.
C-Element, G-LaTChes, eTC.
An External input Request “R” laTChes all numbers into a set of 4-input
registers
(
IN1
-
IN4
).
3. The outputs of the circuit are:
The sorted four numbers as stored in 4-output registers
(
S1
-
S4
).
These
outputs are connected to external pads.
A global acknowledge <Final-Ack> signal which is also connected to an
external output pad.
0
3. The pinout of the chip is thus as follows:
4.
1
vcc
1
GND
16
1
Input Request
16
1 Output Acknowledge
1
Global Reset Input
The input four 4-bit numbers
The sorted four output 4-bit numbers
The actual implementation
of
the chip and the application
of
the estimation
algorithm show realistic overall chip height and hence a better area estimate
within
10
%
for this example and several other examples.
CONCLUSIONS
In this paper,
an
algorithm for estimating the area for standard cell designs is
presented: The algorithm is an extension
of
the work presented by Kurdahi[2].
The extension presented
in
this paper is used to estimate the total chip area
taking into consideration the maximum channel density and the maximum
number
of
feedthroughs. We have used the average wire length model
developed by Feuer
[3],
which is more suitable for use in standard cell design
style
as
compared to the gate arrays average wire length model adopted
in
[2].
We have further developed the average track density function of
Kurdahi
to
derive a formula for the location of the highest track density (x,). Another
formula for the number of
rows
in
a standard cell design
“n”
which results
in
a
more realistic overall chip height and hence a better area estimate was
developed.
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ACKNOWLEDEGEMENTS
The second author would like to acknowledge the support of King Fahd
University
of
Petroleum and Minerals.
References
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in
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pp.
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Feuer, “Connectivity of Random Logic,”
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AH,
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M. Elleithy, and A.
A.
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M.
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Book
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This book “Design and Analysis of Algorithms”, covering various algorithm and analyzing the real word problems. It delivers various types of algorithm and its problem solving techniques. It stretches an outline on analyzing the algorithm and identifying the efficiency based on the time and space complexity. It contributes an idea over analyzing the real world problems to representing the data of the problem and applying the next level algorithm to achieve the goal of the problem.
Article
Full-text available
In this paper a new approach fro implementing CIRCAL algorithm using event logic is presented. A high- level description of an algorithm is expressed in CIRCAL, a formal parallel hardware description language. The approach employs a transition signaling convention and a request-acknowledgment protocol under the bundled data model. The mapping approach is a syntax-directed one that will parse various CIRCAL constructs to their corresponding event logic. The mapping methodology is illustrated by an example.
Article
It is shown from simple theoretical considerations that the distribution f//k of wire lengths for a good two-dimensional placement on a square. Manhattan grid should be of the form f//k equals g/k** gamma (1 less than equivalent to k less than equivalent to L) and f//k approximately equals 0(k greater than L), where gamma is related to the Rent partitioning exponent p by the equation 2p plus gamma approximately equals 3. Three placements were investigated and the distribution functions for wire length were found to follow the above relationships.
Conference Paper
A stochastic model is developed for estimating wiring space requirements for one-dimensional layouts. This model uses as input the number of devices in the complex to be wired, the average length of a connection, and the average number of connections per device, to compute the probability of successfully wiring the devices as a function of the number of tracks provided. A heuristic approach is used to extend this model to the two-dimensional case, and tested against experimen-tal studies. Satisfactory agreement is found between a priori calculations of track requirements for the two-dimensional case against global wiring solutions for artificially generated problems, and for some layouts of actual logic complexes.
Article
The standard cell design style is investigated. Two probabilistic models are presented. The first model estimates the wiring space requirements in the routing channels between the cell rows. The second model estimates the number of feedthroughs that must be inserted in the cell rows to interconnect cells placed several rows apart. These models were implemented in the standard cell area estimation program PLEST (PLotting ESTimator). PLEST was used to estimate the areas of a set of 12 standard cell chips. In all cases, the estimates were accurate to within 10% of the actual areas. PLEST's estimation of a chip layout area takes only a few seconds to produce, as compared with more than 10 h to generate the chip layout itself using an industrial layout system
Conference Paper
An accurate model for the prediction of interconnection lengths for standard cell layouts is presented. On the designs in the test suite estimates are within 10% of the actual layouts. The model abstracts the important features of placement, global routing, and channel routing. The predicted results are obtained from analysis of the net list. No prior knowledge of the functionality of the design is used. Accurate prediction of the interconnection length is useful for estimating the actual layout area, for evaluating the fit of a logic design to a fabrication technology, and for solving placement and routing algorithms
Article
A stochastic model for estimating measures of placement and routing on gate arrays is presented. Three important problems are addressed: estimating the dimensions of the routing channels, estimating the routability of a channel given the number of tracks, and determining the distribution and moments of wire lengths. In the context of wiring space estimation, exact and asymptotic formulas for the dimensions of routing channels are presented. Next, an expression for the probability that a routing channel with a given number of tracks will be routable is derived, and its asymptotic properties are examined. Finally, a model that characterizes the relationship between wire length distributions and partitioning of logic is developed. The model provides a firm mathematical basis for Rent's rule from which the distribution of wire lengths can be determined. That is, Rent's rule, or in general any similar relation, contains all the information about wire lengths. Based on this, estimates for the average wire length are derived. Numerical results from both simulated and real chips are presented.