Formal Verification of DSP VLSI Architectures: A Tutorial


Formal Verification of DSP VLSI Architectures: A Tutorial

If you want to read the PDF, try requesting it from the authors.


In this tutorial paper the area of formal verification of DSP VLSI architectures is presented. The paper discuses the following topics: production systems, formal logic, the equational approach, and the signal flow graph approach. Each approache is explained using one or more of the current available systems.

No file available

Request Full-text Paper PDF

To read the file of this research,
you can request a copy directly from the authors.

ResearchGate has not been able to resolve any citations for this publication.
Full-text available
The book is written to introduce all Electrical Engineering and Computer Science students to integrated system architecture and design. Combined with individual study in related research areas and participation in large system design projects, this text provides the basis for a graduate course-sequence in integrated systems. MOS devices and circuits are considered along with integrated system fabrication, data and control flow in systematic structures, the implementation of integrated system designs, the overview of an LSI computer system, the design of the OM2 data path chip, architecture and design of system controllers, the design of the OM2 controller chip, system timing, highly concurrent systems, and the physics of computational systems. Attention is given to alternative control structures, the stored-program machine, microprogrammed control, algorithms for VLSI processor arrays, and hierarchically organized machines.
Conference Paper
Full-text available
A new formal hardware verification approach for digital signal processing architectures based on a production system environment is introduced. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). A cell library of different hardware components has been implemented. Components in the cell library are described at the transistor level, circuit level, gate level, logical level, and functional level. An example of carry select adder using PROVER is given
A data structure is presented for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by C. Y. Lee (1959) and S. B. Akers (1978), but with further restrictions on the ordering of decision variables in the graph. Although, in the worst case, a function requires a graph where the number of vertices grows exponentially with the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. The algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. Experimental results are presented from applying these algorithms to problems in logic design verification that demonstrate the practicality of the approach.
The Viper microprocessor designed at the Royal Signals and Radar Establishment (RSRE) is one of the first commercially produced computers to have been developed using modern formal methods. Viper is specified in a sequence of decreasingly abstract levels. In this paper a mechanical proof of the equivalence of the first two of these levels is described. The proof was generated using a version of Robin Milner’s LCF system.
HOL is a version of Robin Milner’s LCF theorem proving system for higher-order logic. It is currently being used to investigate (1) how various levels of hardware behaviour can be rigorously modelled and (2) how the resulting behavioral representations can be the basis for verification by mechanized formal proof. This paper starts with a tutorial introduction to the meta-language ML. The version of higher-order logic implemented in the HOL system is then described. This is followed by an introduction to goal-directed proof with tactics and tacticals. Finally, there is a little example of the system in action which illustrates how HOL can be used for hardware verification.
In this paper trends in CAD for application specific IC's (ASIC) are discussed. Shortage of skilled silicon designers, too long time to market and too low level of design as in standard cells and gate arrays, lead to a design strategy whereby system design is strictly separated from silicon design. (Meet-in-the-middle design). System designers will use interactive, knowledge based synthesis tools adressing a number of well defined target architectures to be generated from a formal specification language. Architectures are defined as a connection of a well defined set of reusable and parameterizable modules which are predesigned by silicon specialists. This is no longer done on a CALMA type environment but on an interpretative symbolic programming environment. This environment supports automatic parameterization and generation of layout, timing and testing views as well as automatic adaptability to new technology rules. Verification will be shifting away from costly simulation to knowledge based verification, based on a formal definition of design styles and automatic theorem proving. This will require multiprocessor workstations unifying high speed graphics and imperative, declarative and symbolic programming styles. A major problem with this methodology will be the (re)education of design engineers in order to design hardware the « soft» way.
The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesize synchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operational silicon compiler for bit-serial digital filters. Cathedral-II is based on a ??meet in the middle?? design method that encourages a total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program, a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automated reusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicon design and generates functional and timing models for verification at the module and chip levels.
The results of an assessment of the functionality and performance of tools with different architectural approaches are presented. The goal was to gain insight into the advantages and disadvantages of the various architectures. The tools evaluated in the study were (1) the Automated Reasoning Tool for Information Management (ARTIM), (2) the C Language Integrated Production System (CLIPS), (3) the Knowledge Engineering System (KES), (4) Level 5, and (5) VAX OPS5. Emphasis was on tools implemented in languages other than Lisp. KES and Level 5 were found to be inadequate for an application that required constructive problem solving, but both tools could be expected to provide improved performance for problems based on a heuristic classification approach due to their backward-chaining orientation. On the other hand, ART-IM, CLIPS, and VAX OPS5 might prove less effective for heuristic classification problem solving than for synthesis because they lack support for backward chaining. The results reinforce the fact that all expert system tools have strengths and weaknesses and that no single tool is dominant for a wide spectrum of applications or over a wide range of functionality
FM8501: A verified Microprocessor
  • W Hunt
  • B Brock
[ l l ] Hunt, W. and Brock, B., "FM8501: A verified Microprocessor," Technical Report 47, Inst. for Comp. Science, Univ. of Texas, Austin, Feb. 1986.
Artificial Intelligence and the design of Expert System, The BenjaminKummings publishing Company
  • George F Luger
  • William A Stubblefield
George F. Luger, William A. Stubblefield, Artificial Intelligence and the design of Expert System, The BenjaminKummings publishing Company, 1989.
  • Vlsi Design
VLSI Design," Revue Phys. Appl., vol. 22, January 1988, pp. 31-45.
SILAGE: a High Level Language and Silicon Compiler for Digital Signal Processing A Computational Logic
  • P Hilfinger
  • R Boyer
  • J Moore
Hilfinger, P., "SILAGE: a High Level Language and Silicon Compiler for Digital Signal Processing," Proceedings IEEE 1985 Custom Integrated Circuits Conference, Portland, May 1985, pp. 213-216. [lo] Boyer, R. and Moore, J., A Computational Logic. Academic Press, 1979.
DIALOG: An Expert Debugging System for MO § VLSI DesignsWOMBAT: A New Netlist Comparison Program
  • H Man
  • I Bolsens
  • E Meersch
  • J Cleynenbreughel
  • R Spickelmier
  • A Newton
Man, H., Bolsens, I., Meersch, E., and Cleynenbreughel, J., "DIALOG: An Expert Debugging System for MO § VLSI Designs," IEEE Transactions on Computer Aided Design, CAD-4, no. 3, June [14] Spickelmier, R. and Newton, A., "WOMBAT: A New Netlist Comparison Program," Digest of Technical Papers ICCAD-83, pp. 170-1 7 1.