From Intel VT-x to MIPS: An ArchC-based Model to Understanding the Hardware Virtualization Support

Abstract

Due to the benefits provided by virtualization and parallel processing, such as concurrent execution of multiple operating systems, the performance of servers has grown a lot. Intel VT-x is a hardware support
proposal capable of simplifying Virtual Machine Monitors (VMMs), increasing the performance of virtualized systems. This technology includes definitions of new data structures, new forms of CPU operation, and a new Instruction Set Architecture (ISA). Therefore, in order to understand how Intel VTx works, a didactic simulation environment is very important. So, the goal of this paper is to present an extended model of MIPS R3000 based on ArchC (an architecture description language), with the main features of Intel VT-x. This proposed model, a teaching methodology and how to use this model to simulate and understand virtualization are the main contributions of this paper.

Full text

From Intel VT-x to MIPS: An ArchC-based Model to Understanding the
Hardware Virtualization Support
*
Manuela K. Ferreira, Henrique C. Freitas
†
, Philippe O. A Navaux
Informatics Institute, Universidade Federal do Rio Grande do Sul, Brazil
{mkferreira, hcfreitas, navaux}@inf.ufrgs.br
Abstract
Due to the benefits provided by virtualization and
parallel processing, such as concurrent execution of
multiple operating systems, the performance of servers
has grown a lot. Intel VT-x is a hardware support
proposal capable of simplifying Virtual Machine
Monitors (VMMs), increasing the performance of
virtualized systems. This technology includes
definitions of new data structures, new forms of CPU
operation, and a new Instruction Set Architecture
(ISA). Therefore, in order to understand how Intel VT-
x works, a didactic simulation environment is very
important. So, the goal of this paper is to present an
extended model of MIPS R3000 based on ArchC (an
architecture description language), with the main
features of Intel VT-x. This proposed model, a teaching
methodology and how to use this model to simulate
and understand virtualization are the main
contributions of this paper.
1. Introduction
IBM developed the first Virtual Machine (VM) in
order to achieve an improved system composed of
sharing physical resources [1]. The IBM's
virtualization is a well-defined concept since 1960's,
and it has been largely used currently.
The virtualization offers benefits like concurrent
execution of different Operating Systems (OSs) with
dynamic load balancing. It increases the system
resource utilization, allowing a system manager to
configure the environment where a guest OS will run.
Through virtualization there are many possibilities
such as legacy OS execution; test of applications on a
virtual environment; and isolation of untrusted
applications of unknown quality. These features
improve the system security and prevent software
failures from a VM to affect other VMs. In addition,
they can be used to construct a system software for
scalable computers that have anywhere from 10 to 100
processors. Through physical resource abstraction, 10
real processors can appear to application software as 1;
or 1 processor can appear as 10 [2].
Once confined to specialized server and mainframe
systems, virtualization is now becoming more broadly
available. Currently, new processor architectures have
presented more execution units, high frequencies, and
multiple processing cores. Consequently, processor
proposals [3] have improved the performance of
virtualization systems to a large number of companies.
Intel VT-x is the Intel Virtualization Technology
for IA-32 processors that provides hardware
virtualization support in order to simplify the Virtual
Machine Monitors (VMMs) and to increase the
performance of virtualized systems [4]. This
technology includes definition of new data structures,
new forms of CPU operation and a new Instruction Set
Architecture (ISA). Therefore, in order to understand
how Intel VT-x works, a didactic simulation
environment is very important.
There are new teaching methodologies using
computers as a pedagogical tool. In this context, the
use of simulators is highly recommended, since they
aid students to visualize how the modeled system
operates [5]. At this point, Intel VT-x has important
and interesting features to simulate.
In Computer Architecture courses, the MIPS
processor approach has been used to show the main
architecture features, such as: instruction set, pipeline
organization, memory hierarchy, and I/O system. Since
MIPS is a well-known architecture, it was chosen to be
extended in order to understand the hardware
virtualization support.
Therefore, the goal of this paper is to present an
extended model of MIPS R3000 with the main features
of Intel VT-x, and how to use this model to simulate
* This research is supported by Microsoft Innovation Center.
†
On leave from Pontifícia Universidade Católica de Minas Gerais
(PUC Minas), Belo Horizonte, Brazil, cota@pucminas.br
In: Workshop on Computer Architecture Education, WCAE 2008, Beijing, China, June 21-25, pp. 9-15, 2008
(in conjunction with ISCA 2008)

and understand the virtualization technology. This
extended model is based on an architecture description
language called ArchC [6].
This ArchC model can be used for teaching
hardware virtualization support in undergraduate and
graduate courses. For instance, advanced architecture
courses describe modern technologies; and certainly, a
simulation environment based on an open architecture
description and hardware virtualization can motivate
the students.
Considering the importance and impact of
virtualization technologies in computer architecture,
the main contribution of this paper is related to the
teaching methodology and activities described in
Section 4. Through this methodology, the proposed
model and the subset of virtualization instructions can
be used in current courses in order to improve the
understanding of main related concepts.
This paper is organized into the following sections:
ArchC Overview, MIPS-vt ISA Proposal, Teaching
Methodology and Activities, Conclusions and
Acknowledgment.
2. ArchC Overview
Due to the large possibilities of design decisions for
single-core and multi-core processor architectures, an
Architecture Description Language (ADL) can aid
professors in teaching activities. ADLs [6][7][8][9]
have been developed to model processor architectures
in order to improve the design, or to identify bugs and
performance.
ArchC is an ADL that can automatically generate
simulators using the hardware description language
SystemC. ArchC is capable of describing processor and
ISA design and memory subsystem. Memory
hierarchies can be declared, containing several levels
of memories and caches. Caches can be configured to
simulate different set associativities, write polices,
replacement strategies, and line size [10].
SystemC is a class set in C++ that extends the
language to allow hardware and system modeling.
Although SystemC supports many computing models,
communication and abstraction levels; it is not possible
to extract from a processor description all necessary
information to experiment and evaluate a new ISA [6].
The goal of ArchC is to improve the abstraction for
SystemC models. ArchC provides enough information,
at an appropriate abstraction level, to allow designers
explore and check a new architecture by software
framework automatic generation like assemblers,
simulators, deployment and communication interfaces.
A processor architecture description in ArchC is
divided into two parts: i) in the instruction set
architecture description (AC_ISA), the designer
provides details about instruction formats, size and
names, combined with all necessary information for
decoding and behavior of each instruction; ii) in the
Architecture Resources (AC_ARCHC) description, the
designer depicts about storage devices, pipeline
structure, memory hierarchies, etc. Based on these two
descriptions, ArchC generates a behavioral architecture
simulator written in SystemC [10].
2.1. ArchC-based Works
This sub-section shows ArchC-based works, and
their main contributions for computer architecture
education.
In [10], ArchC is presented as a support tool for
computer architecture courses, and its main features
are related to the following design options: i) single-
cycle (functional) model, ii) cycle-accurate (pipeline)
model, and iii) memory hierarchies.
The work [11] describes the cache configuration
exploration using ArchC. ArchC was extended to
support more details of a memory system. As a result
the Sparc-V8 processor model had its memory
organization optimized for an image processing
application.
The current version of ArchC [12] is capable of
simulating (using SystemC) a multi-core processor. In
[13], ArchC was extended in order to provide a
mechanism to support multiprocessor platforms. The
main contribution for educational activities is related to
the efficient design exploration.
This work presents a didactic ArchC model based
on MIPS ISA description in order to understand the
typical hardware virtualization of Intel VT-x.
3. MIPS-vt ISA Proposal
The MIPS R3000 original architecture description
[12][14] extended with new structures and instructions
based on Intel VT-x [15] was named MIPS-vt.
The MIPS architecture was chosen since it can be
considered a simple and regular RISC processor [14].
Hence, like all RISC architecture, MIPS has a small,
regular and simple instruction set with operands
located in register banks.

Normal
Operation
VMX root
VMX
non-root
VMX Operations
VMXON
VMXOFF
VMLAUNCH
VMRESUME
VMCALL
Figure 1. Transitions in Intel VT-x
The model used in this paper is a MIPS R3000
simplification. This model has 32 32-bit general-
purpose registers, a program counter and two special-
purpose registers of 32-bit for multiplication and
division. There are three types of instruction, which
have 32-bit, with the following fields:
•
immediate: op (6-bit), rs (5-bit), rt (5-bit) and
imm (16-bit);
•
jump: op (6-bit) and addr (26-bit);
•
register: op (6-bit), rs (5-bit), rt (5-bit) shamt
(5-bit) and func (6-bit).
Intel VT-x is the Intel Virtualization Technology
for IA-32 processors that provides hardware
virtualization support. It is composed of a set of
structures and instructions called Virtual Machine
Extensions (VMX). VMX has a new data structure
called Virtual Machine Control Structure (VMCS).
Each launched VM has a VMCS to save its context,
but only one will be the active VMCS of the physical
processor.
This technology provides two new forms of CPU
operation: VMX root operation and VMX non-root
operation. A VMM runs in VMX root operation; and
its guest OSs run in VMX non-root operation,
unprivileged in certain ways. The transition from
VMX root operation to VMX non-root operation is
called VM entry, and the transition from VMX non-
root operation to VMX root operation is called VM
exit. Both forms of operation support all four
privileged levels, allowing a guest OS to run at its
intended privileged level [4]. The behavior of VMX
instructions is presented in Figure 1 and summarized
as follows [15]:
•
VMXON and VMXOFF: to enable and disable
the VMX instructions, respectively;
•
VMLAUNCH, VMCALL and VMRESUME:
to create a VMCS launching a new VM; to exit
from VMX non-root operation mode; and to
resume the VM execution entering in VMX
non-root operation mode; respectively;
• VMCLEAR, VMPTRLD and VMPTRST: to
clear the active VMCS; to save the reference of
active VMCS at memory; and to load a VMCS
reference for active VMCS register;
respectively;
•
VMREAD and VMWRITE: to read and write
fields in active VMCS.
In order to provide virtualization support based on
Intel VT-x, MIPS-vt has a VMCS structure, which is
referenced at memory. This specific processor structure
is capable of keeping each VM context. Figure 2
illustrates the VMCS declaration.
struct VMCS{
bool active; //control fields
int launch_state;
set<string> VM_exit_cond_instruction;
int rb[RB_MAX_REG]; //save the context
int pc;
VMCS();
void clear();
};
Figure 2. VMCS struct definition in vmcs.h file
Figure 3 shows the new bank of four registers; all
of them consist of 32 bits word. These registers control
the operation modes. Two of these registers keep the
references to the active VMCS and to the host VMCS.
Other two registers inform if the processor is in VMX
root or VMX non-root operation mode, and if the
VMX instruction is activated.
In accordance with virtualization instructions,
MIPS-vt has in its AC_ISA description a subset of
VMX instructions based on MIPS 3000 original
instruction formats. The added instructions (Figure 4)
are the following: Type_R: VMXON, VMXOFF,
VMRESUME, and VMCALL. Type_I: VMLAUNCH,
VMCLEAR, VMPTRLD, and VMPTRST. VMREAD
and VMWRITE instructions were not implemented,
and VMCS fields, such as list of instructions that cause
VM exit, were not changed. Hence, there is a standard
VMCS configuration to all VMCSs. The reference to
VM that is represented by a VMCS is a field initialised
before VMLAUNCH using VMWRITE. Since
VMWRITE was not implemented, in order to define

the referenced VM by a VMCS, the VMLAUNCH
instruction, which has no parameter in Intel VT-x
specification, is changed to have an address parameter.
This address is a label in the beginning of VM source
code.
AC_ARCH(
r3000){
/*... old definitions ...*/
/*new registers
* RS[0]=VMX root(0) or non-root(1) modes
* RS[1] = VMXON (1) or VMXOFF(0)
* RS[2] = reference to active VMCS
* RS[3] = referece to host VMCS */
ac_regbank
RS:4;
/*... old definitions ...*/
ARCH_CTOR
(r3000) {
ac_isa
("r3000_isa.ac");
set_endian
("big");
};
};
Figure 3. Register definition in r3000.ac file
AC_ISA
(r3000){ /*old definitions*/
//new instructions
ac_instr<
Type_I
>
vmclear, vmptrld, vmptrst,
vmlaunch;
ac_instr<
Type_R
>
vmxon, vmxoff, vmcall,
vmresume;
ISA_CTOR
(r3000){
//Virtualization instructions
vmxon.
set_asm
("vmxon");
vmxon.
set_decoder
(op=0x00, func=0x3A);
vmxoff.
set_asm
("vmxoff");
vmxoff.
set_decoder
(op=0x00, func=0x3B);
vmcall.
set_asm
("vmcall");
vmcall.
set_decoder
(op=0x00, func=0x3C);
vmclear.
set_asm
("vmclear %imm(%reg)",imm, rs);
vmclear.
set_decoder
(op=0x3D);
vmlaunch.
set_asm
("vmlaunch %expR4A", imm);
vmlaunch.
set_decoder
(op=0x30);
vmresume.
set_asm
("vmresume");
vmresume.
set_decoder
(op=0x00, func=0x3F);
vmptrld.
set_asm
("vmptrld %imm(%reg)",imm, rs);
vmptrld.
set_decoder
(op=0x39);
vmptrst.
set_asm
("vmptrst %imm(%reg)", imm, rs);
vmptrst.
set_decode
r(op=0x38);
};
};
Figure 4. New instructions in file r3000_isa.ac
The MIPS-vt model can be used to simulate
programs allowing students to visualize how the
modeled system operates. Debug commands can be
added in r3000-isa.cpp to print on screen information
during the execution or to save a program trace to be
analyzed. The behavior of VMXON instruction is
presented in Figure 5. This behavior has several trace
commands that are boldface type.
Next section presents a teaching methodology and
an experimental simulation used in a computer
architecture classroom, based on MIPS-vt.
void ac_behavior( vmxon ){
dbg_printf("vmxon\n");
printf("RS_VMX_OP=%s\n",
RS.read(RS_VMX_OP)? "ON": "OFF" );
//test if already it's VMX ON
if(!RS.read(RS_VMX_OP)) {
//set active VMCS as invalid
RS.write(RS_VMCS_ATIVO, 0);
printf("RS_VMCS_ATIVO=%d\n",
RS.read(RS_VMCS_ATIVO));
//set VMX as ON
RS.write(RS_VMX_OP,1);
printf("RS_VMX_OP=%s\n",
RS.read(RS_VMX_OP)? "ON": "OFF" );
}//test if already is VMX non-root operation mode
else if(RS.read(RS_VMX_MODO) ==
VMX_NON_ROOT){
/******save context***/
//set the operation mode root.
RS.write(RS_VMX_MODO,VMX_ROOT);
printf("RS_VMX_MODO = %s\n",
RS.read(RS_VMX_MODO)? "non-root": "root");
printf("VMEXIT – Ilegal (VMXON) in
VMX_NON_ROOT mode\n");
}
};
Figure 5. Behavior of VMXON instruction
4. Teaching Methodology and Activities
In accordance with the MIPS-vt ISA described in
the previous section, the teaching proposal is divided
into the following parts: methodology and activities.
The main motivation is to show how the virtualization
instruction subset is capable of improving concepts
related to processor architecture and hardware
virtualization support. The methodology and
experiment depicted in this section are the main
contribution of this paper, since the teaching of
virtualization ISA are not common in current courses
of computer architectures.

4.1. Teaching Methodology
This teaching methodology is divided into three
parts: work environment, suitable time, and proposed
activities.
Due to the main features and advantages described
in the previous sections, the environment of
architecture description and simulation is the ArchC
language based on SystemC. Through this
environment, students are capable of designing and
simulating ISA, and understanding the main impacts
on the processor architecture. The MIPS architecture is
currently used in many courses due to its didactic
concept. For this reason, the environment is based on
MIPS ISA and the reference book [14].
The suitable time is when to introduce the hardware
virtualization concept, and so, the MIPS-vt proposal.
Considering that [14] has a chapter organization
focusing on a didactic division, and the MIPS-vt is a
new design that demands a previous knowledge, the
suitable time is after the following topics: MIPS ISA,
computational arithmetic, performance evaluation, data
and control paths, pipelining and memory hierarchy.
After these topics a student is capable of understanding
the reasons of instruction formats and impacts on data
and control paths; moreover, how to increase the
performance through pipelining and memory
hierarchy. At this moment, the hardware virtualization
concepts are introduced in order to show the MIPS-vt
instructions. As a consequence, the students are
capable of understanding how the new virtualization
instructions improve the performance, and the
influence of modifications on the architecture units,
such as register bank, and data and control paths.
The next phase is related to teaching activities or
how to use the work environment. This proposal is
responsible for supporting the concepts, the MIPS-vt
design, the ISA behavior and verification, and the
performance evaluation. This next sub-section also
shows an experimental simulation highlighting context
switching, the iteration between VMs, an assembly
program, ArchC statistics, and a trace execution.
4.2. Teaching Activities
This sub-section describes how to use the proposed
work environment as an educational aspect.
Considering the importance of design, verification and
evaluation, in this phase the students work with all
concepts depicted in the previous chapters of the
source book [14], focusing on a virtualization
instruction set architecture.
First of all, the virtualization concepts are
introduced, showing an overview of hardware and
software approaches [1][2][4]. At this point, virtual
machine monitors and specific instruction set
architectures (e.g., Intel VT-x) are described in
accordance with advantages and disadvantages to
achieve a good performance.
An ArchC-based model [16] is used in order to
show a new ISA design with the same Intel features
capable of supporting the hardware virtualization.
Through this description model, the students are
presented to all ISA modifications to support a MIPS
instruction format (Figure 4), and all modifications in
the pipeline organization in order to support new
functional blocks, such as specific register banks
(Figure 3), or new data and control paths.
Considering the importance of behavioral
verification, through ArchC the students can alter the
description in order to identify bugs of design or new
instructions responsible for supporting features not
described yet. An alternative is an available description
architecture previously modified by the professor,
motivating students to study and find description
problems and how to solve them.
Different application codes or different ISA
descriptions also motivate students to understand the
importance of performance evaluation. As a
consequence, an exercise based on ISA exploration, in
order to reduce the execution time of specific
virtualization instructions (Figure 8), improves the
previous knowledge about performance and how an
application can influence in design decisions of a
virtualization instruction set architecture.
As result, this methodology also prepares the
students to develop other works related to design,
verification and evaluation of specific ISAs, in
accordance with tools and source book depicted in
work environment.
Next sub-section shows an experimental simulation
in order to exemplify a typical exercise based on
context switching. Source codes are available in
project web page [16].
4.2.1. Experimental Simulation
Figure 6 shows a diagram of execution example.
This diagram shows an example of VMs' context
switching using Intel VT-x. VM1 is launched, and
after its execution it is interrupted. Thus, VMM
launches the VM2 and, after VM2 execution, VMM
returns to VM1 execution.
Figure 7 shows the main part of the assembly code
used in this experiment, which is available at [16].
First, the VMX instructions are enabled. Thus, the

active VMCS is set with VMCS reference that belongs
to VM1. The VM2 is launched and its code is very
similar to VM1 launched code; only references to
VMCS and to VM source code have to be changed.
After, the VM1 execution is resumed. The VM1 code
has the label vm1, and the instruction VMCALL is
executed before the factorial loop in order to interrupt,
purposely, the VM1 execution.
VMM
VM1
VM2
VM1
VMLAUNCH
VMLAUNCH
VMCALL
VMCALL
VMCALL
VMRESUME
Figure 6. Test iteration description
main:
vmxon #set VMX operation ON
#launch the VM1
addi $6, $0, 1
sw $6, 0($6)
vmptrld 0($6) #set VMCS of VM1 as active
vmlaunch $vm1
# ... launch VM2
#resume VM1
addi $6, $0, 3
vmptrld 0($6) #set VMCS of VM1 as active
vmresume
vmxoff #set VMX operation OFF
break
#VM1 source code, compute factorial
$vm1:
addi $4, $0, 4 #$4=n=4
addi $5, $0, 1 #$5=f=1
vmcall #return to main
$L1:
mult $5, $4 #$hi+$lo=f*n
mflo $5 #f=$lo
addi $4, $4, -1 #n = n-1
bne $4, $0, $L1 #if (n!=0) goto
vmcall
#VM2 source code
Figure 7. The assembly program code
Figure 8 shows statistics of this test execution.
ArchC automatically generate these statistics. Through
a comparison with other processor with no
virtualization support, it is possible to check that with
VMX instruction, the test has fewer executed
instructions. In this case, the context switching is done
through only one instruction. These statistics show the
number of instructions executed and the total
simulation time in ns.
**********************************
* ArchC Simulation Statistics Report *
**********************************
Simulation time: 944
Total of Executed Instructions: 76
=> Instruction Set Statistics:
addi was executed 16 times.
mult was executed 8 times.
mtlo was executed 8 times.
sw was executed 2 times.
bne was executed 8 times.
vmxon was executed 1 times.
vmxoff was executed 1 times.
vmcall was executed 3 times.
vmlaunch was executed 2 times.
vmresume was executed 1 times.
vmptrld was executed 3 times.
vmptrst was executed 0 times.
Figure 8. Execution statistics
Figure 9 shows the execution trace of VMXON
instruction. This trace is related to the VMXON
behavior presented in Figure 5. This trace shows the
VMXON execution as follows: an operation to check
the status (disabled) of VMX instructions, an operation
to set invalid the active VMCS, in order to ensure that
no VM will be launch before the necessary
initializations; and a last operation to set VMX
instruction status in mode ON.
ArchC: ------Starting Simulation ---------------
----- PC=0 ----- 0
vmxon
RS_VMX_OP=OFF
RS_VMCS_ATIVO=0
RS_VMX_OP=ON
----- PC=0x4 ----- 1
Figure 9. Trace execution of instruction
VMXON
It is possible to add new traces in this model that
show what a student needs for a specific work. At this
point, it is necessary to add new printfs using C++
language in instruction behaviors, as presented in
Figure 5.

5. Conclusions
This paper presented the MIPS-vt, an extended
MIPS R3000 model with the main features of Intel
VT-x. This model was designed and simulated using
the ArchC framework. An assembly code example was
simulated using proposed MIPS-vt, and ArchC
generated statistics in order to evaluate the
performance of executed instructions.
The experimental simulation depicted the context
switching problem and how the virtualization
instructions can improve the performance reducing the
number of cycles, since only one instruction is
executed to perform the switching.
Using the teaching methodology, virtualization
concepts and new instructions can be presented in an
suitable time at a computer architecture course.
Moreover, the students are capable of understanding
these concepts, design, verification and evaluation
better than another moment, since they have a previous
knowledge about ISA formats, data and control paths,
which are necessary, for instance, to understand the
impacts on performance evaluation.
The experimental simulation verified the ArchC-
based model as a didactic environment capable of
improving the teaching activities and motivating the
students in classroom. In order to receive contributions
from other researchers about educational research
works, this environment composed of an ArchC-based
MIPS-vt model and program codes are available in
[16].
Future works focus on learning statistical analyses
and a MIPS-vt ISA design in order to support multi-
core architectures, also based on an ArchC model.
6. Acknowledgment
The authors thank Microsoft Innovation Center for
the research opportunity and the participation in
WCAE 2008.
References
[1] M. Rosenblum, T. Garfinkel, “Virtual Machine Monitors:
Current Technology and Future Trends”, IEEE Computer,
Volume 38, Issue 5, pp. 39-47, May 2005.
[2] J. S. Robin, C. E. Irvine, “Analysis of the Intel Pentium's
Ability to Support a Secure Virtual Machine Monitor”, 9
th
USENIX Security Symposium, 16p., 2000.
[3] k. Adams, O. Agesen, “A Comparison of Software and
Hardware Techniques for x86 Virtualization”, 12th
International Conference on Architectural Support for
Programming Languages and Operating Systems, pp.2-13,
2006.
[4] G. Neiger, A. Santoni et all, “Intel Virtualization
Technology: Hardware Support for Efficient Processor
Virtualization”, Intel Computer Journal, Vol. 10, Issue 3,
August 2006.
[5] S. Petit, N. Tomás et all, “ An Execution-Driven
Simulation Tool for Teaching Cache Memories in
Introductory Computer Organization Course”, Workshop on
Computer Architecture Education (WCAE), Article No. 4,
2006.
[6] The ArchC Team, “The ArchC Architecture Description
Language – Reference Manual”, Computer System
Laboratory (LSC) – Institute of Computing, University of
Campinas, http://www.archc.org, 2004.
[7] S. N. Soares, F. R. Wagner, “From Classroom to
Research: Providing Different Services for Computer
Architecture Education”, Workshop on Computer
Architecture Education (WCAE), pp.14-22, 2007.
[8] A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and
A. Nicolau, “EXPRESSION: A language for architecture
exploration through compiler/simulator retargetability”,
European Conference on Design, Automation and Test
(DATE), pp.485-490, March 1999.
[9] V. Zivojnovic, S. Pees, and H. Meyr, “Lisa - machine
description language and generic machine model for
HW/SW co-design”, Workshop on VLSI Signal Processing,
San Francisco, pp.127-136, 1996.
[10] S. Rigo, M. Juliato, R. Azevedo, G. Araújo, P.
Centoducatte, “Teaching Computer Architecture Using an
Architecture Description Language”, Workshop on Computer
Architecture Education (WCAE), Article No. 6, 2004.
[11] P. Viana, E. Barros, S. Rigo, R. Azevedo, G. Araújo,
“Exploring Memory Hierarchy with ArchC”, Symposium on
Computer Architecture and High Performance Computing,
pp.2-9, 2003.
[12] http://www.archc.org. The ArchC Resource Center.
[13] C. Araújo, M. Gomes, E. Barros, S. Rigo, R. Azevedo,
G. Araújo, “Platform Designer: An Approach for Modeling
Multiprocessor Platforms based on SystemC”, Journal of
Design Automation for Embedded Systems, Springer, pp.253-
283, Vol. 10, Number 4, December 2005.
[14] Hennessy, J. L., and D. A. Patterson, Computer
Organization and Design: The Hardware/Software Interface,
Morgan Kaufmann, 3
th
Edition, 2007.
[15] Intel Corporation, “Intel Virtualization Technology
Specification for the IA-32 Intel Architecture”, 2005.
[16] http://www.codeplex.com/visa, The Virtualization
Instruction Set Architecture (VISA) project web page.