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An FPGA implementation of the SURF algorithm for the ExoMars programme
Abstract
Achieving highly accurate feature extraction in a short pe-riod of time is very important for space applications based on computer vision algorithms, such as with the ExoMars programme of ESA. The paper describes a HW/SW co-design scheme using FPGAs to speed-up the SURF algorithm when executed on a low computational power CPU. It performs algorithmic analysis and restructures the SURF steps leading to efficient hardware implementation, while at the same time it exploits the advantages of the CPU. The HW architecture is implemented on a Xilinx Virtex 6 FPGA achieving real-time performance with low hard-ware cost and highly accurate results.
... The implementation achieves about 10 frames per second at 1024 × 768 resolution and the total power consumption is less than 10 W [14]. Schaeferling M. et al. (2010) proposed a hardware architecture to accelerate the SURF algorithm on Virtex-5 FPGA [15]. Lentaris G. et al. (2013) proposed a hardware-software co-design scheme using Xilinx Virtex 6 FPGA to speed-up the SURF algorithm for the ExoMars Programme [16]. Schaeferling M. et al. (2011) implemented a complete SURF-based system on Xilinx Virtex 5 FX70T FPGA for object recognition. ...
... The implementation achieves about 10 frames per second at 1024 × 768 resolution and the total power consumption is less than 10 W [14]. Schaeferling M. et al. (2010) proposed a hardware architecture to accelerate the SURF algorithm on Virtex-5 FPGA [15]. Lentaris G. et al. (2013) proposed a hardware-software co-design scheme using Xilinx Virtex 6 FPGA to speed-up the SURF algorithm for the ExoMars Programme [16]. Schaeferling M. et al. (2011) implemented a complete SURF-based system on Xilinx Virtex 5 FX70T FPGA for object recognition. ...
This paper presents a FPGA-based method for on-board detection and matching of the feature points. With the proposed method, a parallel processing model and a pipeline structure are presented to ensure a high frame rate at processing speed, but with a low power consumption. To save the FPGA resources and increase the processing speed, a model which combines the modified SURF detector and a BRIEF descriptor, is presented as well. Three pairs of images with different land coverages are used to evaluate the performance of FPGA-based implementation. The experiment results demonstrate that (1) when the image pairs with artificial features (such as buildings and roads), the performance of FPGA-based implementation is better than those image pairs with natural features (such as woods); (2) the proposed FPGA-based method is capable of ensuring the processing speed at a high frame rate, such as the speed of can achieve 304 fps under a 100 MHz clock frequency. The speedup of the proposed implementation is about 27 times higher than that when using the PC-based implementation.
We present an implementation of the Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to scale, rotation and illumination changes. The interest point detection and feature descriptor extraction algorithm is often used as the first stage in autonomous robot navigation, object recognition and tracking etc. However, detection and extraction are computationally demanding and therefore can't be used in systems with limited computational power. We took advantage of algorithm's natural parallelism and implemented it's most demanding parts in FPGA logic. Several modifications of the original algorithm have been made to increase it's suitability for FPGA implementation. Experiments show, that the FPGA implementation is comparable in terms of precision, speed and repeatability, but outperforms the CPU and GPU implementation in terms of power consumption. Our implementation is intended to be used in embedded systems which are limited in computational power or as the first stage preprocessing block, which allows the computational resources to focus on higher level algorithms.
Feature detectors are schemes that locate and describe points or regions of `interest' in an image. Today there are numerous machine vision applications needing efficient feature detectors that can work on Real-time; moreover, since this detection is one of the most time consuming tasks in several vision devices, the speed of the feature detection schemes severally affects the effectiveness of the complete systems. As a result, feature detectors are increasingly being implemented in state-of-the-art FPGAs. This paper describes an FPGA-based implementation of the SURF (Speeded-Up Robust Features) detector introduced by Bay, Ess, Tuytelaars and Van Gool; this algorithm is considered to be the most efficient feature detector algorithm available. Moreover, this is, to the best of our knowledge, the first implementation of this scheme in an FPGA. Our innovative system can support processing of standard video (640 x 480 pixels) at up to 56 frames per second while it outperforms a state-of-the-art dual-core Intel CPU by at least 8 times. Moreover, the proposed system, which is clocked at 200 MHz and consumes less than 20W, supports constantly a frame rate only 20% lower than the peak rate of a high-end GPU executing the same basic algorithm; the specified GPU consists of 128 floating point CPUs, clocked at 1.35 GHz and consumes more than 200W.
This article presents a novel scale- and rotation-invariant detector and descriptor, coined SURF (Speeded-Up Robust Features). SURF approximates or even outperforms previously proposed schemes with respect to repeatability, distinctiveness, and robustness, yet can be computed and compared much faster. This is achieved by relying on integral images for image convolutions; by building on the strengths of the leading existing detectors and descriptors (specifically, using a Hessian matrix-based measure for the detector, and a distribution-based descriptor); and by simplifying these methods to the essential. This leads to a combination of novel detection, description, and matching steps. The paper encompasses a detailed description of the detector and descriptor and then explores the effects of the most important parameters. We conclude the article with SURF's application to two challenging, yet converse goals: camera calibration as a special case of image registration, and object recognition. Our experiments underline SURF's usefulness in a broad range of topics in computer vision.
In this document, the SURF detector-descriptor scheme used in the OpenSURF library is discussed in detail. First the algorithm is analysed from a theoretical standpoint to provide a detailed overview of how and why it works. Next the design and development choices for the implementation of the library are discussed and justied. During the implementation of the library, it was found that some of the ner details of the algorithm had been omitted or overlooked, so Section 1.5 serves to make clear the concepts which are not explicitly dened in the SURF paper (1).
Today many industrial applications require object recognition and tracking capabilities. Feature-based algorithms are well-suited for such operations and, among all, Speeded Up Robust Features (SURF) algorithm has been proved to achieve optimal results. However, when high-precision and real time requirements come together, a dedicated hardware is necessary to meet them. In this paper we present a novel architecture for implementing SURF algorithm in FPGA, along with experimental results for different industrial applications.
In this paper, we propose a novel architecture to accelerate the Speeded Up Robust Features (SURF) algorithm by the use of configurable hardware. SURF is used in optical tracking systems to robustly detect distinguishable features within an image in a scale and rotation invariant way. In its performance critical part, SURF computes convolution filters at multiple scale levels without the need to create down-sampled versions of the original image. However, the algorithm exposes a very irregular memory access pattern. We designed a configurable and scalable architecture to overcome these memory access issues without the need to use any internal block RAM resources of the FPGA. The complete detector and descriptor stage of SURF has been implemented and validated in a Virtex 5 FPGA.
This article presents a novel scale- and rotation-invariant detector and descriptor, coined SURF (Speeded-Up Robust Features). SURF approximates or even outperforms previously proposed schemes with respect to repeatability, distinctiveness, and robustness, yet can be computed and compared much faster.This is achieved by relying on integral images for image convolutions; by building on the strengths of the leading existing detectors and descriptors (specifically, using a Hessian matrix-based measure for the detector, and a distribution-based descriptor); and by simplifying these methods to the essential. This leads to a combination of novel detection, description, and matching steps.The paper encompasses a detailed description of the detector and descriptor and then explores the effects of the most important parameters. We conclude the article with SURF’s application to two challenging, yet converse goals: camera calibration as a special case of image registration, and object recognition. Our experiments underline SURF’s usefulness in a broad range of topics in computer vision.