Predicting and reducing substrate induced focus error

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The ever shrinking lithography process window requires us to maximize our process window and minimize tool-induced process variation, and also to quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We quantify these effects and their interactions, and present efforts to reduce their harm to the imaging process. We also present our effort to predict design-induced focus error hot spots at the edge of our process window. The collaborative effort is geared towards enabling a constructive discussion with our design team, thus allowing us to prevent or mitigate focus error hot spots upstream of the imaging process.

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To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous works either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This article presents a joint optimization scheme to consider variation, total fill, line deviation, outlier, overlap, and running time simultaneously. More specifically, first we decompose the rectilinear polygons and partition fillable regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fillable rectangular regions optimizing the fill metrics simultaneously. We propose three approaches, Fast Median approach, LP approach, and Iterative approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.
Conference Paper
Despite the increasing use of advanced imaging methods to pattern chip features, process windows continue to shrink with decreasing critical dimensions. Controlling the manufacturing process within these shrinking windows requires monitor structures designed to maximize both sensitivity and robustness. In particular, monitor structures must exhibit a large, measurable response to dose and focus changes over the entire range of the critical features process window. Any process variations present fundamental challenges to the effectiveness of OPC methods, since the shape compensation assumes a repeatable process. One particular process parameter which is under increasing scrutiny is focus blur, e.g. from finite laser bandwidth, which can cause such OPC instability, and thereby damage pattern fidelity. We introduce a new type of test target called the Process Monitor Grating (PMG) which is designed for extreme sensitivity to process variation. The PMG design principle is to use assist features to zero out higher diffraction orders. We show via simulation and experiment that such structures are indeed very sensitive to process variation. In addition, PMG targets have other desirable attributes such as mask manufacturability, robustness to pattern collapse, and compatibility with standard CD metrology methods such as scatterometry. PMG targets are applicable to the accurate determination of dose and focus deviations, and in combination with an isofocal grating target, allow the accurate determination of focus blur. The methods shown in this paper are broadly applicable to the characterization of process deviations using test wafers or to the control of product using kerf structures.
This work describes the implementation and performance of AGILE focus corrections for advanced photo lithography in volume production as well as advanced development in IBM's 300mm facility. In particular, a logic hierarchy that manages the air gage sub-system corrections to optimize tool productivity while sampling with sufficient frequency to ensure focus accuracy for stable production processes is described. The information reviewed includes: General AGILE implementation approaches; Sample focus correction contours for critical 45nm, 32nm, and 22nm applications; An outline of the IBM Advanced Process Control (APC) logic and system(s) that manage the focus correction sets; Long term, historical focus correction data for stable 45nm processes as well as development stage 32nm processes; Practical issues encountered and possible enhancements to the methodology.
With decreasing critical dimension (CD) budgets and smaller k1 values the need for perfect focus control becomes paramount. Among the individual contributors to the overall focus budget, the accuracy of the leveling system on a process wafer and the focus setting accuracy for the individual layers are two major contributors. In our study we discuss the usage of a new non-optical leveling system and its measurement capability of wafer topography. By exposing focus-exposure matrices (FEMs) and measuring them on multiple points in the field, we demonstrate the systematic and random focus variation across the scanner exposure field for several layers. Critical back end of line (BEoL) layers in particular show considerable impact of topography, thus resulting in the across field focus variations shown. By using the newly developed AGILE leveling system which uses an air-gauge focus sensor we demonstrate a more accurate best focus determination across field, resulting in better overall focus performance. This AGILE system is expected to be independent on any process variation, since there is no (optical) interaction between the measurement device and the process layer stack. By the use of multi-point FEMs we show that the intrafield focus range can be reduced by as much as 50%, depending on certain layer and layout characteristics. We discuss the impact of the new sensor in conjunction with the extended FEM scheme on the overall focus budget for critical layers. Finally, we briefly show a possible integration scenario into the overall exposure strategy.
Our case study experimentally gauges the defocus component induced by a step in the exposure field substrate, with the edge of the step aligned parallel to the scanning slit. Such steps frequently occur at the border of different chiplets or process monitors within one exposure field. A common assumption is that a step-and-scan imaging system can correct for the majority of such topography, since the wafer is dynamically leveled under the static image plane as it is scanned. Our results show that the range of defocus approaches about 85% of the actual step height and thus contributes significantly to the overall focusing variance. This area on the wafer in which defocus can be observed extends by more than 3mm to both sides of the step. In the same area a degradation of imaging fidelity can be observed in the form of exaggerated proximity effects.
We formulate a physical model to extract effective dose and defocus (EDD) from pattern profile data and demonstrate its efficacy in the analysis of in-line scatterometer measurements. From the measurement of a single target structure, the model enables simultaneous computation of pattern dimensions pre-calibrated to the imaging system dose and focus settings. Our approach is generally applicable to ensuring the adherence of pattern features to dimensional tolerances in the control and disposition of product wafers while minimizing in-line metrology.