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USING AN FPGA IMPLEMENTATION OF THE MULTICYCLE MIPS MACHINE TO TEACH RECONFIGURABLE COMPUTING IN THE NEW EHEA
Abstract
Reconfigurable Computing is a very important discipline nowadays. Furthermore, with the new hardware description languages like Handel-C the change to hardware programming is easier for the computer engineers. In this work, we present a proposal of course about Reconfigurable Computing devoted to the training of the new computer engineers within the new European Higher Education Area based on the multicycle MIPS machine implementation using FPGAs and Handel-C.
... Otros cursos incorporan a los dispositivos FPGA dentro de su programas académicos. Por ejemplo, [18] hace uso de sesiones prácticas de laboratorio para el diseño de Unidades Aritmético Lógicas, unidades de memoria y unidades de control a través de Handel-C. Así también, contempla sesiones para la enseñanza de la paquetería ISE de Xilinx y el uso de Visual C++. ...
Resumen— Este artículo presenta la implementación de ejemplos de prácticas de laboratorio relacionadas con el área de procesamiento de imágenes utilizando procesadores embebidos en FPGA (Field Programmable Gate Array). Con la implementación de estos ejemplos, el alumno aprenderá a realizar diseños con el enfoque hardware/software e incrementará sus habilidades como ingeniero, al integrar sus conocimientos en electrónica digital sobre procesadores embebidos en arquitecturas reconfigurables, y de informática, al programar los algoritmos en C/C++. Los algoritmos propuestos en estos ejemplos de laboratorio para el procesamiento de las imágenes se ejecutan en el microcontrolador embebido Microblaze de Xilinx.
... Otros cursos incorporan a los dispositivos FPGA dentro de su programas académicos. Por ejemplo, [18] hace uso de sesiones prácticas de laboratorio para el diseño de Unidades Aritmético Lógicas, unidades de memoria y unidades de control a través de Handel-C. Así también, contempla sesiones para la enseñanza de la paquetería ISE de Xilinx y el uso de Visual C++. ...
This paper proposes a series of related laboratory projects to the image processing area through reconfigurable integrated circuits like FPGA (field programmable gate array). With the implementation of these projects, the students will not only develop skills in electronic design, they also will increase their knowledge as engineers, with the integration of electronic engineering and computer science in the design of reconfigurable hardware with FPGA's. The algorithms proposed in these laboratory projects, for the image processing, are coded in C++ and are implemented in the embedded microcontroller Microblaze.
This chapter captures the experience acquired in the development of applications based on genetic algorithms. Specifically,
we implemented two games that show an intelligent behaviour by executing genetic algorithms. They both show good results as
well, because they are able to play successfully against human players. Moreover, the genetic algorithms parameters are user-configurable;
so, the user can modify the number of individuals per generation, the number of generations, the mutation probability of each
individual, the crossover function to generate new individuals, etc. This is very useful because the applications developed
also generate statistical reports that show how individuals evolve in each generation. Therefore, the user can understand
the evolution and analyze results easily. With this approach the user can test several combinations of parameters to study
and compare them by analyzing their behaviour, speed, etc. In conclusion, as we are going to see in this chapter, the implementation
of these two genetic games is an interesting strategy in order to teach and learn genetic algorithms.
In this paper we present a design case study using Handel-C---a recently developed programming language for compilation of high-level programs directly into FPGA hardware. The design is an 8-bit RISC microcontroller core with 33 instructions, prescaler and a programmable timer. Handel-C was used throughout the entire design and debugging flow. The RISC microcontroller design was implemented in on the XESS XS40 FPGA board with Xilinx XC4010XL FPGA . The overall design, including debugging, testing and the FPGA implementation was completed in less than 48 man-hours.
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Towards the European Higher Education Area: Survey of Main Reforms from Bologna to Prague
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ECTS -European Credit Transfer and Accumulation System
- European Commission
European Commission: "ECTS -European Credit Transfer and Accumulation System". Available at:
http://europa.eu.int/comm/education/programmes/socrates/ects_en.html (2005).