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An Analog Integrated Circuit Beamformer for High-Frequency Medical Ultrasound Imaging
Abstract
We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.
... All-pass filters as delay stages have a large variety of applications and have been utilized in many different radio frequency (RF) and phase shift circuits like synchronizing ultra-wideband (UWB) impulse radios with locally generated reference pulses, equalizers and analog/RF beamformers [3,9,[12][13][14]. There are several current-and voltage-mode all-pass filters in the literature [6,7,17], using one or more operational voltage or current amplifiers. ...
... where ω is the angular frequency. From (9), note that the group delay is equal to 2Lg m1 at low frequencies and g m2 (i.e., R 2 = 1/g m2 ) will be neglected, since the inductor L shorts the source of M 1 to ground at DC. At high frequencies, the resistor R 2 can be regarded as a source degeneration resistor, contributing to the linearity of the circuit. ...
... The gain roll-off is due to the existence of parasitic effects of the transistors and also due to the fact that the DC gain of the all-pass filter is less than unity [refer to (2)]. The group delay response of the proposed all-pass filter is shown in Fig. 5, indicating a flat group delay equal to 59.8 ps over an approximately 5 GHz bandwidth, which is very close to the theoretical value in (9) with an error of about 11.5%. Figure 6 shows the gain and group delay responses of the second-order all-pass filter under different values of R 2 (= 1/g m2 ). ...
In this paper, a CMOS wideband second-order voltage-mode all-pass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay–bandwidth product. The proposed circuit is highly linear and has an input-referred 1-dB compression point \(P_{1\mathrm{{dB}}}\) of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank; therefore, the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point \(P_{1\mathrm{{dB}}}\) of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters.
... With the cable issue eliminated, the burden is now pushed onto the subarray beamforming electronics, which must be designed in a pixel pitch-matched style and within a very small per-channel area (250 µm × 250 µm in this paper). To meet these constraints, prior work has implemented the delays using sample and hold (S/H) circuits [8] or analog filters [9]. However, such analog approaches tend to sacrifice performance and typically suffer from a combination of issues related to restricted delay range, coarse delay resolution, and/or limited SNR. ...
... Section IV presents the experimental results, followed by conclusions in Section V. Fig. 3 compares the block diagrams of prior art and our system. Fig. 3(a) represents BF approaches using analog filters [9] or S/H circuits [8], [11]. Creating a time delay with an analog filter requires the approximation of a linear phase characteristic, which suffers from a strong tradeoff between filter bandwidth and maximum delay. ...
... Compared to [36], our work consumes more power due to a much higher SNR target for PA applications. A direct comparison to the analog BF ICs [8], [9] is more difficult to make, due to the significantly different performance parameters. If the SNR and delay range are reduced to 40 dB and 200 ns, respectively, the power of the ΔΣM and BF is reduced by approximately eight times and five times. ...
This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 $\mu \text{m}$ by 250 $\mu \text{m}$ . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.
... To prevent distortion of the fastest signal, the analog delay line should delay the fastest signal during the two-step FSI process. Among various analog delay circuits, an all-pass filter is adopted because it requires neither any sampling operation which could cause sampling harmonics nor a high-frequency clock [11][12][13][14]. The all-pass filter has a unit gain at all frequencies and a phase shift at ...
... To prevent distortion of the fastest signal, the analog delay line should delay the fastest signal during the two-step FSI process. Among various analog delay circuits, an all-pass filter is adopted because it requires neither any sampling operation which could cause sampling harmonics nor a high-frequency clock [11][12][13][14]. The all-pass filter has a unit gain at all frequencies and a phase shift at a designed frequency, which adjust the delay time. ...
A readout integrated circuit (ROIC) using two-step fastest signal identification (FSI) is proposed to reduce the number of input channels of a data acquisition (DAQ) block with a high-channel reduction ratio. The two-step FSI enables the proposed ROIC to filter out useless input signals that arise from scattering and electrical noise without using complex and bulky circuits. In addition, an asynchronous fastest signal identifier and a self-trimmed comparator are proposed to identify the fastest signal without using a high-frequency clock and to reduce misidentification, respectively. The channel reduction ratio of the proposed ROIC is 16:1 and can be extended to 16 × N:1 using N ROICs. To verify the performance of the two-step FSI, the proposed ROIC was implemented into a gamma photon detector module using a Geiger-mode avalanche photodiode with a lutetium-yttrium oxyorthosilicate array. The measured minimum detectable time is 1 ns. The difference of the measured energy and timing resolution between with and without the two-step FSI are 0.8% and 0.2 ns, respectively, which are negligibly small. These measurement results show that the proposed ROIC using the two-step FSI reduces the number of input channels of the DAQ block without sacrificing the performance of the positron emission tomography (PET) systems.
... The direct calculation method outputs unsteadily and is not fit for real-time applications. Time-domain windowing was proposed to weaken the defect in the direct calculation method to some degree, as tiny changes in fetal heart rate are not uncommon [17]. If a spike is low that it is missed, the result will decrease by the smallest unit; meanwhile, if the disturbance is detected as a fetal heart sound peak, the result will increase by the smallest unit. ...
In certain cases, the condition of the fetus can be revealed by the fetal heart sound. However, when the sound is detected, it is mixed with noise from the external environment as well as internal disturbances. Our exclusive sensor, which was constructed of copper with an enclosed cavity, was designed to prevent external noise. In the sensor, a polyvinylidene fluoride (PVDF) piezoelectric film, with a frequency range covering that of the fetal heart sound, was adopted to convert the sound into an electrical signal. The adaptive support vector regression (SVR) algorithm was proposed to reduce internal disturbance. The weighted-index average algorithm with deviation correction was proposed to calculate the fetal heart rate. The fetal heart sound data were weighted automatically in the window and the weight was modified with an exponent between windows. The experiments show that the adaptive SVR algorithm was superior to empirical mode decomposition (EMD), the self-adaptive least square method (LSM), and wavelet transform. The weighted-index average algorithm weakens fetal heart rate jumps and the results are consistent with reality.
... In [78], the authors investigated the maximum possible dynamic range of binary quantization under different conditions and found that binary quantization can be used when the input SNR is lower than 5 dB. Comparators can also operate at higher sampling rates, which is particularly useful for highfrequency arrays [14,24]. Furthermore, binary excitation combined with pulse-width modulation has been used to control the shape of the transmitted waves with similar performance to that of digital-to-analogue converters (DACs) [79]. ...
Pulse-echo arrays are used in radar, sonar, seismic, medical and non-destructive evaluation. There is a trend to produce arrays with an ever-increasing number of elements. This trend presents two major challenges: (i) often the size of the elements is reduced resulting in a lower signal-to-noise ratio (SNR) and (ii) the time required to record all of the signals that correspond to every transmit-receive path increases. Coded sequences with good autocorrelation properties can increase the SNR while orthogonal sets can be used to simultaneously acquire all of the signals that correspond to every transmit-receive path. However, a central problem of conventional coded sequences is that they cannot achieve good autocorrelation and orthogonality properties simultaneously due to their length being limited by the location of the closest reflectors. In this paper, a solution to this problem is presented by using coded sequences that have receive intervals. The proposed approach can be more than one order of magnitude faster than conventional methods. In addition, binary excitation and quantization can be employed, which reduces the data throughput by roughly an order of magnitude and allows for higher sampling rates. While this concept is generally applicable to any field, a 16-element system was built to experimentally demonstrate this principle for the first time using a conventional medical ultrasound probe.
... A great diversity of efficient hardware-level beamforming strategies in the analogue and digital domains have been proposed in literature. In analogue beamforming, signals from each transducer element are delayed with analogue delay lines, and then summed and digitised [5][6][7]. However, the number of analogue delay cells increases quadratically with the number of channels, resulting in excessive complexity, power consumption and pulse distortion for a practical array. ...
Background:
Point of care ultrasonography has been the focus of extensive research over the past few decades. Miniaturised, wireless systems have been envisaged for new application areas, such as capsule endoscopy, implantable ultrasound and wearable ultrasound. The hardware constraints of such small-scale systems are severe, and tradeoffs between power consumption, size, data bandwidth and cost must be carefully balanced.
Methods:
In this work, two receiver architectures are proposed and compared to address these challenges. Both architectures uniquely combine low-rate sampling with synthetic aperture beamforming to reduce the data bandwidth and system complexity. The first architecture involves the use of quadrature sampling to minimise the signal bandwidth and computational load. Synthetic aperture beamforming (SAB) is carried out using a single-channel, pipelined protocol suitable for implementation on an FPGA/ASIC. The second architecture employs compressive sensing within the finite rate of innovation framework to further reduce the bandwidth. Low-rate signals are transmitted to a computational back-end (computer), which sequentially reconstructs each signal and carries out beamforming.
Results:
Both architectures were tested using a custom hardware front-end and synthetic aperture database to yield B-mode images. The normalised root-mean-squared-error between the quadrature SAB image and the RF reference image was [Formula: see text] while the compressive SAB error was [Formula: see text] for the same degree of spatial compounding. The sampling rate is reduced by a factor of 2 (quadrature SAB) and 4.7 (compressive SAB), compared to the RF sampling rate. The quadrature method is implemented on FPGA, with a total power consumption of [Formula: see text] mW, which is comparable to state-of-the-art hardware topologies, but with significantly reduced circuit area.
Conclusions:
Through a novel combination of SAB and low-rate sampling techniques, the proposed architectures achieve a significant reduction in data transmission rate, system complexity and digital/analogue circuit area. This allows for aggressive miniaturisation of the imaging front-end in portable imaging applications.
This article presents an ultrasound (US) transceiver IC including a highly power-efficient US receiver (RX) and a high-voltage (HV) US transmitter (TX) for US capsule endoscopy (USCE) systems for the first time. The proposed USCE system employs the developed IC, a single-element piezoelectric transducer (PZT), and a mechanically rotating reflector to obtain 360
$^{\circ}$
transmural scans while traveling through the gastrointestinal (GI) tract. Since the USCE system operates with a tiny battery, power efficiency is greatly important. To reduce power consumption by decreasing the required operating speed of the analog-to-digital converter (ADC), we propose a new RX structure employing synchronized analog envelope detection. It is unlike conventional US RX ICs that necessitate power-hungry high-speed ADCs to acquire the US signal residing at a high center frequency with wide bandwidth. Instead, the proposed work employs an analog envelope detector based on a quadrature demodulation method. As a result, it uses only a single circuit path rather than two (I and Q) paths by using a demodulation carrier whose phase is synchronized with the incoming US signal. A ping-pong noise-shaping (NS) SAR ADC is adopted to improve resolution while maintaining low power consumption. Besides, the TX IC, including an on-chip charge pump, is designed to generate HV pulses to drive the PZT. The prototype IC is fabricated in a 0.18
$\mu$
m bipolar-CMOS-DMOS (BCD) process. The RX consumes 2.3 mW, and the ADC achieves a 53.71 dB SNDR and a 66.45 dB SFDR. The TX generates 25 V pulses with 25 ns pulsewidth. US B-mode images of a water tank and a custom phantom are successfully obtained by using the prototype capsule endoscopy system employing the fabricated IC chip.
This article presents a low-power and small-area transceiver application-specific integrated circuit (ASIC) for 3-D trans-fontanelle ultrasonography. A novel micro-beamforming receiver architecture that employs current-mode summation and boxcar integration is used to realize delay-and-sum on an N-element sub-array using N
$\times$
fewer capacitive memory elements than conventional micro-beamforming implementations, thus reducing the hardware overhead associated with the memory elements. The boxcar integration also obviates the need for explicit anti-aliasing filtering in the analog front end, thus further reducing die area. These features facilitate the use of micro-beamforming in smaller pitch applications, as demonstrated by a prototype transceiver ASIC employing micro-beamforming on sub-arrays of
$\tit{N}=4$
elements, targeting a wearable ultrasound device that monitors brain perfusion in preterm infants via the fontanel. To meet its strict spatial resolution requirements, a 10-MHz 100-
$\mu$
m-pitch piezoelectric transducer array is employed, leading to a per-element die area
$>$
2
$\times$
smaller than prior designs employing micro-beamforming.
To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without variations in process, voltage, and temperature. Moreover, to maintain the duty cycle of long propagation signals, this novel CBDC requires only a few delay cells, significantly reducing hardware costs and power consumption. Simulations were conducted, revealing a maximum time delay of 451.9 ns with a time resolution of 652 ps and a maximum lateral resolution error of 0.04 mm at 6.8 mm.
This paper demonstrates hybrid sub-aperture beamforming (SAB) with time-division multiplexing (TDM) for massive interconnect reduction in ultrasound imaging systems. A single-chip front-end system prototype has been fabricated in 180-nm HV BCD technology that combines 5×1 SAB with 8×1 TDM to efficiently reduce the number of receive signal interconnects by a factor of 40. The system includes on-chip high-voltage (HV) pulsers capable of generating unipolar pulses up to 70 V in transmit (TX) mode. The receiver (RX) chain consists of a T/R switch, a variable-gain low-noise amplifier (VG-LNA) with 4-step gain control (15-32 dB) for time-gain compensation followed by a programmable switched-capacitor analog delay-and-sum beamformer. The proof-of-concept prototype operates at a 200-MHz clock frequency and the SAB provides 32-step fine delays with a maximum delay of 310 ns corresponding to better than
$\lambda$
/20 delay quantization at 5 MHz. With these specifications, the SAB is capable of beam steering from 0
$^{\circ }$
to 45
$^{\circ }$
for a 5-element subarray with 150-micron pitch (
$\lambda$
/2), providing a near-ideal phased array imaging performance. The sub-aperture beamformer is followed by the TDM system where each of the 8 channels is sampled at a rate of 25 MS/s after an anti-aliasing bandpass filter. The full functionality of the prototype chip is validated through electrical and acoustic measurements on a 1-D capacitive micromachined ultrasonic transducer (CMUT) array designed for intracardiac echocardiography (ICE).
This paper demonstrates hybrid sub-aperture beamforming (SAB) with time-division multiplexing (TDM) for massive interconnect reduction in ultrasound imaging systems. A single-chip front-end system prototype has been fabricated in 180-nm HV BCD technology that combines 5×1 SAB with 8×1 TDM to efficiently reduce the number of receive signal interconnect by a factor of 40. The system includes on-chip high voltage (HV) pulsers capable of generating unipolar pulses up to 70 V in transmit (TX) mode. The receiver (RX) chain consists of a T/R switch, a variable-gain low-noise amplifier (VG-LNA) with 4-step gain control (15-32 dB) for time-gain compensation followed by a programmable switched-capacitor analog delay-and-sum beamformer. The proof-of-concept prototype operates at 200-MHz clock frequency and the SAB provides 32-step fine delays with a maximum delay of 310 ns corresponding to better than λ/20 delay quantization at 5 MHz. With these specifications the SAB is capable of beam steering from 0° to 45° for a 5-element subarray with 150-micron pitch (λ/2), providing a near ideal phased array imaging performance. The sub-aperture beamformer is followed by the TDM system where each of the 8 channels is sampled at a rate of 25 MS/s after an antialiasing bandpass filter. Full functionality of the prototype chip is validated through electrical and acoustic measurements on a 1-D capacitive micromachined ultrasonic transducer (CMUT) array designed for intracardiac echocardiography (ICE).
This paper demonstrates hybrid sub-aperture beamforming (SAB) with time-division multiplexing (TDM) for massive interconnect reduction in ultrasound imaging systems. A single-chip front-end system prototype has been fabricated in 180-nm HV BCD technology that combines 5×1 SAB with 8×1 TDM to efficiently reduce the number of receive signal interconnect by a factor of 40. The system includes on-chip high voltage (HV) pulsers capable of generating unipolar pulses up to 70 V in transmit (TX) mode. The receiver (RX) chain consists of a T/R switch, a variable-gain low-noise amplifier (VG-LNA) with 4-step gain control (15-32 dB) for time-gain compensation followed by a programmable switched-capacitor analog delay-and-sum beamformer. The proof-of-concept prototype operates at 200-MHz clock frequency and the SAB provides 32-step fine delays with a maximum delay of 310 ns corresponding to better than λ/20 delay quantization at 5 MHz. With these specifications the SAB is capable of beam steering from 0° to 45° for a 5-element subarray with 150-micron pitch (λ/2), providing a near ideal phased array imaging performance. The sub-aperture beamformer is followed by the TDM system where each of the 8 channels is sampled at a rate of 25 MS/s after an antialiasing bandpass filter. Full functionality of the prototype chip is validated through electrical and acoustic measurements on a 1-D capacitive micromachined ultrasonic transducer (CMUT) array designed for intracardiac echocardiography (ICE).
Medical ultrasound has become a crucial part of modern society and continues to play a vital role in the diagnosis and treatment of illnesses. Over the past decades, the develop- ment of medical ultrasound has seen extraordinary progress as a result of the tremendous research advances in microelectronics, transducer technology and signal processing algorithms. How- ever, medical ultrasound still faces many challenges including power-efficient driving of transducers, low-noise recording of ultrasound echoes, effective beamforming in a non-linear, high- attenuation medium (human tissues) and reduced overall form factor. This paper provides a comprehensive review of the design of integrated circuits for medical ultrasound applications. The most important and ubiquitous modules in a medical ultrasound system are addressed, i) transducer driving circuit, ii) low- noise amplifier, iii) beamforming circuit and iv) analog-digital converter. Within each ultrasound module, some representative research highlights are described followed by a comparison of the state-of-the-art. This paper concludes with a discussion and recommendations for future research directions.
Photoacoustic (PA) imaging is becoming more attractive because it can obtain high-resolution and high-contrast images through merging the merits of optical and acoustic imaging. High sensitivity receiver is required in deep
in-vivo
PA imaging due to detecting weak and noisy ultrasound signal. A novel photoacoustic receiver system-on-chip (SoC) with coherent detection (CD) based on the early-and-late acquisition and tracking is developed and first fabricated. In this system, a weak PA signal with negative signal-to-noise-ratio (SNR) can be clearly extracted when the tracking loop is locked to the input. Consequently, the output SNR of the receiver is significantly improved by about 29.9 dB than input one. For the system, a high dynamic range (DR) and high sensitivity analog front-end (AFE), a multiplier, a noise shaping (NS) successive-approximation (SAR) analog-to-digital convertor (ADC), a digital-to-analog convertor (DAC) and integrated digital circuits for the proposed system are implemented on-chip. Measurement results show that the receiver achieves 0.18 µVrms sensitivity at the depth of 1 cm with 1 mJ/cm
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laser output fluence. The contrast-to-noise (CNR) of the imaging is improved by about 22.2 dB. The area of the receiver is 5.71 mm
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, and the power consumption of each channel is about 28.8 mW with 1.8 V and 1 V power supply on the TSMC 65 nm CMOS process.
This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled on the SoC FPAA. Using the Ladder Filter as a programmable CT delay operation enables a traditionally difficult analog signal operation. This effort extensively models and characterizes the ladder filter delay stage in terms of its transfer function, delay tunability, power requirements, distortion, and SNR. The theoretical development is compared to experimental measurements on an SoC FPAA with programmable ladder filter delay of
$2.9\mu \text{s}$
and
$4.2\mu \text{s}$
for multiple input frequencies (e.g. 5kHz, 20kHz). In addition, we show that VMMs can compensate the non-idealities found in the ladder filter delay-line operation.
This paper presents a 32-channel high timing resolution transmit-beamforming circuit for use in high-frequency ultrasound imaging systems. Conventional transmit-beamforming circuits are typically implemented using field-programmable gate array (FPGA) chips. However, it is difficult for FPGAs to provide high timing resolution to meet the beamforming requirements of high-frequency ultrasound imaging systems. The proposed transmit-beamforming design can generate stable and suitable delays to excite 32-channel array transducer elements without variations in the process, voltage, and temperature. In addition, the proposed low-complexity architecture can maintain the duty cycle of long prorogation signals with low hardware cost to meet the timing requirements of a large channel number array transducer. The proposed designed transmit beamformer uses 0.18-µm CMOS technology for a 30-MHz high-frequency linear array, and the simulation results show that the proposed transmit-beamforming application-specific integrated circuit can achieve a maximum time delay of 619.5 ns with a time resolution of 617 ps.
In this article, we present a high delay resolution and all-digital transmit-beamforming circuit for use in high-frequency and wearable ultrasound imaging systems. The proposed transmit beamformer comprises an all-digital delay-locked loop (ADDLL), a cycle-based beamforming delay line (CBDL), and a pulse controller. ADDLL can provide specific digital control code for the CBDL to generate stable and suitable delays to excite array transducer elements without variations in process, voltage, and temperature. CBDL not only provides a finer delay resolution for high-frequency ultrasound imaging systems but also requires a few delay cells to maintain the duty cycle of long prorogation signals, thereby significantly reducing hardware costs. The pulse controller can adjust the number and width of output pulses to meet the requirements of different ultrasonic transducers and Doppler ultrasound color imaging. The proposed transmit beamformer uses a 0.18-
$\mu \text{m}$
CMOS technology for a 30-MHz high-frequency linear array with 256 elements, and the focusing depth is from 3.5 to 8.1 mm. The measurement results indicate that the proposed transmit-beamforming design can achieve a maximum time delay of 562.6 ns with an average time resolution of 535 ps. The proposed design offers a smaller volume and finer delay resolution, and it is highly suitable for wearable ultrasound imaging systems.
Biomedical engineering is one of the fastest developing research disciplines in the past 60 years with the aid of rapid advances in technol- ogy. Biomedical engineering has emerged in Turkey in late 1970s but the research conducted in this area has been developing only in the past 15 years. The aim of this review is to summarize the problems regarding biomedical engineering in Turkey; to present the main sub- jects that are conducted in biomedical field in Turkey; and to summarize the prominent research papers conducted by Turkish Institutes published during the period 2008-2018 that contribute and/or have a potential to contribute to research and development (R&D) in bio- medical engineering field in Turkey. These studies were divided into categories of tissue engineering, biosensors and biomedical devices; and summarized in this review.
An 8-channel ultrasound receiver compatible with in-probe electronics for 3-D ultrasound imaging is proposed. It has eight analog front-ends for signal conditioning and a beamforming embedded SAR analog-to-digital converter (ADC) for performing both an 8-to-1 analog summation and its digitization in charge mode. By combining the 30-dB programmable gain of the analog front-ends with the 60-dB signal-to-noise ratio of the ADC, the 8-channel receiver achieves the DR of 80.2 dB. The delay is set in increments of 4.17 ns, up to a maximum of 292 ns. Implemented in a 0.18-μm CMOS process, a prototype occupies an active area of 0.525 mm
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/channel and draws 23.25 mW/channel at a sampling frequency of 20 MHz.
This paper presents a single chip reduced-wire active catheter application-specific integrated circuit (ASIC), equipped with programmable transmit (Tx) beamforming and receive (Rx) time-division multiplexing (TDM). The proposed front-end ASIC is designed for driving a 64-channel one-dimensional transducer array in intracardiac echocardiography (ICE) ultrasound catheters. The ASIC is implemented in 60 V 0.18-μm HV-BCD technology, integrating Tx beamformers with high voltage pulsers and Rx front end in the same chip, which occupies 2.6 × 11 mm
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that can fit in the catheter size of 9 F (<;3 mm). The proposed system reduces the number of wires from >64 to only 22 by integrating Tx beamformer that is programmable using a single low-voltage differential signaling data line. In Rx mode, the system uses 8:1 TDM with direct digital demultiplexing providing raw channel data that enables dynamic Rx beamforming using individual array elements. This system has been successfully used for B-mode imaging on standard ultrasound phantom with 401 mW of average power consumption. The ASIC has a compact element pitch-matched layout, which is also compatible with capacitive micromachined ultrasound transducer on CMOS application. This system addresses cable number and dimensional restrictions in catheters to enable ICE imaging under magnetic resonance imaging by reducing radio frequency induced heating.
A quadrature synthetic aperture front-end receiver for B-mode ultrasound imaging is presented. The receiver targets small-scale imaging applications such as capsule endoscopy and low-cost portable devices. System complexity, area, power consumption, and cost are minimized using synthetic aperture beamforming (SAB), whereby signals are processed in a sequential manner using only a single channel. SAB is combined with quadrature (I/Q) sampling, which further reduces the bandwidth and computational load. I/Q demodulation is carried out using a full custom analog front-end (AFE), which comprises a low-noise, variable gain preamplifier, followed by a passive mixer, programmable gain amplifier (PGA) and active lowpass filter. A novel preamplifier design is proposed, with quasi-exponential time-gain control and low noise ( ${\text{5.42\,nV}}/\sqrt{\text{Hz}}$ input-referred noise). Overall, the AFE consumes ${\text{7.8\,mW}}$ (static power) and occupies ${\text{1.5}}\,\text{mm}\times {\text{1.5}}\,\text{mm}$ in AMS ${\text{0.35}}\,\mu \text{m}$ CMOS. Real-time SAB is carried out using a Spartan-6 FPGA, which dynamically apodises and focuses the data by interpolating and applying complex phase rotations to the I/Q samples. For a frame rate of ${\text{7}}\,\text{Hz}$ , the power consumption is ${\text{3.4}}\,\text{mW}/\text{channel}$ across an aperture of 64 elements. B-mode images were obtained using a database of ultrasound signals ( ${\text{2.5}}\,\text{MHz}$ center frequency) derived from a commercial ultrasound machine. The normalized root mean squared error between the quadrature SAB image and the RF reference image was ${\text{13}}\%$ . Image quality/frame rate may be tuned by varying the degree of spatial compounding. IEEE
Intracardiac echocardiography (ICE) provides real-time ultrasound imaging of the heart anatomy from inside, guiding interventions like valve repair, closure of atrial septal defects (ASD) and catheter-based ablation to treat atrial fibrillation. With its better image quality and ease of use, ICE is becoming the preferred imaging modality over transesophageal echography (TEE) for structural heart interventions. The existing commercial ICE catheters, however, offer a limited 2-D or 3-D field of view despite catheters utilizing large number of wires. In these catheters, each element in the ICE array is connected to the backend data-acquisition channel with a separate wire, which is a critical barrier for improving image quality and widening the field of view. In order to use ICE catheters under MRI instead of the ionizing X-ray radiation-based angiography, the number of interconnect wires in the catheter should be minimized to reduce RF-induced heating. Furthermore, reducing the number of wires improves the flexibility and lowers the cost of the single-use ICE catheters.
We propose an analog delay line (ADL) that adopts a current-splitting method (CSM) to reduce power consumption. The proposed ADL employs a pipelined sample-and-hold architecture and includes a buffer in the analog memory cell to prevent a charge sharing problem. The CSM reduces power consumption without distorting the sampled data by dividing the current source of the buffer into a holding current source and a buffering current source, which are, respectively, located inside and outside of the analog memory cell. The simulated power consumption of the proposed ADL without and with the CSM is 1080 and 90 μW, respectively, indicating that the CSM reduces power consumption by 91.7%. The proposed ADL was fabricated using a 0.18-μm CMOS process with a 1.8-V supply voltage and occupies an active area of 120 × 140 μm
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. The sampling capacitor in the analog memory cell was implemented with MOS capacitors instead of metal-insulator-metal capacitors, resulting in an area per unit delay of the proposed ADL of only 600 μm2, which is much smaller than that in prior works. The measurement results show that the delay of the proposed ADL is accurately controlled from 25 to 475 ns with a unit delay step of 25 ns at a sampling frequency of 40 MHz.
A 64-channel RX digital beamformer was implemented in a single chip for 3-D ultrasound medical imaging using 2-D phased-array transducers. The RX beamformer chip includes 64 analog front-end branches including 64 non-uniform sampling ADCs, a FIFO/Adder, and an on-chip look-up table (LUT). The LUT stores the information on the rising edge timing of the non-uniform ADC sampling clocks. To include the LUT inside the beamformer chip, the LUT size was reduced by around 240 times by approximating an ADC-sample-time profile w.r.t. focal points (FP) along a scanline (SL) for a channel into a piece-wise linear form. The maximum error between the approximated and accurate sample times of ADC is eight times the sample time resolution (Ts) that is 1/32 of the ultrasound signal period in this work. The non-uniform sampling reduces the FIFO size required for digital beamforming by around 20 times. By applying a 9-dot image from Field-II program and 2-D ultrasound phantom images to the fabricated RX beamformer chip, the original images were successfully reconstructed from the measured output. The chip in a 0.13-um CMOS occupies 30.25 [Formula: see text] and consumes 605 mW.
This paper presents a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) for ultrasound imaging systems. The proposed AANC reduces unnecessary power consumption of the LNA, which arises from useless noise floor, by controlling the noise floor of the LNA with respect to the attenuation of the ultrasound. In addition, a current feedback amplifier with a source-degenerated input stage reduces variations of the bandwidth and the closed loop gain, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-[Formula: see text] CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 [Formula: see text] at the frequency of 5 MHz. The second harmonic distortion is -53.5 dB when the input signal frequency is 5 MHz and the output voltage swing is 2 [Formula: see text]. The power consumption of the LNA using the AANC is 16.2 mW at the supply voltage of 1.8 V, which is reduced to 64% of that without using the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69, to our knowledge, which is the lowest NEF compared with previous LNAs for ultrasound imaging.
This paper presents the design of a continuous-time $DeltaSigma$ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 ${rm mm}^{2}$ and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.
A low-power high-energy-efficiency switched current (SI)-based beamformer is designed and fabricated in a 180-nm complementary metal-oxide-semiconductor technology. The beamformer is implemented using an analog RAM (ARAM) delay and sum approach. A new bias-shared SI architecture is proposed for the low-power ARAM implementation. The highlight of the proposed architecture is that the number of memory cells in the ARAM can be increased without a proportional increase in power consumption. This feature allows the beamformer to have a longer memory depth and higher flexibility for wave shaping during the beam formation. As proof of concept, 16 channels have been implemented for the beamformer, each containing 16 memory cells. The current consumption of a single memory cell is 27 μA. The maximum input signal frequency is 10 MHz, and the sampling frequency is 25 MHz. The measurement results for the beamformer show a 60-dB signal-to-noise ratio after summation. The total current consumption of the chip, including the beamformer along with the bias generation and a digital controller, is 7 mA, and it occupies an active area of 1.3 mm
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.
Ultrasound imaging is widely used for medical diagnosis, because it is harmless to the human body and has real-time processing capability. Usually the focusing (beamforming) operation is performed for both TX and RX. The RX focusing is performed by an RX beamformer [1-5], which consists of delay elements and adders. Nowadays, digital beamformers (DBF) are mostly used for conventional ultrasound imaging because of high SNR. Recently, 2D ultrasound transducers have been introduced for 3D imaging. Since the 2D transducer has a huge number of transducer elements (e.g., 9216 for a 72×128 array), it cannot use DBF because of the huge number of required ADCs and wires inside the probe cable. Therefore, analog beamforming must be performed, at least at the front stage of the 2D transducer.In this work, where a 2D CMUT array is used, the maximum delay difference among transducer elements is 8μs with a maximum steering angle of 45° and a maximum focal depth of 15cm. The target sampling resolution is 6.25ns (λc / 53.3) with a carrier frequency of 3MHz. An analog-digital-hybrid architecture and a non-uniform sampling scheme are used for the RX beamformer of this work to achieve the wide dynamic range of delay time and small chip-area. The RX beamformer consists of 8 analog beamformers (ABF) followed by a single DBF, as shown in Fig. 24.8.1. An ABF performs the focusing operation for the input signals of the adjacent 8 channels to generate an analog output signal. The 8 analog output signals from the 8 ABFs are applied to the DBF. The DBF converts the 8 analog input signals into the 8 digital signals, and then performs the focusing operation on the 8 digital signals to generate a digital output signal for every focal point.
We present a system-on-a-chip (SoC) for use in high-frequency capacitive micromachined ultrasonic transducer (CMUT) imaging systems. This SoC consists of trans-impedance amplifiers (TIA), delay locked loop (DLL) based clock multiplier, quadrature sampler, and pulse width modulator (PWM). The SoC down converts RF echo signal to baseband by quadrature sampling which facilitates modulation. To send data through a 1.6 m wire in the catheter which has limited bandwidth and is vulnerable to noise, the SoC creates a pseudo-digital PWM signal which can be used for back telemetry or wireless readout of the RF data. In this implementation, using a 0.35-μm std. CMOS process, the TIA and single-to-differential (STD) converter had 45 MHz bandwidth, the quadrature sampler had 10.1 dB conversion gain, and the PWM had 5-bit ENoB. Preliminary results verified front-end functionality, and the power consumption of a TIA, STD, quadrature sampler, PWM, and clock multiplier was 26 mW from a 3 V supply.
To reduce the memory area, a two-stage RX beamformer (BF) chip with 64 channels is proposed for the ultrasound medical imaging with a 2D CMUT array. The chip retrieved successfully two B-mode phantom images with a steering angle from -45 (°) to +45 (°), the maximum delay range of 8 μs, and the delay resolution of 6.25 ns. An analog-digital hybrid BF (HBF) is chosen for the proposed chip to utilize the easy beamforming operation in the digital domain and also to reduce chip area by minimizing the number of ADCs. The chip consists of eight analog beamformers (ABF) for the 1st-stage and a digital beamformer (DBF) for the 2nd-stage. The two-stage architecture reduces the memory area of both ABF and DBF by around four times. The DBF circuit is divided into three steps to further reduce the digital FIFO memory area by around twice. Coupled with the non-uniform sampling scheme, the proposed two-stage HBF chip reduces the total memory area by around 40 times compared to the uniform-sampling single-stage BF chip. The chip fabricated in a 0.13- μm CMOS process occupies the area of 19.4 mm(2), and dissipates 1.14 W with the analog supply of 3.3 V and the digital supply of 1.2 V.
High frequency ultrasound arrays have applications ranging from imaging of small animals, skin and eye to intravascular ultrasound (IVUS). We describe an application where a guidewire IVUS system uses high frequency phased arrays with integrated electronics placed directly on the guidewire rather than a catheter for imaging. Multiple arrays provide the full transverse cross section of the artery during percutaneous interventions. We focus on a 1-D CMUT phased array to be used in the guidewire IVUS. CMUTs are particularly suitable for this application with their ease of fabrication and single chip electronics integration. The array frequency is chosen to be around 35-40MHz with 10MHz bandwidth so that the 1-D CMUT phased array with a 300um wide aperture can closely match the lateral resolution of a current 20MHz, 3.5F solid state IVUS array. Here we discuss the initial design, large signal modeling, fabrication and experimental characterization of a 12 element, 300×1000um CMUT array with 25um pitch. The electrical and acoustic characterization results for a CMUT array with 20um square membranes are presented. Modeling results for different size membranes indicating adequate performance for higher bandwidth applications are also discussed.
A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- μ m CMOS process with an active area of 16 mm (2). The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.
An Analog RAM architecture for beamforming based on switched current circuits is presented. The proposed architecture allows the sharing of the same bias current for different memory cells, hence results in a large amount of power saving. The beamformer consists of total 16 channels and in each channel a delay line with depth of 16 has been implemented. The input frequency is 10MHz and a sampling frequency of 25MHz is used. The proposed architecture achieves 50dB of dynamic range and 49dB of SNDR with power dissipation of 760μW for one channel. The ARAM is implemented in 180nm CMOS technology and occupies 250×150μm2 per channel.
Atherosclerosis is the main cause of coronary heart disease, which is today the leading cause of death worldwide and will continue to be the first in the world in 2030. In the formation of atherosclerotic coronary lesions, a critical primary step is the accumulation and oxidation of low-density lipoprotein (LDL) particles. Oxidized-LDL favours leucocyte recruitment and their activation, as well as cell death. This leads to generation of complex atherosclerotic plaques. These plaques have a high content of necrotic core, a thin inflamed fibrous cap (intense accumulation of macrophages) and scarce presence of smooth muscle cells (i.e. thin-capped fibroatheroma). At early stages of the formation of the atheroma, the remodelling of the vessel wall usually prevents plaque from encroaching on the lumen, thereby masking the presence of atheroma on angiography. In contrast, greyscale intravascular ultrasound can fully assess the extension of the disease axially and longitudinally. This intravascular imaging technique has played a vital role in advancing our understanding of the pathophysiology of coronary artery disease, and in the development of novel cardiovascular drugs and device therapies. This intravascular imaging technology and its clinical and research applications are discussed in more detail below.
A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm<sup>2</sup> in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.
Side-looking (SL) IVUS probes are extensively used for management of cardiovascular diseases. Currently SL-IVUS imaging probes use either a single rotating transducer element or solid-state arrays. Probes with single rotating piezoelectric transducer have simple front-end, but have fixed focused operation, and suffers from motion artifacts. Solid-state SL-IVUS imaging probes use piezoelectric transducer arrays and electronic beam-forming. Synthetic phased array processing of signals detected with small-sized elements in these arrays limits the SNR achievable with these probes. In this study, we explore a new SL-IVUS probe architecture employing rotating phased annular CMUT arrays. We tested and compared imaging performance of the existing and proposed probe configurations through simulated point spread functions. We also two fabricated sample annular array designs operating at 20-MHz and 50-MHz. Our experimental measurements on the 20-MHz array in oil shows 105% fractional bandwidth. The 50-MHz array with parylene coating shows approximately 40% fractional bandwidth measured in water. We also present imaging results acquired from wire-targets to test the experimental point-spread functions.
High frequency ultrasonic imaging is considered by many to be the next frontier in ultrasound. It has many clinical applications ranging from imaging the eye and skin to small animal imaging. Small animal imaging has recently generated intense interest for the purpose of evaluating the efficacy of drugs and gene therapy. Commercial high frequency scanners often termed "ultrasonic biomicroscope", or UBM, all use mechanically scanned single element transducers at frequencies between 30 to 60 MHz with a frame rate of 30 frames/second or lower. To alleviate problems with UBMs which include mechanical motion and fixed focusing, high frequency linear arrays and imaging systems in the 20-50 MHz range have been developed. In this paper, current efforts in the development of high frequency ultrasonic imaging will be reviewed and potential biomedical applications discussed.
Diagnostic Ultrasound Imaging provides a comprehensive introduction to and a state-of-the-art review of the essential science and signal processing principles of diagnostic ultrasound. The progressive organization of the material serves beginners in medical ultrasound science and graduate students as well as design engineers, medical physicists, researchers, clinical collaborators, and the curious. This it the most comprehensive and extensive work available on the core science and workings of advanced digital imaging systems, exploring the subject in a unified, consistent and interrelated manner. From its antecedents to the modern day use and prospects for the future, this it the most up-to-date text on the subject. Diagnostic Ultrasound Imaging provides in-depth overviews on the following major aspects of diagnostic ultrasound: absorption in tissues; acoustical and electrical measurements; beamforming, focusing, and imaging; bioeffects and ultrasound safety; digital imaging systems and terminology; Doppler and Doppler imaging; nonlinear propagation, beams and harmonic imaging; scattering and propagation through realistic tissues; and tissue characterization.
For phased-array ultrasound imaging, alternative beamforming techniques and their VLSI circuits are studied to form a fully digital receive front-end hardware. In order to increase the timing accuracy in beamforming, a computationally efficient interpolation scheme to increase the sampling rate is examined. For adaptive beamforming, a phase aberration correction method with very low computational complexity is described. Image quality performance of the method is examined by processing the non-aberrated and aberrated phased-array experimental data sets of an ultrasound resolution phantom. A digital beamforming scheme based on receive focusing at the raster focal points is examined. The sector images of the resolution phantom, reconstructed from the phased-array experimental data by beamforming at the radial and raster focal points, are presented for comparison of the image resolution performances of the two beamforming schemes. VLSI circuits and their implementations for the proposed techniques are presented.
The paper describes high-frequency 1D CMUT arrays designed and fabricated for use in electronically scanned high-resolution ultrasonic imaging systems. Two different designs of 64-element linear CMUT arrays are presented. A single element in each array is connected to a single-channel custom front-end integrated circuit for pulse-echo operation. The first design has a resonant frequency of 43 MHz in air, and operates at 30 MHz in immersion. The second design exhibits a resonant frequency of 60 MHz in air, and operates at 45 MHz in immersion. Experimental results are compared to simulation results obtained from the equivalent circuit model and nonlinear dynamic finite element analysis; a good agreement is observed between these results. The paper also briefly discusses the effects of the area fill factor on the frequency characteristics of CMUTs, which reveals that the transducer active area should be maximized to obtain a wideband response at high frequencies.
Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-μm SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-μm multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10<sup>-5</sup> to less than 10<sup>-12</sup>.
We designed and fabricated a dynamic receive beamforming integrated circuit (IC) in 0.35-µm CMOS technology. This beamformer is suitable for integration with an ultrasound annular array for high-frequency (30–50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC is capable of buffering, delaying and preamplification for 8 receive channels. We explored an analog delay cell based on a current-mode first-order all-pass filter, which is used as the basic building block to form an analog dynamic delay line. We also explored a bandwidth enhancement method on the delay cell that improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1 mW of power and is capable of generating a tunable delay between 1.75 ns to 2.5 ns, enabling dynamic receive beamforming over a focal range from 1.4 mm to 2 mm. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Our experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.
In this paper, a time delay circuit is designed for path mismatch compensation in the polar loop transmitter for the WiMAX standard. The delay circuit contains two stages, each realized in the second-order form of the Padé approximant, to account for a tuning range from 1 ns to 10 ns in 1 ns steps. The proposed circuit is fabricated using 0.35-μm SiGe technology in order to be incorporated into a fully integrated transmitter in the future. The measurement result in network analyzer shows the delay dispersion in worst case within 30 MHz signal bandwidth has 7% variation and has gain dispersion 1.4 dB.
Our research project is to design a readout IC for an ultrasonic transducer consisting of a matrix of more than 2000 elements. The IC and the matrix transducer will be put into the tip of a transesophageal probe for 3D echocardiography. A key building block of the readout IC, a programmable analog delay line, is presented in this paper. It is based on the time-interleaved sample-and-hold (S/H) principle. Compared with conventional analog delay lines, this design is simple, accurate and flexible. A prototype has been fabricated in a standard 0.35μm CMOS technology. Measurement results showing its functionality are presented.
A 2D array for acquiring 3D images is described. Interconnection methods are presented that connect elements of the array to integrated circuits (ICs) within the transducer. These ICs simultaneously process signals from ALL elements forming a fully sampled array. Comparisons are made with mechanical and sparse array solutions. Several signal processing options for use within the ICs are presented.
Annular arrays can operate with a small number of channels because the shape of the physical elements matches the acoustic phase fronts. The symmetry of the annular array provides axisymmetric focusing without the need for additional beamforming channels. An annular array structure can be constructed by connecting elements of a 2D array and therefore a similar reduction in the number of delay channels required can be achieved described by D. G. Bailey et al. and R. Bele (1987). We present simulation results for annular array apertures with a diameter of 20-26 mm and design frequency in the 5-8 MHz range. The simulations are used to determine the required number of annular rings (around 20), the effect of the size of the underlying 2D array elements (should be < 200 um), and the optimal ring widths for a particular design with 20 rings (325 um). Simulations of a 20 ring design with a 26 mm aperture show that the -6 dB beamwidths are less than 0.5 mm over a depth of field from 1 to 5 cm with a single transmit focus. The azimuthal and elevation beam widths are, as expected, equivalent. Experimental measurements of the field at the focal point show good agreement with the model.
Vibration of piezoelectric elements after electrical excitation creates ringdown artifacts in ultrasound images close to the transducer surface. For intraluminal applications, high quality images are often needed at depths close to the catheter surface. Consequently, ringdown artifacts pose a serious problem for intraluminal circumferential arrays. A current method to reduce these artificial echoes subtracts a precalibrated ringdown signal from each frame in a data set. The dynamic nature of the ringdown artifact, however, reduces the effectiveness of this subtraction algorithm with time following data collection. The ringdown signal has very distinctive characteristics, especially in the near field azimuthal spectrum. An in-depth study of those characteristics presents new alternatives to minimize ringdown artifacts. Using a set of depth-dependent azimuthal filters, we present a method to significantly reduce ringdown artifacts while minimally affecting the real signal. Rubber phantoms with embedded graphite particles were imaged close to the transducer surface to study potential improvements obtained with the azimuthal filters. Results show a reduction of the ringdown signal by at least 10 dB, while increasing the dynamic range between the real signal and the ringdown from 2 dB to 15 dB. The combination of azimuthal filtering with ringdown subtraction can greatly enhance contrast at ranges close to the transducer surface.
The authors designed and constructed a real-time phased-array
imaging system for medical applications based on the principles of
digital beam formation and autonomous channel control. The system is
capable of high-precision steering, dynamic apodization, dynamic
focusing, and highly accurate beamforming using sampling rates close to
the Nyquist rate over the medical diagnostic frequency range. All
controls and signal processing needed for a single channel of the array
imager have been integrated into a single custom VLSI circuit. The
authors describe the basic principles embodied in this chip
We present the analysis, design, and measurement results of a high-gain, low-noise differential transimpedance amplifier (TIA) designed to interface with electrostatic microelectromechanical systems (MEMS) resonators. A capacitive-feedback current amplifier drives current into an active load to obtain a 56 MOmega transimpedance gain, 1.8 MHz bandwidth, phase response near 0deg, and 65 fA/radicHz input-referred noise. The TIA was fabricated in 0.18 mum CMOS technology and dissipates 436 muW from a 1.8 V supply.
The proposed CMOS ultrasound transceiver chip will enable the development of portable high resolution, high-frequency ultrasonic imaging systems. The transceiver chip is designed for close-coupled MEMS transducer arrays which operate with a 3.3-V power supply. In addition, a transmit digital beamforming system architecture is supported in this work. A prototype chip containing 16 receive and transmit channels with preamplifiers, time-gain compensation amplifiers, a multiplexed analog-to-digital converter with 3 kB of on-chip SRAM, and 50-MHz resolution time delayed excitation pulse generators has been fabricated. By utilizing a shared A/D converter architecture, the number of A/D converter and SRAM is cut down to one, unlike typical digital beamforming systems which need 16 A/D converters for 16 receive channels. The chip was fabricated in a 0.35-mum standard CMOS process. The chip size is 10 mm<sup>2</sup>, and its average power consumption in receive mode is approximately 270 mW with a 3.3-V power supply. The transceiver chip specifications and designs are described, as well as measured results of each transceiver component and initial pulse-echo experimental results are presented.
This paper presents a solid foundation for implementing analog vector-matrix multipliers (VMMs) in field-programmable analog arrays (FPAAs). Custom analog VMMs have been demonstrated to be 1000 times more power efficient than commercial digital implementations. However, no previous analog VMM discussion has carefully provided all of the implementation and performance considerations needed to utilize such a system. We utilize the FPAA because it provides an ideal platform for embedding low-power analog processing into larger systems. FPAAs allow the analog processing system to be rapidly prototyped, implemented at low cost, and easily reconfigured in the field. This paper can double as a complete analog VMM design specification, as well as a systematic tutorial on developing general systems with FPAA hardware. We detail the aspects of VMM topology choice, completely analyze the performance metrics, and describe the methods and tools involved in FPAA synthesis.
Implementing beamforming for high frequency arrays is challenging because of the accurate delay requirements at high frequencies. High frequency digital beamforming is not suitable for catheter based applications as a large number of cables is required between the array and the external beamformer. A possible solution is to perform analog beamforming on an integrated circuit adjacent or monolithically integrated to the imaging array. In this study, we introduce an improved voltage in voltage out low pass filter as an analog delay cell for high frequency dynamic beamformers. This circuit can generate three times more delay with a given bandwidth when compared to conventional low pass filters. Delay of the circuit is tunable and the gain of the cell is inherently very close to unity. The proposed delay cell operates single ended and therefore is more suitable for CMUT operation which generates single ended output. We designed a test beamformer for a 30MHz, equal area, annular array with 100% bandwidth using the proposed delay cell and the unit-delay focusing architecture. Required delays are implemented using a delay line made up of improved delay elements with tunable delays. To demonstrate functionality we designed and fabricated a custom front-end IC in a 0.5¿m standard CMOS process. The IC chip consists of 8 transimpedance amplifiers, voltage-to-current converters, the analog dynamic beamformer, and two buffers. We present results of preliminary imaging experiments that demonstrate the focusing capability.
ΣΔ beamforming is a promising technique for small analog front-end (AFE) of the medical ultrasound imaging system. Nonetheless, the high data rate from the ΣΔ modulator in the AFE and the high-Q reconstruction filter put harsh requirements on the digital beamforming circuits. Although the BScan-sample-based ΣΔ beamformer structure with FIR reconstruction filter reduces the speed requirement on multipliers so as to make the ΣΔ beamformer implementable in conventional digital platforms, it still requires large area for high-speed adders. In this work, a new BScan-sample-based ΣΔ beamformer structure with IIR reconstruction filter is developed. The new structure greatly reduces the hardware cost. Both ΣΔ beamformers are implemented in FPGAs and digital ICs. The new beamformer is 8 times smaller than the FIR beamformer. For a 128-element, 5MHz ultrasound medical imaging system with 256 beamformers, the new ΣΔ beamformer can be implemented with 2 FPGA chips or a 5.2mmÃ5.2mm digital IC in 0.18μm CMOS logic process.
A variety of new devices in the field of intravascular ultrasound imaging are being designed and tested. Mechanical intravascular ultrasound (IVUS) devices with rotating transducers have been developed that allow transducer pullback with integrated longitudinal 2-dimensional displays. Recent advances in the area of imaging include (1) solid-state systems that combine ultrasound with balloon and stent placement; (2) combined imaging atherectomy devices; (3) imaging cores or guidewires; (4) forward-looking devices; (5) 3-dimensional reconstruction techniques; (6) high-frequency imaging; and (7) improved methods for characterizing tissue. Other promising approaches include magnetic resonance imaging, thermography, and optical coherence tomography. An important goal for long-term technologic improvement is visualization of lipid accumulations and fibrous caps during their early stages of development.
In order to improve the lateral resolution and extend the field of view of a previously reported 48 element 30 MHz ultrasound linear array and 16-channel digital imaging system, the development of a 256 element 30 MHz linear array and an ultrasound imaging system with increased channel count has been undertaken. This paper reports the design and testing of a 64 channel digital imaging system which consists of an analog front-end pulser/receiver, 64 channels of Time-Gain Compensation (TGC), 64 channels of high-speed digitizer as well as a beamformer. A Personal Computer (PC) is used as the user interface to display real-time images. This system is designed as a platform for the purpose of testing the performance of high frequency linear arrays that have been developed in house. Therefore conventional approaches were taken it its implementation. Flexibility and ease of use are of primary concern whereas consideration of cost-effectiveness and novelty in design are only secondary. Even so, there are many issues at higher frequencies but do not exist at lower frequencies need to be solved. The system provides 64 channels of excitation pulsers while receiving simultaneously at a 20-120 MHz sampling rate to 12-bits. The digitized data from all channels are first fed through Field Programmable Gate Arrays (FPGAs), and then stored in memories. These raw data are accessed by the beamforming processor to re-build the image or to be downloaded to the PC for further processing. The beamformer that applies delays to the echoes of each channel is implemented with the strategy that combines coarse (8.3 ns) and fine delays (2 ns). The coarse delays are integer multiples of the sampling clock rate and are achieved by controlling the write enable pin of the First-In-First-Out (FIFO) memory to obtain valid beamforming data. The fine delays are accomplished with interpolation filters. This system is capable of achieving a maximum frame rate of 50 frames per second. Wire phantom images acquired with this system show a spatial resolution of 146 μm (lateral) and 54 μm (axial). Images with excised rabbit and pig eyeball as well as mouse embryo were also acquired to demonstrate its imaging capability.
The visualisation of living tissues at microscopic resolution is attracting attention in several fields. In medicine, the goals are to image healthy and diseased tissue with the aim of providing information previously only available from biopsy samples. In basic biology, the goal may be to image biological models of human disease or to conduct longitudinal studies of small-animal development. High-frequency ultrasonic imaging (ultrasound biomicroscopy) offers unique advantages for these applications. In this paper, the development of ultrasound biomicroscopy is reviewed. Aspects of transducer development, systems design and tissue properties are presented to provide a foundation for medical and biological applications. The majority of applications appear to be developing in the 40-60-MHz frequency range, where resolution on the order of 50 microm can be achieved. Doppler processing in this frequency range is beginning to emerge and some examples of current achievements will be highlighted. The current state of the art is reviewed for medical applications in ophthalmology, intravascular ultrasound, dermatology, and cartilage imaging. Ultrasound biomicroscopic studies of mouse embryonic development and tumour biology are presented. Speculation on the continuing evolution of ultrasound biomicroscopy will be discussed.
High-frequency ultrasound (above 10 MHz) has been used successfully in many medical applications, including eye, skin, gastrointestinal, intravascular, and Doppler flow imaging. Most of these applications use single-element transducers, thereby imposing a tradeoff between resolution and depth of field. Fabrication difficulties and the need for high-speed electronic beamformers have prevented widespread use of arrays at high frequencies. In this paper, a unit-delay focusing architecture suitable for use with high-frequency ultrasound annular arrays is described. It uses a collection of identical, active delay cells that may be simultaneously varied to accomplish focusing. Results are presented for an analog integrated circuit intended for use with a five-element, 50-MHz planar annular array. Focusing is possible over an axial range for which the ratio of maximum to minimum f-number is 2.1. Unit-delay architectures also are described for curved annular arrays and linear arrays.
The design, fabrication, and performance of miniature high-frequency annular arrays are described. A 50-MHz, 2-mm-diameter, 7-element, equal-area annular array was fabricated and tested. The array elements were defined using photolithography and the electrical contacts were made using ultrasonic wire bonding. The resulting transducer produced pulses with a -6 dB bandwidth of 52% and an insertion loss of -16 dB. A radiation pattern was collected by scanning the transducer array above the tip of a glass fiber. A -6 dB two-way beam width of 75 microns was found at f/2. The radiation pattern decreased smoothly to less than -60 dB at a distance of 550 microns.
Digital transmit and receive beamformers for a 45-MHz, 7-element annular array are described. The transmit beamformer produces 0- to 80-Vpp monocycle pulses with a timing error of less than +/-125 ps. Up to four adjustable transmit focal zones can be selected. The dynamic receive beamformer uses a variable frequency sampling technique in which the frequency of analog-to-digital conversion on each channel is adjusted as the signals are received. The variable frequency clock signals required to trigger analog-to-digital conversion are obtained using a pair of high-frequency field-programmable gate arrays and a precision quartz oscillator. The gate arrays are also used to sum the digitized signals. A maximum receive beamformer timing error of less than +/-900 ps was obtained on each channel. The performance of the combined transmit and receive beamformer was tested by imaging wire phantoms. Images of CD-1 mice were also generated. The system produced images with a dynamic range of 60 dB.
This is the second part of a two-paper series reporting a recent effort in the development of a high-frequency annular array ultrasound imaging system. In this paper an imaging system composed of a six-element, 43 MHz annular array transducer, a six-channel analog front-end, a field programmable gate array (FPGA)-based beamformer, and a digital signal processor (DSP) microprocessor-based scan converter will be described. A computer is used as the interface for image display. The beamformer that applies delays to the echoes for each channel is implemented with the strategy of combining the coarse and fine delays. The coarse delays that are integer multiples of the clock periods are achieved by using a first-in-first-out (FIFO) structure, and the fine delays are obtained with a fractional delay (FD) filter. Using this principle, dynamic receiving focusing is achieved. The image from a wire phantom obtained with the imaging system was compared to that from a prototype ultrasonic backscatter microscope with a 45 MHz single-element transducer. The improved lateral resolution and depth of field from the wire phantom image were observed. Images from an excised rabbit eye sample also were obtained, and fine anatomical structures were discerned.
The purpose of the present study was to validate the diagnostic accuracy of optical coherence tomography (OCT), integrated backscatter intravascular ultrasound (IB-IVUS), and conventional intravascular ultrasound (C-IVUS) for tissue characterization of coronary plaques and to evaluate the advantages and limitations of each of these modalities.
The diagnostic accuracy of OCT for characterizing tissue types is well established. However, comparisons among OCT, C-IVUS, and IB-IVUS have not been done.
We examined 128 coronary arterial sites (42 coronary arteries) from 17 cadavers; IVUS and OCT images were acquired on the same slice as histology. Ultrasound signals were obtained using an IVUS system with a 40-MHz catheter and digitized at 1 GHz with 8-bit resolution. The IB values of the ultrasound signals were calculated with a fast Fourier transform.
Using histological images as a gold standard, the sensitivity of OCT for characterizing calcification, fibrosis, and lipid pool was 100%, 98%, and 95%, respectively. The specificity of OCT was 100%, 94%, and 98%, respectively (Cohen's kappa = 0.92). The sensitivity of IB-IVUS was 100%, 94%, and 84%, respectively. The specificity of IB-IVUS was 99%, 84%, and 97%, respectively (Cohen's kappa = 0.80). The sensitivity of C-IVUS was 100%, 93%, and 67%, respectively. The specificity of C-IVUS was 99%, 61%, and 95%, respectively (Cohen's kappa = 0.59).
Within the penetration depth of OCT, OCT has a best potential for tissue characterization of coronary plaques. Integrated backscatter IVUS has a better potential for characterizing fibrous lesions and lipid pools than C-IVUS.
This paper presents a low power high speed continuous-time (CT) delta-sigma modulator (DSM) for ultrasound application. The modulator was designed for a portable ultrasound digital beamformer to digitize ultrasound signal centered at 3.5 MHz with a fractional bandwidth of 0.6. A CMOS 0.18 mum 3<sup>rd</sup>-order low-pass DSM sampled at 200 MHz was implemented. A transconductor (G<sub>m</sub>) with improved linearity was proposed in order to reduce the power dissipation by increasing its linear input range. Simulation shows that the DSM can achieve a dynamic range of 61.5 dB and consume only 3.4 mW power at 1.8 V supply voltage.
This paper describes the design and implementation of a 64-channel beamformer for a 50 MHz linear array for use in medical imaging. The results for a series of theoretical models comparing various beamforming algorithms are given. The final algorithm is a compromise solution, applying a simple linear interpolation algorithm to a data set acquired using 4x interleaved sampling. This allows for 12 bit, 200 MS/s performance with a 50 MS/s ADC. This algorithm has been implemented on a Virtex 4 FPGA using a commercially available applications board featuring onboard SDRAM, oscillator, and parallel and serial communications. This board was tested with ideal data, as well as with an 8-channel analog board. There was excellent agreement between the hardware and computer simulation results.
Although side looking intravascular ultrasound (SL-IVUS) imaging systems using single element piezoelectric transducers set the resolution standard in the assessment of the extent of coronary artery disease, improvements in transducer performance are needed to perform harmonic imaging and high resolution imaging of vulnerable plaque. With their small channel count, annular arrays exploiting the inherent broad bandwidth of CMUTs and electronic focusing capability of integrated electronics provide a path for desired SL-IVUS imaging catheters. In this paper, we first describe the design, low temperature fabrication of an 840 mum diameter, 8 element CMUT annular array. Testing of the individual elements in oil shows a uniform device behavior with 100% fractional bandwidth around 20 MHz without including the effects of attenuation and diffraction. We also present linear scan imaging results obtained on wire targets in oil, tissue and tissue mimicking phantoms using both unfocused and dynamically focused transducers. The results for axial and lateral resolution are in agreement predicted by the simulations and show the feasibility of this approach for high resolution SL-IVUS imaging.
Fully sampled 2D arrays present severe and conflicting requirements in element count, interconnect density, impedance, autonomous delay and amplitude control, high bandwidth at high dynamic range, and power consumption. cMUT transducer elements can have arbitrary dimensions machined directly above integrated circuits. We have designed a circuit that fits within the area of a 2D array element and achieves good signal fidelity at practical power dissipation, while limiting interconnect to 1D array complexity. It incorporates several novel techniques that simplify the process of preamplification, time-varying gain, baseband mixing, A/D conversion and beam formation. This achieves the design goals with highly parallel information retrieval. We also describe a novel transmitter that images at high volume rates with similar penetration to a traditional probe. Such performance is useful for visualizing fast-moving anatomical structures, such as heart valves, in 3D. We show how the transmitter and receiver form a bistatic probe suitable for clinical use. Experimental data are presented to evaluate the image quality obtained from the receiver circuit. We analyze its noise, distortion and time-gain control (TGC) performance. The new approach appears competitive with 1D probes in all basic imaging parameters, and permits 3D scanning We also investigate transmitter performance. Finally, we compare two- way signal-to-noise ratio and penetration with the state of the art.
The 5-tap FIR structure uses 3rd-order linear-phase cells to implement delays of 500ps for a T/2 fractionally-spaced equalizer. To improve the bandwidth of the summing circuit, the design incorporates a transimpedance load, increasing the bandwidth by a factor of 3.6 over a conventional resistive load. The equalizer consumes 96mW with plusmn1.5V and occupies 0.26mm<sup>2</sup> in a CMOS 0.35mum process.
A new analog CMOS high-speed continuous-time FIR filter is presented. The filter has five taps with 6- bit weights and operates at an effective sampling rate of 606 MS/s. The circuit was fabricated in a 0.5 µm CMOS process and dissipates 51 mW while operating from a single 3 volt supply.
An integrated circuit capable of focusing a high-frequency ultrasound annular array is presented. It uses a novel unit-delay architecture to accomplish focusing of the array with a single control voltage. System measurements for a 5-element array indicate excellent pulse fidelity with a dynamic amplitude range of 60 dB at 50 MHz. This is the highest frequency single-chip ultrasound beamformer that has been demonstrated to date.
High-speed transimpedance amplifiers (TIAs) used at the front end
of optical fiber receivers present design challenges in the form of
trade-offs between input noise current, speed, transimpedance gain,
power dissipation, and supply voltage. This transimpedance amplifier in
0.6 μm CMOS exhibits 4.5 pA/√Hz average input noise current,
622 Mb/s data rate, and 8.7 kΩ transimpedance gain while
dissipating 30 mW from a 3 V supply
Growing demand for high-speed I/O on digital ICs creates an increasingly noisy environment in which phase-locked loops (PLLs), delay-locked loops (DLLs), and other clock generating blocks must function. This noise, typically in the form of supply noise and substrate noise, makes design of low-jitter PLLs and DLLs challenging. This paper describes both a DLL and PLL design based upon self-biasing techniques in which all bias voltages and currents are referenced to other generated bias voltages and currents. Self biasing leads to a number of desirable properties that include IC process independence, fixed damping factor, fixed bandwidth-to-operating-frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both damping factor and bandwidth-to-operating-frequency ratio are determined completely by a ratio of capacitors
A fully differential, Class-AB, log domain microbeamformer has been designed in a 60 GHz Si-Ge BiCMOS process. The demonstrated microbeamformer has four input channels and four delays, though the concept can easily be extended to any desirable configuration. The log domain, Class-AB architecture is perfect for medical ultrasound applications due to the fact that the received ultrasound signal has very low amplitude during the major part of the reception period. This leads to very low power consumption because of the Class-AB configuration. The delay-line in the microbeamformer is constructed using a cascade of low input impedance allpass filter cells. A simple implementation of the zero in the allpass filter helps to keep the overall power consumption low. The delay of each allpass filter cell is programmable through the adjustment of a tuning current. Due to the Class-AB architecture used, every source signal must be shaped by a signal preconditioning circuit before connected to the filter cells. A well-known preconditioning circuit has been modified to increase the dynamic range. The modification introduces noise cancellation as well as a method to increases the maximum signal swing. The dynamic range of one preconditioning cell is shown to increase 12.6 dB compared to the classic translinear circuit at a penalty of 15% increase in the power consumption. Signal-to-noise ratio of one allpass filter cell is typically 56.5 dB, and the global dynamic range of the same cell is typically 63.8 dB at an average power consumption of 3.5 mW when 16 input signals are connected to the filter. The power consumption at maximum signal amplitude for the microbeamformer having four input channels and four delays is 3.2 mW with a supply voltage of 2.5 V. In the intended application, the quiescent power consumption is a much better description of the average power consumption. This power consumption is 1.3 mW.
A new second-order all-pass filter with maximum achievable delay-bandwidth-product (DBW) is presented. The proposed circuit will be used as a wideband delay element in impulse radio ultra-wideband transceivers. Benefiting from a simple architecture, the proposed circuit achieves a 60 ps delay across a 10 GHz bandwidth, which is the largest delay ever reported over such a wide bandwidth. In addition, the most noticeable advantage of this delay circuit is the small variation of group delay across a wide frequency range, which means negligibly small phase distortion introduced by the circuit
Digital beamforming based on oversampled delta-sigma (/spl Delta//spl Sigma/) analog-to-digital (A/D) conversion can reduce the overall cost, size, and power consumption of phased array front-end processing. The signal resampling involved in dynamic /spl Delta//spl Sigma/ beamforming, however, disrupts synchronization between the modulators and demodulator, causing significant degradation in the signal-to-noise ratio. As a solution to this, we have explored a new digital beamforming approach based on non-uniform oversampling /spl Delta//spl Sigma/ A/D conversion. Using this approach, the echo signals received by the transducer array are sampled at time instants determined by the beamforming timing and then digitized by single-bit /spl Delta//spl Sigma/ A/D conversion prior to the coherent beam summation. The timing information involves a nonuniform sampling scheme employing different clocks at each array channel. The /spl Delta//spl Sigma/ coded beamsums obtained by adding the delayed 1-bit coded RF echo signals are then processed through a decimation filter to produce final beamforming outputs. The performance and validity of the proposed beamforming approach are assessed by means of emulations using experimental raw RF data.
A 64-element, high efficiency, ceramic piezoelectric array transducer operating at 20 MHz has been constructed for ultrasonic intraluminal imaging. The array is mounted on the surface of a 1.2 mm diameter catheter appropriate for coronary artery applications. Integrated into the catheter tip is a custom analog chip set permitting complete data capture from the array. That is, on each firing any combination of array elements can be selected independently as transmitter or receiver. Using data acquired in this way, a complete phased array aperture (i.e., independent transmit and receive apertures) can be synthesized. Reconstruction hardware based on a custom application specific integrated circuit (ASIC) has been designed and built to produce real-time images. Beam forming coefficients are derived using an optimal filtering approach accounting for the circular geometry of the array. Simulated and measured beam patterns for this system are compared. In addition, images of coronary anatomy acquired with the real-time system are displayed demonstrating the marked image quality improvement compared to previous synthetic aperture intraluminal systems.
A pipelined delay-sum architecture based on bucket-brigade devices was proposed as an analog beamformer for a micromachined piezoelectric ultrasonic sensor phased array. A parasitic-insensitive device structure was developed to optimize the device characteristics, and input attenuators were used to overcome bucket overflow. The beamformer, fabricated using a CMOS process, exhibited a total harmonic distortion of -45 dB and beamforming imperfection of less than -50 dB using a 100-kHz input signal with peak voltage of 400 mV.
There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-μm CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 μVrms and a power dissipation of 80 μW while consuming 0.16 mm<sup>2</sup> of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 μW while maintaining a similar noise-power tradeoff.
A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is
reported. Using array averaging and a wideband track-and-hold, a 6-b
flash ADC achieves better than 5.5 effective bits for input frequencies
up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input
at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB,
respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s.
The chip occupies 0.8-mm<sup>2</sup> active area, fabricated in
0.35-μm CMOS