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Improvement of one-dimensional module placement in VLSI layout design

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Abstract

This paper considers the building block method, which is one of the methods in VLSI layout design, and discusses the improvement of module placement assuming that a one‐dimensional placement of the modules is given as the initial placement. Discussions are made of the following: The case where net list given as the input is composed only of two‐terminal nets, which connect the external terminals and the modules. The placement improvement problem PMO is formulated, where the virtual connection length defined only by × coordinate is to be minimized while retaining the placement order of the modules. The algorithm to solve this problem, as well as the proof for the optimality, are presented. Then a problem PM1 with a constraint on the range of displacement of the module is considered, and it is shown that the problem can be solved by extending the algorithm for PMO. A problem PM2 is considered, which is an extension of PM1 by introducing in general the multiterminal net connecting modules and external terminals. It is shown that PM2 can be reduced to PM1. A problem PM3 is considered, where river routing is adopted as the connection model, and the connection length is to be minimized considering also y coordinates (separation). It is shown that the optimal solution can be obtained in a polynomial time of the number of modules and the number of nets.

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... In this work, we propose an error-free bundling approach that speeds up the wire length estimation, especially when the interconnection scale is large. Our approach is based on the fact that the total HPWL of the nets spanning between two blocks forms a piecewise linear convex function with respect to the relative position of the two blocks [13, 17]. With this function implemented as a lookup table, we can compute the total wire length promptly and precisely by binary-searching the table instead of scanning the nets one by one. ...
... Furthermore, we show that 3-pin nets can be bundled together with 2-pin nets. The contribution of this paper lies in the following aspects: @BULLET The piecewise linear wire length function is usually exploited for wire length optimization in the single-row fixedordering cell placement problem [3, 13, 17]. When facing the order-free block placement problem in which optimization by this function becomes a hard task, researchers turn to the omnipotent simulated annealing (SA) and totally forget about this function. ...
... The y wire length can be estimated similarly. An interesting fact is that the total x wire length of all the 2-pin nets between a pair of blocks is a piecewise linear convex function with respect to the relative x-position of the two blocks [13, 17]. An example can be found inFig. ...
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The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea is to bundle the 2-pin nets between block pairs, and mea- sure the wire length bundle by bundle, instead of net by net. Previous bundling method (5) introduces a huge error which compromises the performance. We present an error- free bundling approach which utilizes the piecewise linear wire length function of a pair of blocks. With the function implemented into a lookup table, the wire length can be computed promptly and precisely by binary search. Further- more, we show that 3-pin nets can also be bundled, result- ing in a further speedup. The effectiveness of our method is verified by experiments.
... A similar curve tting problem has been considered by Ohmura et al. (1990) and by Imai (1991): min ...
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