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Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding*1
Abstract
An alternative route to existing silicon on insulator (SOI) material technologies such as SIMOX (separation by implanted oxygen) and BESOI (bonded and etch-back SOI) is the new Smart-Cut process, which appears to be a good candidate to achieve ULSI criteria. The Smart-Cut process involves two technologies: wafer bonding and ion implantation associated with a temperature treatment which induces a in-depth splitting of the implanted wafer. The details of the Smart-Cut process, the physical phenomena involved in the different technological steps such as hydrogen implantation related mechanisms and wafer bonding are discussed. The characteristics of the final structure in terms of thickness homogeneity, crystalline defects, surface microroughness, and electrical characterization are presented. Other applications of this process are also highlighted.
... To prevent blistering, a thick, rigid substrate was bonded to the surface of the wafer where the microcavities were formed through ion implantation. This procedure induced the microcavities, initially formed in a vertical orientation, to evolve laterally [29]. This innovative approach has been applied to the Smart Cut ™ technology. ...
... In the first step, annealing is done within a temperature range of 400-600 • C to split the single-crystal silicon layer. In the second step, annealing near 1100 • C is carried out to enhance the bonding strength [29]. ...
... Additionally, by manipulating the oxidation time and polishing steps, the thickness of both the device layer and the BOX layer can be varied across a broad spectrum with high uniformity [37]. This technology permits the device layer thickness to range from as little as 4 nm to as much as 1.5 µ m, and the BOX layer thickness can vary from 5 nm up to 5 µ m [29,38,39]. Furthermore, the process's flexible design allows the utilization of high-quality seed wafers for the device layer, while less expensive, lower-quality wafers can be employed as handle wafers due to their supportive role. ...
Silicon-on-insulator (SOI) wafers offer significant advantages for both Integrated circuits (ICs) and microelectromechanical systems (MEMS) devices with their buried oxide layer improving electrical isolation and etch stop function. For past a few decades, various approaches have been investigated to make SOI wafers and they tend to exhibit strength and weakness. In this review, we aim to overview different manufacturing routes for SOI wafers with specific focus on advantages and inherent challenges. Then, we look into how SOI wafers are characterized for quality assessment and control. We also provide insights towards potential future directions of SOI technology to further accelerate ever-growing IC and MEMS industries.
... For the donor wafers, substrates can be refreshed and reused after each layer transfer operation. The cross-section image of the fabricated SOI wafer is shown in Figure 2b [34]. A dense and sharp interface without any defects can be observed by transmission electron microscopy (TEM), proofing the advantages of Smart Cut technology. ...
... This technology also provides new opportunities for growing and emerging fields, such as sensors, energy harvesting, flexibles electronics, photonics, and MEMS, etc. [41][42][43][44][45][46][47][48][49][50][51][52]. [34]. (c) Transferred GeOI interface observed by TEM [40]. ...
... (i-k) Application of the bonded GeSnOI wafer in the GeSn FinFET [56]. Reprinted with permission from ref. [34]. Copyright 1997 Japan Society of Applied Physics. ...
Wafer bonding technology is one of the most effective methods for high-quality thin-film transfer onto different substrates combined with ion implantation processes, laser irradiation, and the removal of the sacrificial layers. In this review, we systematically summarize and introduce applications of the thin films obtained by wafer bonding technology in the fields of electronics, optical devices, on-chip integrated mid-infrared sensors, and wearable sensors. The fabrication of silicon-on-insulator (SOI) wafers based on the Smart CutTM process, heterogeneous integrations of wide-bandgap semiconductors, infrared materials, and electro-optical crystals via wafer bonding technology for thin-film transfer are orderly presented. Furthermore, device design and fabrication progress based on the platforms mentioned above is highlighted in this work. They demonstrate that the transferred films can satisfy high-performance power electronics, molecular sensors, and high-speed modulators for the next generation applications beyond 5G. Moreover, flexible composite structures prepared by the wafer bonding and de-bonding methods towards wearable electronics are reported. Finally, the outlooks and conclusions about the further development of heterogeneous structures that need to be achieved by the wafer bonding technology are discussed.
... There are several different methods for producing "kerfless/kerffree" Si wafers without casting and sawing: the Direct Wafer ® production process to fabricate high-performance "kerfless" silicon wafers directly from molten silicon [2], the "Smart-cut" process [3], epitaxial growth using CVD on a porous Si substrate followed by exfoliation of the epi-Si wafer [4,5], and some others, like stress-induced lift-off processes, which for several reasons have not achieved practical application in PV so far. Moreover, the edge-defined, film-fed growth (EFG) technique [6] has been commercialised but has not been able to stay competitive with the Cz-Si approach due to low throughput, non-standard geometry, and high dislocation density resulting in lower cell efficiencies and increased brittleness. ...
... The most technologically advanced ion cut process is the Smart-Cut process [3], which involves hydrogen implantation followed by wafer bonding and annealing. This method allows the transfer of Si layers with required thickness. ...
This paper describes the high-rate (~1.5 μm/min) growth of Si films on Si supporting substrates with (100) crystallographic orientation at 600 °C, 800 °C, and 1000 °C in a vacuum environment of ~1 × 10−5 mbar using electron beam (e-beam) evaporation. The microstructure, crystallinity, and conductivity of such films were investigated. It was established that fully crystalline (Raman spectroscopy, EBSD) and stress-free epi-Si layers with a thickness of approximately 50 µm can be fabricated at 1000 °C, while at 600 °C and 800 °C, some poly-Si inclusions were observed using Raman spectroscopy. Hall effect measurements showed that epi-Si layers deposited at 1000 °C had resistivity, carrier concentration, and mobility comparable to those obtained for c-Si wafers fabricated through ingot growth and wafering using the same solar grade Si feedstock used for the e-beam depositions. The dislocation densities were determined to be ∼2 × 107 cm−2 and ∼5 × 106 cm−2 at 800 and 1000 °C, respectively, using Secco etch. The results highlight the potential of e-beam evaporation as a promising and cost-effective alternative to conventional CVD for the growth of epi-Si layers and, potentially, epi-Si wafers. Some of the remaining technical challenges of this deposition technology are briefly indicated and discussed.
... This latter property means that it could relax the criteria for the choice of materials in the previous section so all of GaAs, ZnS, ZnSe and CdTe could be used as waveguide cladding. Further, it is used on an industrial scale as part of the process to produce SOI wafers [179,180], although this requires annealing for stronger covalent bonding between the surfaces and reintroduces issues with lattice mismatch and dissimilar CTE [181]. ...
... an implantation of H + ions is used to create a layer of microscopic defects beneath the wafer surface, which will result in a crack along this layer and parallel to the surface when the wafer is annealed [179,180]. However, this is not suitable as the heating will also lead to chemical bonding at the interfaces and therefore defects due to lattice mismatch. ...
Mid-infrared group IV photonics is a field which, by adapting techniques from silicon photonics at visible and near-infrared wavelengths and using mature semiconductor fabrication processes, could establish an enabling technology for a diverse range of applications in numerous areas. In particular, integrated photonic sensors could take advantage of the characteristic absorptions of many chemicals at mid-infrared wavelengths, due to strong fundamental molecular vibrations in this region. Such “lab-on-a-chip” devices would be applied to areas like medical diagnostics and environmental monitoring.To develop complex mid-infrared photonic integrated circuits, a set of corebuilding-block components are required. Currently, the components in mid-infrared group IV photonics are limited to operating at relatively narrow wavelength ranges. This lack of spectral bandwidth is not an issue for some applications, but to unlock the full potential of the field, it is essential to develop wideband devices.The operating wavelength range of mid-infrared devices may be limited by absorptions of the material platform or the geometry of the component; this work considers both to increase the available spectral bandwidth. Silicon-on-insulator waveguides with propagation losses ∼1.5 dB/cm are shown to only support the fundamental mode over an octave of frequency, as an experimental demonstration of a technique that in principle will be applicable to much of the mid-infrared range. Beam splitters were fabricated on silicon-on-insulator platforms with low insertion losses and high performance over a bandwidth of 3.1 − 3.7 μm: multimode interferometers are shown with an insertion loss of <1 dB and imbalance of <0.5 dB; and an insertion loss of ∼0.2 dB was achieved for 50/50 Y-splitters. Further, considering material platforms, silicon membrane devices have been successfully transfer printed onto a high-transparency zinc selenide substrates, to develop waveguides without substrate absorption losses.
... The G centers are activated when a Si wafer containing C impurities (incorporated either during growth or by implantation) is annealed and subsequently irradiated with high-energy protons [24]. For this reason, G centers are inherent to SOI substrates fabricated by the smart-cut technique, in which the annealing and proton irradiation are the essential steps [26]. In the pristine sample, the concentration of the G centers is expected to be non-monotonically distributed along the depth. ...
... In the pristine sample, the concentration of the G centers is expected to be non-monotonically distributed along the depth. The projected range of the implanted protons during the SOI fabrication process [26] results in a higher background signal close to the top surface. Therefore, we perform a XY confocal PL scan at some depth below the surface (Z = 12 µm) as presented in Fig. 3(a). ...
We create and isolate single-photon emitters with a high brightness approaching 10^5 counts per second in commercial silicon-on-insulator (SOI) wafers. The emission occurs in the infrared spectral range with a spectrally narrow zero phonon line in the telecom O-band
and shows a high photostability even after days of continuous operation. The origin of the emitters is attributed to one of the carbon-related color centers in silicon, the so-called G center, allowing purification with the 12C and 28Si isotopes. Furthermore, we envision a concept of a highly-coherent scalable quantum photonic platform, where single-photon sources, waveguides and detectors are integrated on the same SOI chip. Our results provide a route towards the implementation of quantum processors, repeaters and sensors compatible with present-day silicon technology.
... It can also intentionally create crystal defects using inert gas ions, and the defect depth and density are arbitrarily tuned by controlling the ion energy and dose. Implantation damages have been positively and extensively utilized for wafer splitting, 23 impurity gettering, 24 and strain engineering 25,26 in the fields of three-dimensional semiconductors. Therefore, it can be expected ARTICLE pubs.aip.org/aip/adv that ion implantation is also helpful for a structural transformation based on crystal defect formation in two-dimensional materials. ...
We report on the formation of a tellurium nanosheet with a MoOx cap by thermal annealing of ion-implanted 2H–MoTe2 multilayers. The presence of crystal defects generated by ion implantation at an energy of 90 keV accelerates the incorporation of O atoms and the surface desorption of Te atoms in the defective MoTe2 during thermal annealing, and subsequently, a tellurium nanosheet is formed around the bottom regions in the defective MoTe2 due to tellurium segregation. For the angle-resolved Raman spectroscopy, polar plots exhibit two-fold and four-fold symmetries for peak intensities of 121 and 143 cm−1, respectively, signifying the structural anisotropy of the tellurium nanosheet. On reducing the ion energy, the two Raman peak intensities collected from the tellurium nanosheet remarkably decrease, and they disappear for the sample at 30 keV. On the other hand, the decrease of the implantation energy increases the E2g peak intensity at 235 cm−1, which corresponds to the in-plane vibration mode of 2H–MoTe2. The distribution of crystal defects along the depth direction tuned by ion implantation energy is very critical for the formation of a tellurium nanosheet with structural anisotropy from the 2H–MoTe2 multilayers.
... One crucial factor driving the commercial feasibility of this technological revolution is the high-volume availability and cost-effectiveness of silicon-on-insulator (SOI) wafers. These SOI wafers, prepared using the 'smart-cut', i.e. ion slicing techniques [10], enable the manufacturing of silicon photonic integrated circuits but crucially have a significantly larger magnitude of usage in consumer microelectronics. Today, globally more than 3 million wafers are produced per year in SOI, as large as 300 mm in diameter [8]. ...
Photonic integrated circuits based on Lithium Niobate have demonstrated the vast capabilities afforded by material with a high Pockels coefficient, allowing linear and high-speed modulators operating at CMOS voltage levels for applications ranging from data-center communications and photonic accelerators for AI. However despite major progress, the industrial adoption of this technology is compounded by the high cost per wafer. Here we overcome this challenge and demonstrate a photonic platform that satisfies the dichotomy of allowing scalable manufacturing at low cost, while at the same time exhibiting equal, and superior properties to those of Lithium Niobate. We demonstrate that it is possible to manufacture low loss photonic integrated circuits using Lithium Tantalate, a material that is already commercially adopted for acoustic filters in 5G and 6G. We show that LiTaO3 posses equally attractive optical properties and can be etched with high precision and negligible residues using DUV lithography, diamond like carbon (DLC) as a hard mask and alkaline wet etching. Using this approach we demonstrate microresonators with an intrinsic cavity linewidth of 26.8 MHz, corresponding to a linear loss of 5.6 dB/m and demonstrate a Mach Zehnder modulator with Vpi L = 4.2 V cm half-wave voltage length product. In comparison to Lithium Niobate, the photonic integrated circuits based on LiTaO3 exhibit a much lower birefringence, allowing high-density circuits and broadband operation over all telecommunication bands (O to L band), exhibit higher photorefractive damage threshold, and lower microwave loss tangent. Moreover, we show that the platform supports generation of soliton microcombs in X-Cut LiTaO3 racetrack microresonator with electronically detectable repetition rate, i.e. 30.1 GHz.
... Two kind of substrates are used for the growth of a-Si:H films. One is silicon on insulator (SOI) 48) and the other is c-Si wafers. These substrates are placed on the GND electrode, where the growth temperature is controlled by a heater assembled in the electrode. ...
The surface passivation of crystalline silicon (c-Si) is studied during growth of hydrogenated amorphous silicon (a-Si:H) by means of plasma-enhanced chemical vapor deposition (PECVD). The surface passivation is characterized by an in-situ method of the photocurrent measurement of c-Si during the growth of an a-Si:H passivation layer at various growth temperatures. The passivation is also characterized by an ex-situ method of the carrier lifetime measurement performed at room temperature in air. According to both the in-situ and ex-situ results, the surface passivation is found to be optimized around a growth temperate of 200C, where the defect reduction and the band offset formation at the a-Si:H/c-Si interface play important roles.
... In the experiment, silicon on insulator (SOI) [137] is used as a substrate. There are two beneficial points to adapt a SOI substrate, with respect to a neat silicon wafer. ...
Plasma-induced defects are often recognized in state-of-the-art semiconductors, high-efficiency solar cells and high-sensitivity image sensors. These defects are in the form of a dangling bond, bond deformation, or impurity/residual, which impacts on the device performance and reliability. The defects are introduced via plasma-material interactions during manufacturing processes such as deposition, etching and implantation. So, the management of defects throughout the manufacturing is important for high-performance device fabrication. In this review, we overview the generation and recovery of plasma-induced defects in order to develop the defect-managed advanced plasma processing for further improving the device performances. The defect generation and recovery kinetics are explained, based on the recent results of in-situ and real-time detection of plasma-induced defects. Two examples are presented: the growth of hydrogenated amorphous silicon (a-Si:H) and the surface passivation of crystalline silicon for high-efficiency solar cell applications.
... It thus appears that electronic-grade silicon, in principle, could constitute a rather clean environment for applications in quantum optics that, in contrast with III-V or SiC, overcomes any problem related to alloy disorder. However, we also note that, this estimation may be a lower bound for the number of emitting impurities in pristine samples [49], given the existence of several unavoidable and uncontrolled issues, such as the presence of interfaces between the SOI and the underlying BOX, impurities at the wafer top surface and impurities introduced during the SOI fabrication (e.g. via oxygen implant for SIMOX or proton implant for Smart-Cut [50,51]). ...
The aim of this thesis it to explore the potential of complex carbon impurities in silicon (G-centers) for applications in quantum technologies. This point defect was originally highlighted in carbon-rich Si samples undergoing high-energy electron irradiation followed by high temperature annealing. A key feature of G-centers is their infrared emission, matching the important optical telecommunications wavelength O-band spreading between 1260-1360 nm. Through my PhD work we have demonstrated that we are able to create individual G-centers by ion implantation in conventional silicon on insulator, isotopically purified 28Si on insulator, and embed these emitters in photonic nanostructures such as dielectric Mie resonators. The creation of single defects was demonstrated by measuring the anti-bunching in light intensity-correlation (second order auto-correlation function). We developed a low-resolution optical lithography and plasma etching method joined with solid state dewetting (defined in chapter 4.3) of monocrystalline, ultra-thin, silicon on insulator to form monocrystalline, atomically smooth, Mie resonators in well-controlled and large, periodic arrays. By integrating light emitting G-centers within the Si-based antennas we engineered the light emission by tuning carbon dose, beam energy and islands size in order to optimize the coupling between the emitters and the Mie resonances in space and frequency. Directional (Huygens-like) light emission at 120 K was demonstrated experimentally and confirmed by Finite Difference Time Domain simulations. We estimate that, with an optimal coupling of the G-centers emission with the resonant antennas, a collection efficiency of about 90% can be reached using a conventional objective lens. The integration of these telecom-frequency emitters in resonant antennas is relevant for their efficient exploitation in quantum optics applications and more generally to Si-based photonic metasurfaces.
... Later, the Smart-Cut® technique [6] would make the interface between Si and buried SiO2 as good as the best MOS device interfaces, making characterization techniques like pseudo-MOS less necessary. ...
This paper presents a historical analysis of reconfigurable field effect transistors (RFETs). History shows the naturalness of its development from the evolution of integrated circuits (ICs) technology. Next, its operating principles are detailed to further study the variety of structures proposed in the specialized literature. Among these structures, the Back Enhanced SOI MOSFET (BESOI MOSFET) has been studied in detail, which stands out for its simplicity of fabrication and the possibility of integration with conventional technologies. The BESOI MOSFET is used to present proofs of concept for RFET applications such as: reconfigurable digital circuits, light sensor, permittivity-based biosensor and charge-based biosensor. The latter may allow, for example, obtaining a glucose sensor. Finally, future perspectives of applications of RFETs are presented, as in systems of protection of the intellectual property of ICs.
... Le Smart Cut ® marque une étape décisive dans la recherche de couches minces au silicium cristallin. C"est un procédé qui a permis de relier directement l"énergie d"implantation à la profondeur des ions implantés pour arriver à un détachement contrôlé [54][55][56]. Dans son élaboration destinée à la microélectronique, la couche obtenue a une épaisseur comprise entre quelques dizaines de nanomètres à 2 micromètres, correspondant à des énergies d"implantation dans la gamme des keV. Cette faible épaisseur est soutenue par un autre wafer qu"on appelle raidisseur [57]. ...
Les cellules solaires à base de silicium mono et multi cristallin dominent le marché du photovoltaïque. En effet, plus de 90% des panneaux sur le marché sont à base de silicium. Cependant, il se pose au moins deux problèmes majeurs qui impactent les cellules à base de ce matériau. D’abord, leur rendement au laboratoire est de 26,3%, une valeur proche de la limite théorique de 29,4% d’après la théorie Shockley Queisser. Ensuite, le coût de production des cellules à base de silicium est élevé à cause entre autres, des pertes de matière première. Ces deux problématiques ont été abordées d’une part en réduisant l’épaisseur du silicium et d’autre part en intégrant ces couches dans une structure tandem. Pour absorber le spectre solaire, classiquement on utilise des couches de 200µm, alors que des épaisseurs inférieures à 100 µm seraient suffisantes. L’implantation d’hydrogène à haute énergie permet de réaliser des substrats d’épaisseur variant de 15 à 100 µm. Ainsi, nous avons obtenu des substrats de 48 et 70 µm avec des énergies d’implantation respectivement de 2 et 2,5 MeV. C’est un procédé fiable et reproductible. Cependant, la réduction de l’épaisseur peut entrainer une création importante de défauts dans le substrat si un traitement n’est pas appliqué après le détachement. Des études par simulation, sous le logiciel SILVACO-TCAD, nous ont permis d’étudier l’impact des recombinaisons en surface et en volume sur les performances des cellules solaires à base de couches minces de silicium cristallin. Des mesures de durées de vie des porteurs minoritaires photo générés par la méthode Quasi- Steady- State Photoconductance (QSS-PC) ont été réalisées afin de mesurer l’impact des contraintes résiduelles après le détachement. Par ailleurs, nous avons utilisé ces films de silicium pour servir de cellule Bottom (cellule d’en bas) dans des structures de type tandem. Des simulations sur le logiciel SCAPS-1D ont été réalisées pour étudier les performances d’une telle cellule combinant le CZTS (Copper, Zinc, Tin, Sulfide) (Top cell, cellule d’en haut) et le silicium cristallin en couche mince (Bottom cell) dont un rendement de conversion de plus de 27% a été obtenu.
... As shown in Fig. 6a, a 4-inch GaAs thin film was successfully transferred onto the SiO 2 /Si (100) substrate with an area ratio of the transferred GaAs thin film to the donor GaAs wafer larger than 90%. The dispersive large voids were induced by the contaminants or particles on the bonding surfaces [14,27]. Fig. 6b shows a typical cross-sectional SEM image of the GaAs-on-Si hetero-structure, in which the total thickness of the transferred GaAs film is about 640 nm. ...
Heterogeneous integration of single-crystalline GaAs thin film on a Si substrate provides a promising material platform for Si-based optoelectronic integration. In this work, based on the clarified splitting mechanism of GaAs, the ion implantation conditions for GaAs film transfer were optimized. It was found that the co-implantation of He and H ions is more efficient in exfoliating the GaAs thin film with a lower thermal budget and lower density of defects in comparison with the case of the single He/H ion implantation. With the Al2O3 as the bonding intermediate layer, a 4-inch GaAs film was successfully transferred onto the Si (100) substrate via the optimized ion-slicing technique. The surface treatments, including chemical mechanical polishing, ozone oxidation, and KOH cleaning, were explored to improve the surface quality of the as-transferred GaAs thin film to the level of epi-ready. After post-annealing at 400°C for 1 h, the quality of the transferred GaAs thin film was further improved with only 89.03 arcsec for the full width at half maximum of the X-ray rocking curve.
... In this short review, we will only focus on the application of light ion irradiation in tailoring the electronic properties of emerging functional materials [16][17][18][19] and in modifying the dynamic performance of semiconductor power devices [20,21] . The other applications, such as doping semiconductors and "smart cut" [22,23] , are not covered. ...
In this review, the application of light ion irradiation is discussed for tailoring novel functional materials and for improving the performance in SiC or Si based electrical power devices. The deep traps and electronic disorder produced by light ion irradiation can modify the electrical, magnetic, and optical properties of films (e.g., dilute ferromagnetic semiconductors and topological materials). Additionally, benefiting from the high reproducibility, precise manipulation of functional depth and density of defects, as well as the flexible patternability, the helium or proton ion irradiation has been successfully employed in improving the dynamic performance of SiC and Si based PiN diode power devices by reducing their majority carrier lifetime, although the static performance is sacrificed due to deep level traps. Such a trade-off has been regarded as the key point to compromise the static and dynamic performances of power devices. As a result, herein the light ion irradiation is highlighted in both exploring new physics and optimizing the performance in functional materials and electrical devices.
... La conductivité thermique de Cr 2 AlC est proche de celle du Zircaloy-4, idéale pour assurer les échanges de chaleur entre le combustible et le fluide caloporteur dans le cas d'applications pour les EATFs. Toutefois, le coefficient de dilatation thermique de Cr 2 AlC est deux fois plus élevé que celui du Zircaloy-4, ce qui pourrait entrainer de la fissuration lors de grandes variations de température.Table I.3 -Présentation de quelques propriétés de la phase MAX Cr 2 AlC et du Zircaloy-4.Elle est très utilisée en science des matériaux, et plus particulièrement en microélectronique pour le dopage de semi-conducteurs ou pour la préparation de substrats de silicium sur oxyde (SOI pour Silicon On Insulator ) en utilisant la technologie Smart Cut[52]. L'implantation ionique est aussi utilisée pour former des nanoparticules dans les oxydes. ...
L’objectif de cette étude est de comprendre le comportement sous irradiation de la phase MAX Cr2AlC, dont les propriétés mécaniques et la résistance à l’oxydation permettent d’envisager des applications dans les réacteurs nucléaires. Pour cela, des films minces polycristallins et des monocristaux de Cr2AlC ont été implantés avec des ions He+. L’influence de la dose et de la température d’implantation sur l’état microstructural de Cr2AlC, mais aussi l’effet des recuits post-implantation, ont été caractérisés par DRX, MET et mesures de résistivité. Ces expériences ont permis de comprendre la formation progressive de la phase désordonnée γ-Cr2AlC et les mécanismes de déformation associés.Pour les implantations à température ambiante (RT), on observe une formation rapide d’antisites Cr/Al ne générant pas de déformation mais modifiant fortement la résistivité. L’interprétation des mesures de DRX permet de montrer que la déformation provient de la création de paires de Frenkel de C. Nous avons également déterminé une concentration seuil d’hélium implanté pour la formation de bulles. Pour les plus fortes fluences, des nano fissures se forment dans la région implantée ainsi que des cloques en surface, relaxant les contraintes emmagasinées. L’absence d’amorphisation des monocristaux même pour un endommagement important (30 dpa) suggère un effet significatif des joints de grains sur cette transformation.Lorsque la température d’implantation augmente, la saturation en défauts conduisant à la formation de la phase désordonnée intervient pour des fluences plus élevées. De plus, nos résultats suggèrent que la transition de phase est favorisée par la présence d'hélium.Les recuits de monocristaux implantés à RT nous ont permis de suivre la relaxation de la déformation. Différents mécanismes sont proposés pour expliquer cette relaxation allant de la recombinaison des défauts ponctuels à faible température jusqu’à la dissociation des complexes Hen-Vm à plus haute température.
... The nanochip was a field-effect nanotransistor designed on the basis of a silicon-on-insulator structure. SOI structures were made with the implementation of a similar Smart Cut technology [28], but with a number of differences. It is known that the technology is based on hydrogen-induced transfer of silicon layers onto the handle plate. ...
A nanoribbon biosensor (NRBS) was developed to register synthetic DNAs that simulate and are analogous to miRNA-17-3p associated with colorectal cancer. Using this nanoribbon biosensor, the ability to detect miRNA-17-3p in the blood plasma of a patient diagnosed with colorectal cancer has been demonstrated. The sensing element of the NRBS was a nanochip based on a silicon-on-insulator (SOI) nanostructure. The nanochip included an array of 10 nanoribbons and was designed with the implementation of top-down technology. For biospecific recognition of miRNA-17-3p, the nanochip was modified with DNA probes specific for miRNA-17-3p. The performance of the nanochip was preliminarily tested on model DNA oligonucleotides, which are synthetic analogues of miRNA-17-3p, and a detection limit of ~10−17 M was achieved. The results of this work can be used in the development of serological diagnostic systems for early detection of colorectal cancer.
... On the other hand, the wafer-bonded (100) GOI substrate, prepared by SOITEC through the Smart-cut technology, 22,23) has a ∼90 nm thick Ge layer with a slight tensile strain of ∼0.18% and a ∼140 nm thick SiO 2 capping layer. The thickness of BOX SiO 2 and a Si supporting substrate is 150 nm and ∼750 μm, respectively. ...
It is demonstrated in this work that a high temperature thermal process including oxidation and N2 annealing at 850 oC can provide tensile strain of ~0.58 % at maximum into Ge-on-Insulator (GOI) structures without any special patterning or external stressors. The different impacts of oxidation and annealing on tensile strain generation, surface roughness and crystal qualities in the GOI structures fabricated by Ge condensation and wafer bonding are systematically examined. Tensile strain of 0.47 % is achieved without severe thermal damages under the optimal thermal process condition, which indicates the high potential of the present method for improving the performance of GOI n-channel MOSFETs. The influence of thermal expansion mismatch between Ge and SiO2 are suggested as a possible physical origin of high amount of tensile strain into GOI structures.
... An iterative algorithm optimises the GOTFET structures such that the lower V tl = V dd /3, higher V th = 2V dd /3, and the performance of the proposed CGOT NTI, PTI & STI cells are much better than the CMOS NTI, PTI & STI cells. The proposed GOTFETs can be fabricated using the steps listed in [18,[23][24][25]. ...
This work reports low and high threshold gate-overlap tunnel FET (GOTFET) devices for ternary logic applications. An iterative numerical algorithm was developed, which optimises the GOTFET structure such that its characteristics are far superior to the equally-sized MOSFET at the same technology node. These devices are designed in such a way that the low and high Vt (LVT & HVT) are Vtl=Vdd/3 and Vth=2Vdd/3 respectively, with the ranges (0⋯Vdd/3), (Vdd/3⋯2Vdd/3) & (2Vdd/3⋯Vdd) representing 0, 1 & 2 states respectively. The performance of the GOTFETs is explained with physical explanations and models of device operation. Optimised GOTFETs were benchmarked with standard MOSFETs for the same circuits designed using the same technology. We have used 45 nm technology for all benchmarking purposes, since it is the lowest industry-standard technology library freely available for academic purposes. Proposed GOTFETs have on currents Ion roughly twice, and off currents Ioff at least an order lower than the corresponding MOSFETs. Furthermore, this work proposes a method to effectively suppress the ambipolar behaviour of GOTFETs with improved device performance, engineering the appropriate drain doping concentration, and a gate overlap/underlap on the source and drain regions. The performance of the optimised complementary GOTFET (CGOT) negative ternary inverter (NTI), positive ternary inverter (PTI) & standard ternary inverter (STI) cells were benchmarked with equivalent CMOS circuits. The overall PDP of the CGOT ternary cells were 99.9% lower than the corresponding CMOS cells. The proposed CGOT ternary cells will serve as the starting point for any ternary logic applications.
... However, the complex lattice structures in the LN crystal lead to lattice mismatching between the thin film and substrate, subsequently seriously affecting the quality of the epitaxial film. To address this problem, an emerging technique, known as "Smart-Cut," was introduced to acquire high-quality single-crystal LN thin film (Bruel, 1995;Bruel et al., 1997). This technology has proven to be very advantageous in preparing LN thin films on insulators (LNOI), which structure is similar to the POS substrate (Rabiei and Gunter, 2004;Poberaj et al., 2009;Poberaj et al., 2012;Ma et al., 2014;Wang et al., 2018;Luo et al., 2019;Michael et al., 2019). ...
This paper studied the manufacturing process of Piezoelectric-on-Silicon (POS) substrate which integrates 128° Y–X Lithium niobate thin film and silicon wafer using Smart-Cut technology. The blistering and exfoliation processes of the He as-implanted LN crystal under different annealing temperatures are observed by the in-situ method. Unlike the conventional polishing process, the stripping mechanism of the Lithium niobate thin film is changed by controlling annealing temperature, which can improve the surface morphology of the peeling lithium niobate thin film. We prepared the 128° Y–X POS substrate with high single-crystal Lithium niobate thin film and surface roughness of 3.91 nm through Benzocyclobutene bonding. After simulating the surface acoustic wave (SAW) characteristics of the POS substrate, the results demonstrate that the Benzocyclobutene layer not only performs as a bonding layer but also can couple more vibrations into the LN thin film. The electromechanical coupling coefficient of the POS substrate is up to 7.59% in the Rayleigh mode when h LN/λ is 0.3 and h BCB/λ is 0.1. Therefore, as a high-performance substrate material, the POS substrate has proved to be an efficient method to miniaturize and integrate the SAW sensor.
... Pour éviter ces effets de canaux courts, il est alors nécessaire d'augmenter la capacité du diélectrique de grille. Il a alors fallu introduire de nouvelles architectures de grille tel que les structures FinFET (pour Fin Field Effect Transistor) où la zone active sous forme d'aileron possède 3 faces recouvertes par la grille [Hisamoto 1998] ou bien FDSOI (Fully Depleted Silicon On Insulator) qui conserve l'architecture planaire de grille sur des substrats SOI, ce qui permet de diminuer les capacités parasites entre la source et le drain [Fenouillet-Beranger 2009, Bruel 1997](cf. Fig.1.2). ...
Depuis une dizaine d’années, l’industrie du semi-conducteur fait face à un défi sans précédent : structurer la matière dans des gammes de dimensions nanométriques avec des facteurs d’aspect toujours plus grands et avec une précision atomique. Or, les technologies plasmas conventionnelles reposant sur l’utilisation de réacteur plasma basse pression à source inductive (ICP) ou capacitive (CCP) ne répondent plus aux exigences de la miniaturisation des dispositifs avancés de la microélectronique. En 2013, le Leti/CEA et le LTM proposèrent un nouveau concept de gravure aux résultats intéressants pour faire de la gravure sélective anisotrope d’espaceurs Si3N4. Ce procédé repose sur deux étapes : une étape d’implantation d’ions légers qui modifie le matériau sur quelques nanomètres suivie d’une étape de retrait sélectif par gravure humide ou par plasma délocalisé en NH3/NF3. Initialement, ce concept nécessitait deux équipements pour réaliser le procédé. Or en 2016, le LTM a acquis un prototype de réacteur permettant de réaliser ces deux étapes au sein d’une même enceinte grâce à un mode de fonctionnement standard CCP (pour l’implant), et un mode en plasma délocalisé permettant une gravure sélective à partir d’espèces neutres uniquement. Dans ce contexte, l’objectif de ces travaux de thèse est de démontrer le potentiel de ce prototype de réacteur pour faire de la gravure anisotrope sélective et de l’appliquer aux procédés d’espaceurs Si3N4. Pour atteindre cet objectif, il a fallu comprendre les mécanismes impliqués dans les deux étapes du procédé. L’étude des implantations à base de plasma d’He ou d’H2 a montré que la profondeur de modification est contrôlée par le flux et l’énergie des ions. De plus, si le plasma d’He conduit essentiellement à la rupture de liaisons Si-N dans le matériau, l’hydrogène induit, lui, la création de liaisons Si-H et N-H. L’étude des cinétiques de gravure par ellipsométrie cinétique de Si3N4 et SiO2 en plasma délocalisé de NH3/NF3 a montré que la gravure de ces films se fait via la formation d’une couche de sels (NH4)2SiF6 et d’un temps d’incubation avant le début de la réaction. Le film est consommé lors de la formation de la couche de (NH4)2SiF6 et les espèces réactives diffusent au travers de la couche de sel fluoré causant un ralentissement de la vitesse de gravure. Des études des cinétiques de gravure en fonction de la température du substrat et des ratios de gaz ont montré que le temps d’incubation est dû à une compétition entre les mécanismes de chimisorption des espèces réactives physisorbées à la surface du film et de désorption de ces dernières sous l’effet de la température du substrat. Une augmentation de la température favorise la désorption des réactifs plutôt que la chimisorption, entrainant une augmentation du temps d’incubation et un ralentissement des cinétiques de gravure. En modifiant l’état de surface par une implantation He ou H2, nous avons montré qu’il est possible de réduire les temps d’incubation par rapport à un film non implanté en favorisant l’adsorption grâce à des terminaisons OH en surface. Cette réduction du temps d’incubation offre une fenêtre de procédé où le film implanté se grave avec une sélectivité infinie par rapport au film non implanté. Ce résultat est extrêmement intéressant pour le procédé de gravure d’espaceurs Si3N4 dans lequel la sélectivité des surfaces horizontales (implantées) par rapport aux surfaces verticales (non implantées) est capitale. Basé sur cette compréhension, nous avons développé un procédé cyclant une étape d’implantation suivie d’une étape de retrait par plasma délocalisé dont le temps a été ajusté pour être dans la fenêtre de procédé. Les résultats sont prometteurs puisque qu’il est possible d’atteindre une très bonne sélectivité par rapport au flanc des espaceurs non implantés et du substrat en silicium sous-jacent.
... The former approach consists of kerfless wafering of Si ingots or wafers, while the latter one includes c-Si growth either from liquid or gas phases. For the "top-down" approach, methods can be found such as direct film transfer by H + ion implantation near wafer surface [10] and epifree process with H 2 annealing at 1100 • C of Si trenches fabricated by reactive ion etching [11]. In the "bottom-up" approach, when the melt-assisted epitaxial growth is concerned, there are wafer equivalent techniques such as string ribbon growth [12]. ...
The homoepitaxy of Si is particularly interesting for the purpose of kerfless wafer production, for example in the photovoltaic domain. Substrate surface engineering is a key step prior to epitaxial growth, which will affect the quality of the epitaxial layer and its detachment for layer transfer. In this work, we propose two plasma-based surface engineering methods including the deposition of a bilayer homoepitaxial interface and a SiGe heteroepitaxial interface. Their impact on the crystalline quality of epitaxial Si layers grown both by plasma-enhanced chemical vapor deposition (PECVD) at 200 °C and by atmospheric pressure chemical vapor deposition (APCVD) at 1130 °C are explored. Stacking faults are observed in epitaxial Si layers with an ultra-thin epitaxial Si interface layer. For surface engineering method based on the addition of an interfacial heteroepitaxial SiGe layer, a higher interfacial hydrogen content and a better bulk epitaxial Si quality are observed in comparison with interfacial homoepitaxial Si layer.
... Next, the implanted bulk LN is bonded to the patterned, planarized SOI. After bonding, the sample is annealed to strengthen the bond as well as to 'slice' off the majority of the bulk LN, leaving a thin film whose thickness is determined approximately by the ion implant depth [67,68]. The exposed, sliced LN film is then planarized to reduce slicing-induced roughness or crystalline damage. ...
The past decade has seen significant growth in the field of thin film lithium niobate electro-optic modulators, which promise reduced voltage requirements and higher modulation bandwidths on a potentially integrated platform. This article discusses the state-of-the-art in thin film modulator technology and presents a simplified simulation technique for quickly optimizing a hybrid silicon- or silicon nitride-lithium niobate modulator. Also discussed are the feasibility of creating a 1 V half-wave voltage, 100 GHz bandwidth modulator, and the design specifications for a single hybrid silicon-lithium niobate platform optimized to operate across all telecommunication bands (between 1260 and 1675 nm wavelengths).
... This technology has received an enormous amount of attention due to its potential to prevent short channel effects and leakage current via the substrate. The process of reference for the fabrication of SOI substrates is the SmartCut TM technology (Bruel et al. 1997) developed by CEA-Leti and commercialized by SOITEC ( Figure I.17): The donor Si wafer is oxidized, followed by an ionic implantation of hydrogen at a controlled depth. ...
Nano-heteroepitaxy is a promising approach for the growth of high quality, thin and fully strain relaxed SiGe layers (for strained Si devices). First theorized by Luryi and Suhir, the idea is to start the growth from sufficiently small nano-pillars so that the layer can relax faster, elastically, and then coalesce without generating additional defects. In this PhD, an integration scheme based on diblock copolymer patterning was used to fabricate nanometer-sized templates, on which SiGe nano-heteroepitaxy was explored using a 300 mm industrial Reduced Pressure-Chemical Vapor Deposition tool. Si0.75Ge0.25 nano-heteroepitaxy on Si and Si0.75Ge0.25 nano-pillars was first studied. Results showed highly selective and uniform processes based on a chlorinated chemistry for the epitaxial growth of 20 nm high Si and Si0.75Ge0.25 nano-pillars. Smooth surfaces and full strain relaxation were obtained in the 650-700°C range for 200 nm thick Si0.75Ge0.25 layers grown both types of nano-pillars. However, planar defects (twins and stacking faults) were identified as occurring during the coalescence process. Therefore, Si0.75Ge0.25 nano-pillars coalescence was investigated. The evolution in terms of grain shape, size and number was examined, with individual pillars merging into larger grains for thicknesses above 30 nm. High degrees of macroscopic strain relaxation were obtained at the different stages of nano-pillars merging. Defects such as stacking faults and twins appeared at the early stages of nano-pillars coalescence. The impact of the nano-template used for the nano-heteroepitaxy of Si0.75Ge0.25 layers was also evaluated. Various integration schemes were designed in order to measure the impact of pitch, the presence (or not) of the nano-template during coalescence and the nature of the masking material itself. Results showed more flexibility in terms of surface preparation with higher pitch size nano-templates. Removal of the nano-template did not improve the relaxation of coalesced layers. Changing the nature of masking material in the nano-template (SiO2 versus strain free SiN) proved that the thermal stress generated during growth was not a source of defects. The nano-heteroepitaxy approach was extended to pure Ge. Results showed a highly selective and uniform process for the epitaxial growth of Ge nano-pillars at 600°C. A degraded surface morphology, with otherwise similar structural properties, were obtained for 2D Ge layers grown on Ge nano-pillars compared with growth on bulk Si. Usual coalescence related defects were once again found.
... The sample structure is schematically shown in Fig. 2. Silicon-on-insulator (SOI), prepared by smart cut, 39 is used as a substrate for the growth of the passivation layer. The SOI is borondoped p-type, 150-300 Ω cm À1 , 300 + 3 nm-thick c-Si, polished with surface oriented h100i. ...
Surface passivation of crystalline silicon (c-Si) is experimentally studied during the growth of a hydrogenated amorphous silicon (a-Si:H) and epitaxial silicon (epi-Si) passivation layer at a subnanometer to nanometer scale. The property of surface passivation is monitored in real time via in situ measurement of a photocurrent in c-Si under plasma-enhanced vapor deposition for the passivation layer growth. The measurement results suggest the following. Passivation is improved by the growth of an a-Si:H layer, where a large band offset is formed at the a-Si:H/c-Si interface, and the carrier recombination is suppressed. On the other hand, passivation is deteriorated with the growth of an ultrathin epi-Si layer ( d ≲ 2.5 ± 1.0 nm) because the band offset is not formed at the interface, and plasma-induced defects are created in c-Si. However, passivation is improved with a thick epi-Si layer ( d ≳ 2.5 ± 1.0 nm), where the band bending is formed near the epi-Si/c-Si interface, which partially suppresses the carrier recombination. The suppression of the plasma-induced defects as well as the formation of the band offset are important for surface passivation.
... The usual process consists of 3 main technological steps the hydrogen implantation inside a donor wafer, a bonding to a receiving wafer and a fracture treatment that enables the material splitting parallel to the donor surface (see Fig. 1). So far, this method has been successfully developed to transfer a large number of materials such as Si [2], Ge [3], SiGe [4], SiC [5], GaN [6], and is here being considered to transfer semiconducting diamond wafers. A successful application of this procedure is possible by controlling the ion implantation depth as well as the sharpness of the implanted/not implanted transition. ...
An alternative route for the development of diamond-based technologies is the Smart-Cut process. Such a process could make possible the combination of diamond and silicon technologies, as well as building alternative structures or manufacturing large diamond wafers. However, crystalline quality and implantation-related damages may alter the electronic properties of the diamond wafer. In fact, this is a critical bottleneck that needs to be analysed in order to develop a reliable diamond/Smart-Cut based technology. In this contribution, we present STEM-based experiments used to evaluate various key parameters such as the sharpness of the transition regions, the behaviour of the implanted region and diamond lattice performance in Smart-Cut processes. Indeed, an outstanding sp²/sp³ relation close to ideality (it is, that of undamaged diamond) is evidenced in the diamond-transfer region.
In this work, the effect of Ge sample bombardment by energy E i = 1.2 MeV mono‐energetic He ⁺ ions within the fluence range of 10 ¹³ –1.2 × 10 ¹⁵ cm ⁻² on the microwave reflection/transmission modification in the frequency range of 26–38 GHz is investigated. It is shown for the first time that such Ge treatment allows achieving a drastic increase in its interaction with microwaves. After the 1 µm thick undersurface area of Ge, accounting for less than 10 ⁻³ of its bulk, underwent the fluence of 1.2 × 10 ¹⁵ cm ⁻² , the increase of the microwave absorption coefficient from 0.06 to 0.78 and decrease of the microwave reflection coefficient from 0.7 to 0.18 are observed. This is caused by the occurrence of dangling atomic bonds in nanoscale cavities inside the material. Most probable energy loss mechanisms of microwaves in modified Ge are suggested. Modified semiconductor structures can be used as microwave‐absorbing coverings, devices employing a periodic structure of materials or a gradient of its properties.
With the development of photonic integration technology, meta-waveguides have become a new research hotspot. They have broken through the theoretical diffraction limit by virtue of the strong electromagnetic manipulation ability of the metasurface and the strong electromagnetic field limitation and guidance ability of the waveguide. However, the reported meta-waveguides lack research on dynamic modulation. Therefore, we analyze the modulation effect of the metasurface on the optical field in the waveguide and design an ultra-compact on-chip meta-waveguide phase modulator using split ring magnetic resonance. It has a very short modulation length of only 3.65 µm, wide modulation bandwidth of 116.8 GHz, and low energy consumption of 263.49 fJ/bit. By optimizing the structure, the energy consumption can be further reduced to 90.69 fJ/bit. Meta-waveguides provide a promising method for the design of integrated photonic devices.
Polyoxometalates (POMs) are metal-oxo clusters formed by early transition metals in their highest oxidation state. More particularly, they exhibit adjustable redox properties, i.e. they can be reduced successively and reversibly to one or several electrons, such that they find their applications as redox mediators or electron reservoirs for electrocatalysis, solar energy conversion, molecular batteries or information storage. Previous results of POMs deposition onto surface characterized by electrical transport measurements were encouraging to envision the integration of active layers of POMs into nanodevices for molecular electronics. The electrical properties of the resulting device will depend on the assembly quality. The mastering of POMs immobilization onto substrates and the control of the POM/substrate interface is still required. In this context, NH2/NH3+-terminated organic monolayers grafted on oxide-free silicon substrates were prepared by hydrosilylation and post-modifications. After the electrostatic deposition of photoreducible (nBu4N)3[PMo12O40] POMs, the photoreduction of the immobilized POMs was studied by means of several characterization tools (XPS, UV-Vis-NIR spectroscopy, KPFM). Preliminary electrical characterization of a POM-based pseudo MOSFET prototype device was carried out to study the influence of the POM redox state on the device conductance and to study the possible photoswitching property. Concurrently, the covalent grafting of POM hybrids onto functionalized, hydrogenated or oxidized Si surfaces was explored during the project, with the prospects of a more stable, controlled and tunable POM/substrate interaction.
On the one hand, Graded Photonic Crystals (GPC) allow to efficiently control the flow of light thanks to the shape of their photonic bands, which we verified by demonstrating a “photonic mirage” at wavelength scale. On the other hand, GRaded INdex (GRIN) optics is undergoing a renewal because it allows downsizing optical systems, opening a new way to optical design. But GRIN optics was limited by a lack of easy to implement fabrication techniques. Nanotechnology enables to efficiently fabricate photonic crystals, which we will implement to fabricate GPC for GRIN optics. The main purpose of this Ph.D. topic is to explore graded photonic crystals and related gradient index optics in the near-infrared domain for applications on Silicon On Insulator (SOI) platforms. Gradient photonic crystals in the microwave band have been investigated by previous Ph.D. students in our group. This work then attempts to extend the application to the near-infrared field. According to the theory of subwavelength electromagnetism, the size of the device should be of the same order of magnitude as the operating wavelength. Thus, unlike the previous microwave field, a big challenge in the NIR field is the fabrication and characterization of the corresponding devices. A significant part of this work is focused on the fabrication and characterization process of gradient photonic crystals in the NIR field. We focus on nano-fabrication technology as well as SNOM characterization. SOI was chosen as the processing platform for this work, considering the good compatibility of the silicon-based platform with photonic devices and its ability to integrate well with nanofabrication techniques. In addition, another emphasized aspect of this work is to explore the effect of the variation of the photonic crystal parameters on its effective refractive index. Thus, the case of normalized frequencies in different photonic crystal energy bands is also a direction of the investigation. We attempt to manipulate the effective refractive index (even negative refractive index) of photonic crystals by changing their parameters. Experimental demonstration of negative refractive index gradient photonic crystal lens and related gradient photonic crystal devices will be highlighted. In summary, we have designed, fabricated and characterized gradient photonic crystal lens in the near-infrared domain.
Crystalline Si (c-Si) thin films have been widely studied for their application to solar cells and flexible electronics. However, their application at large scale is limited by their fabrication process. As reviewed in this paper, many approaches have been studied but only some of them have been made into large scale industrial production. The standard wire sawing of Si ingots cannot be scaled down to produce thin c-Si wafers and films due to the brittle nature of c-Si material, the resulting significant thickness variations, and the waste of material. Therefore, techniques based on the kerf-less processes including “top-down” and “bottom-up” approaches have been developed in recent decades. In this review, photovoltaic applications of thin c-Si wafers with thicknesses ranging from 50 µm down to 1 µm are presented first. Then, methods to fabricate c-Si thin films based on both approaches are detailed, including slim-cut, “smart-cut”, epi-free, as well as various growth processes such as molecular beam epitaxy, liquid phase epitaxy, ion beam, and chemical vapor deposition processes at a wide range of growth temperatures, from 1000 °C down to 150 °C. The advantages and disadvantages of these methods are presented and compared.
A beneficial effect of argon (Ar) ion bombardment for crystalline silicon (c-Si) surface passivation has been studied. Experiments of an Ar plasma treatment over an hydrogenated amorphous silicon (a-Si:H) layer grown on c-Si are performed, where an a-Si:H layer is prepared at different levels of defect density. Interestingly, the c-Si surface passivation is improved by an Ar plasma treatment for a defect-rich, i.e. low-quality, a-Si:H layer, while it is deteriorated by the treatment for a low-defect, i.e. high-quality, a-Si:H layer. The improvement of passivation is discussed in terms of microstructural changes of a-Si:H, associated with redistribution of hydrogen, where mobile hydrogens play an important role.
This paper presents a Vertical Line-Tunneling FET (VLTFET) optimized for superior performance in analog applications. The saturation mechanism, DC, and small-signal behaviors are physically explained with the help of energy band diagrams, electron density, and tunneling width parameters. VLTFET has higher output resistance ro owing to the independence of the drain bias on the band-to-band (BtB) generation. Increasing the source-gate overlap length Lov from 0.1 μ m to 0.5 μ m triples the transconductance gm, maintaining ro constant, resulting in thrice the intrinsic gain Avo. In analog circuits using conventional MOSFETs, gm increases and ro decreases with increasing width W. On the other hand, in analog circuits using VLTFETs, Avo can be enhanced by increasing Lov which increases gm without affecting ro. Unity-gain BW fT (or the GBW product) is dominated by the relative change in the overall gate capacitance CGG and gm due to change in Lov, since both gm and CGG are proportional to Lov. However, in analog circuits with realistic capacitive loads, fT rapidly increases with Lov. VLTFET-based cascode CS amplifiers provide a 10 dB increment in its gain as Lov is increased from 30 nm to 100 nm. Similarly, a VLTFET-based cascode current mirror shows a theoretical output resistance Rout in the order of 10¹¹Ω, behaving as an ideal current mirror/source.
Silicon is the most widely used material in microelectronic devices; integration of atomic impurities in silicon via doping during growth or ion implant is now widely used as it allows to form conventional transistors. Exploiting all the knowledge accumulated over the last 60 years in the context of the second quantum revolution that is now underway would help accelerate the commercialization of quantum technologies. Several works have already reported that silicon can be an optically active material with point-like defects emitting below the Si bandgap, both in ensemble emission and absorption in natural Si as well as in isotopically purified [Formula: see text]Si, even under electrical pumping. Very recently, the detection of individual impurities in silicon opened the door for further exploitation of this indirect bandgap material to applications in quantum technologies, including single photon emission at near-infrared frequency, matching the telecommunication band and optical detection of individual spins. Here, we describe the current state-of-the-art and discuss the forthcoming challenges and goals toward a reliable exploitation of these solid-state quantum-emitters in the context of quantum technologies. In particular, we examine opportunities, issues, and challenges in controlling defect formation and localization, extrinsic effects, and integration of optical devices.
The effect of H⁺ implantation and annealing of diamond (100) monocrystalline substrates has been studied by ToF-SIMS, cathodoluminescence, transmission spectroscopy and TEM. Blistering conditions suitable for the Smart Cut™ technology have been identified in monocrystalline diamond, using two sets of hydrogen implantation and annealing. A first hydrogen implantation followed by a first annealing leads to amorphization of a buried layer without hydrogen exodiffusion. Blisters and exfoliations appear at the surface of the diamond samples, after a second hydrogen implantation inside the pre-amorphized diamond layer and a final annealing, as evidenced by TEM and optical microscopy. Demonstration of hydrogen-induced blistering is a major step to adapt the Smart Cut™ process on diamond material. This process is compatible with wafer bonding before the second annealing and therefore open the way for thin diamond layer transfer on a bonded receiver wafer, still not achieved to date.
Quantum dot (QD) laser as a light source for silicon optical integration has attracted great research attention because of the strategic vision of optical interconnection. In this paper, the communication band InAs QD ridge waveguide lasers were fabricated on GaAs-on-insulator (GaAsOI) substrate by combining ion-slicing technique and molecular beam epitaxy (MBE) growth. On the foundation of optimizing surface treatment processes, the InAs/In0.13Ga0.87As/GaAs dot-in-well (DWELL) lasers monolithically grown on a GaAsOI substrate were realized under pulsed operation at 20 °C. The static device measurements reveal comparable performance in terms of threshold current density, slope efficiency and output power between the QD lasers on GaAsOI and GaAs substrates. This work shows great potential to fabricate highly integrated light source on Si for photonic integrated circuits.
Solar cells based on thin crystalline silicon (c-Si) substrates have the potential to provide relevant efficiencies with less material. In this article, we report on the fabrication of thin solar cells starting from a 20
μ
m-thick c-Si wafer. Special attention is paid to optical performance of the rear surface where we need very high internal reflection and light scattering to improve light trapping properties of the device. In this sense, we introduce a texturization of the rear surface, which is excellently passivated by aluminium oxide films. In addition, for the rear contacts we use metal-covered wide-bandgap materials to improve back reflectance with a Vanadium Oxide/c-Si heterojunction for the emitter regions while the base contacts are defined by laser processing phosphorus doped amorphous silicon carbide films. Best solar cell has a reasonable efficiency of 8.7% and, more importantly, external quantum efficiency measurements demonstrate a better performance for photons with
λ
> 900 nm than in the case of a flat rear surface.
Flexible electronics is one of the most emerging fields of future electronic devices. The application of flexible inorganic membrane provides a feasible way to realize high-performance electronic device with desired deformation ability. In this paper, a method to fabricate large-scale flexible monocrystalline silicon membrane by crystal-ion-slicing (CIS) technique using benzocyclobutene (BCB) bonding layer is reported. With introduction of BCB bonding layer, a 1-μm-thick Si membrane with the size of 8 × 8 mm can be obtained on the polyimide substrate using the conventional CIS technique. Morphology and structure characterizations confirm the high crystallinity and structural integrity of the as-fabricated silicon membrane. Typical piezoresistive effect can be observed in the measured dependence of the resistance of Si membrane on the bending strain, indicating the potential to using this method to construct flexible force sensor with high stability and sensitivity.
Wafer direct bonding was first developed in order to fabricate silicon‐on‐insulator (SOI) wafers. Smart Cut process is suitable for thinner SOI wafers. Hydrophilic wafer bonding is a method to bond wafers using hydrogen bonds between – OH groups on hydrophilic surface of wafers. This method is often called as “wafer direct bonding” or “wafer fusion bonding.” In the method, the wafers to be bonded are cleaned by chemical solutions such as NH3/H2O2 and H2SO4/H2O2 mixture. The surface roughness of the wafers is important to achieve the bonding. The surface activated bonding (SAB) is originally based on a simple idea that atoms on two clean surfaces can make strong interatomic bonds even at room temperature when they are mated. SAB originally uses cleaning of material surfaces in vacuum by sputter etching using high‐energy ion/atom beam of inert gases. The concept of SAB has been expanded in order to bond wide range of materials.
This paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device optimized for superior analog performance. DGLTFET has thrice the on currents Ion, at least one order lower off currents I o f f, twice the transconductance gm, at least two orders higher output resistance ro, and at least two orders higher overall intrinsic gain gmro than the equivalent metal‐oxide‐semiconductor field‐effect transistor (MOSFET) having the same width at the same technology node. The proposed device, being a double‐gate (DG) structure, exhibits extremely high vertical fields which ensures that line‐tunneling dominates over the point‐tunneling by several orders. This eliminates the notorious “hump” or the “kink” effects observed in conventional LTFET characteristics, which are detrimental for analog applications. In this work, we have optimized the DGLTFET device by changing critical parameters like the epi‐layer thickness and its doping concentration, which have serious influence on the line‐tunneling behavior. Optimization of the critical parameters for enhanced line‐tunneling leads to improved analog performance parameters like gm and ro, and finally, superior analog circuits. The performance of the DGLTFET was benchmarked with the equivalent MOSFET in fundamental analog VLSI circuits, namely, CS amplifier (both resistive and cascode loads), current mirror (both single‐stage and cascode configurations), and a two‐stage op‐amp. This paper shows that the DGLTFET CS amplifier has a gain‐BW product or unity‐gain BW fT of 15 GHz, while that of MOSFET CS amplifier with the same bias current is 10 GHz. The DGLTFET current mirror has at least three orders of magnitude higher ro than the corresponding MOSFET current mirror. Similarly, the common‐mode rejection ratio (CMRR) of the DGLTFET op‐amp is 57 dB compared to the CMRR of 33.5 dB of the equivalent design in standard 45‐nm complementary metal‐oxide semiconductor (CMOS) technology. The 45‐nm library is the lowest industry‐standard technology node currently available free for academic licenses in the public domain; hence, the benchmarking for validation was carried out at 45 nm. However, the claims/investigations made in this work are also valid for lower technologies, and related results are excluded in this report keeping the manuscript length in mind. This paper presents a double‐gate line‐tunneling FET (DGLTFET) device optimized for superior analog performance. DGLTFET has thrice the on currents Ion, at least one order lower off currents Ioff, twice the transconductance gm, at least two orders higher output resistance ro, and at least two orders higher overall intrinsic gain gmro than the equivalent MOSFET having the same width at the same technology node. DGLTFET CS amplifier has a unity‐gain BW fT of 15 GHz, while that of MOSFET CS amplifier with the same bias current is 10 GHz. Similarly, the CMRR of the DGLTFET op‐amp is 57 dB compared to the CMRR of 33.5 dB of the equivalent design in standard 45‐nm CMOS technology.
We tried laser slicing of (100) MgO wafer used as a substrate for heteroepitaxial growth of single crystal diamond. The laser slicing was successful by irradiating the inside of the material with an ultrashort pulse laser and generating a {100} cleavage. However, it was clarified that the cleavage of {100} was excessively extended and deviated from the slicing surface, so that steps of 20 μm were formed on the peeled surface. In order to reduce the kerf-loss, it was necessary to control the cleavage of {100}. Therefore, we proposed a scanning method to control cleavage and its extension. As a result, we succeeded in slicing a 2-inch MgO wafer with a kerf-loss of 30 μm.
In the context of growing interest in strain engineering, we present a theoretical protocol for the reconstruction of extrinsic and intrinsic strain tensors in single-crystals attached to a template, with an arbitrary oriented coordinate system. Input data for the protocol are extrinsic deformations of lattice planes, i.e., measured with reference to a template. By combining the protocol with elasticity theory, material property modification can be elucidated. Different methods for strain measurements can take advantage of this approach. It has been applied for reconstruction of strain tensor depth distribution in off-axis LiTaO3 crystals implanted with H⁺ ions, which is the key step for piezoelectric thin film-on-insulator fabrication by the Smart Cut process. Modifications of composition, lattice parameters, and elastic constants are indicated and discussed.
This paper presents a systematic study on the performance of double gate (DG)-MOSFETs with an ultrathin embedded dielectric film (DF) at the center of the channel from the source to drain of the device. The numerical simulation results show that for k ≤ 12, the value of ION/IOFF of a 20-nm DF-DG-MOSFET increases with increasing value of DF thickness t reaching a maximum value of about 10⁷ for dielectric constant k =1, and t = 5 nm whereas, tends to decrease for k> 12. Also, the 20 nm DF-DG-MOSFET with (k = 1, t = 5 nm) shows the lowest subthreshold swing SS of 79 mV/decade and drain induced barrier lowering DIBL of 109 mV/V. However, the intrinsic delay of DF-DG-MOSFET increases with increasing t for k ≤ 12, whereas, decreases as both t and k increase for k> 12 reaching a value of 0.5ps for (k = 80, t = 5 nm) compared to 0.8ps for an identical conventional DG-MOSFET. This study, clearly, shows that the performance of DG-MOSFETs can be optimized by wise choice of t and k of an embedded DF and provides guidelines for the design of high performance and low power nanoscale logic devices.
This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher Ion : Ioff ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static+dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.
Silicon surface evolution during annealing was investigated by atomic force microscopy (AFM) in a mixture of hydrogen (H 2 ) and hydrogen chloride (HCl). The power spectrum density (PSD) calculated by experimental data was fitted to the analytical results of a continuum surface dynamics equation to determine the surface relaxation mechanism. The coexistence of two mechanisms was revealed, i.e., silicon surface diffusion and silicon desorption by chlorine adatoms, whose relative contribution depended on the HCl concentration. Thus, we proposed a unified model of silicon surface dynamics under pure H 2 and HCl atmosphere, which sufficiently clarified the PSD evolution and allowed the determination of the diffusion and desorption reaction constants. Specifically, the evolution of the desorption reaction constant with increasing HCl concentration suggested a complex desorption path.
The ion-cut technology used for the fabrication of Silicon-On-Insulator (SOI) substrates involves a thermally activated layer splitting process with the evolution of hydrogenated defect complexes into microcracks in H-implanted Si. Since the layer splitting process is highly correlated to the interaction of H atoms with defects, it is expected that the blistering kinetics arising from H implantation would vary with the crystal plane orientation of Si substrates. This study presents a thorough investigation of the influence of crystal plane orientation on the blistering kinetics and defect evolution in H-implanted Si. Three Si substrates of Si(100), Si(111), and Si(110) were implanted with H2⁺ ions at an accelerated energy of 40 keV to a fluence of 2.5 × 10¹⁶ cm⁻². After ion implantation, the blistering characteristics, defect complexes, and microstructure of the specimens were characterized by SIMS, in-situ OM observation system, Raman spectra, and XTEM. The results revealed that two limiting steps of H atom diffusion dominate the blistering process in different temperature intervals. The transformation of VH3 (or V2H6) defect complex into Si:H surface state is mainly prevailing in the low-temperature interval. The blistering characteristics of Si showed a high correlation with the crystal plane orientation of Si substrates due to the difference in planar atomic density. Si(110) having a largest planar atomic density corresponds to a highest threshold temperature and a longest onset time for blister formation, followed by Si(111) and Si(100) in turn. The correlation between blistering characteristics and substrate orientation can be attributed to the fact that H implantation leads to different densities of the H-terminated platelets in Si specimens with various planar atomic densities, thus affecting the efficiency of free H atom diffusion into platelets and the blister growth as well. A conclusive finding from this study is that substrate orientation diversifies the defect density in damage layer caused by hydrogen implantation, which could change the nucleation sites of platelets available for blister formation and eventually influence the blistering efficiency and microcrack extension.
The Smart Cut process has been applied for the first time to SiC,
in order to form silicon carbide on insulator (SiCOI) structures. These
structures have been formed on polycrystalline SiC and on silicon
substrates
Single crystals of Si are doped at room temperature with hydrogen from 2 × 1016 H/cm2 to 1.6 × 1018 H/cm2 in a range of energy from 20 keV to 1 MeV. Experiments using RBS/channeling, profilometry and cross-section TEM are reported.
Irradiation of materials with large doses of gaseous ions may cause surface damage by blistering. This problem is of particular concern in fusion reactors. A stress model and a gas pressure model have been proposed in order to explain blister formation. Recent developments concerning the validty of these models will be outlined. Important swelling in the blister cap explains the difference between the measured thickness and the projected range. Large pressure in the blister cavity and saturation of the integrated stresses have been demonstrated. It now appears that both models can be unified in order to explain blister formation. Depending on experimental conditions, blistering is more or less serious. It may be a transient or a repetitive phenomena and it may be suppressed. Different models have been proposed in order to explain these behaviours. In particular, it is clear that once the He saturation reaches the surface, the gas build-up is insufficient to form new blisters. Moreover, surface irregularities prevent blistering by favouring the formation of microcavities in non-coplanar planes.
The first wall surfaces of fusion devices will be exposed to bombardment by inert gaseous projectiles such as helium. The flux, energy, and angular distribution of the helium radiation will depend not only on the type of device but also on its design parameters. For near term tokamak devices, the first wall surface phenomena caused by helium bombardment that appear to be quite important are physical sputtering and radiation blistering. Examples of these processes for a number of first wall candidate materials are discussed. While the physical sputtering phenomenon is understood, the mechanism of blister formation is not yet fully comprehensible. The various models proposed for radiation blistering of metal during helium bombardment is critically reviewed in the light of most recent experimental results.
A silicon wafer bonding process is described in which only thermally grown oxide is present between wafer pairs. Bonding occurs after insertion into an oxidizing ambient. It is proposed the wafers are drawn into intimate contact as a result of the gaseous oxygen between them being consumed by oxidation, thus producing a partial vacuum. The proposed bonding mechanism is polymerization of silanol bonds between wafer pairs. Silicon on insulator (SOI) is produced by etching away all but a few microns of one of the bonded pair. Capacitor measurements show a 27 μs minority‐carrier lifetime and no degradation of the SOI‐insulator interface. In addition, there is negligible charge at the bonding interface making the technique attractive for three‐dimensional as well as planar SOI applications.
A new application for proton ion beams in the field of Silicon On Insulator material (SOI) technology is reported. In this technology, based on hydrophillic wafer bonding and referred to as “Smart-Cut”, heat treatment induces an in-depth micro-slicing of one of two bonded wafers previously implanted with hydrogen. The principle of this process involves the basic mechanisms associated with high fluence proton implantation in materials, such as blistering, flaking and exfoliation. The intrinsic properties of this process lead to very high crystalline quality of the SOI layers and very good thickness uniformity. After presentation of the process details and the underlying physical aspects, the main characteristics of the Smart-Cut technology and first physical and electrical characterizations are reported.
The flexibility provided by full dielectric isolation and the
quasi-ideal properties of the SOI MOSFET (sharp subthreshold slope, low
body-effect coefficient, ...) have given rise to new fields of
applications for SOI devices. Beside high-temperature and radiation hard
niche applications, SOI technology is now increasingly used for the
fabrication of low-voltage, low-power CMOS circuits, high-frequency
(microwave) devices, and power devices. Some novel SOI devices have been
recently reported as well
The feasibility of transferring patterned and multilayered thin
films, simulating part of the stacked structure of a CMOS integrated
circuit, from their original bulk silicon substrate to a final
substrate, was demonstrated using the Smart-Cut process
A silicon on insulator material technology based on wafer bonding
is described, in which a heat treatment induces an in-depth microslicing
of one of the two bonded wafers previously implanted with hydrogen. The
basic phenomena, and the first physical and electrical characterisations
are discussed briefly