Low Energy Magnetic Domain Wall Logic in Short, Narrow, Ferromagnetic Wires

Abstract

We present circuit simulation results of an implementation of universal logic that operates at low switching energy. Information is stored in the position of a single domain wall in a thin, short ferromagnetic wire. The gate is switched by current-driven domain wall motion, and information is read out using a magnetic tunnel junction. The inputs and outputs of the device are currents controlled by voltage clocks, making it compatible with CMOS. Using devices that operate at 100–1 mV, we simulate a shift register circuit and a full-adder circuit. The simulations show that the magnetic logic gates can operate at lower switching energy than CMOS electronics.

Full text

IEEE MAGNETICS LETTERS, Volume 3 (2012) 3000104
Spin Electronics
Low Energy Magnetic Domain Wall Logic in Short, Narrow, Ferromagnetic Wires
Jean Anne Currivan1,2∗, Youngman Jang2∗, Mark D. Mascaro2∗,MarcA.Baldo
2∗∗,
and Caroline A. Ross2∗∗
1Harvard University, Cambridge, MA 02138, USA
2Massachusetts Institute of Technology, Cambridge, MA 02139, USA
∗Member, IEEE
∗∗Senior Member, IEEE
Received 29 November 2011, revised 5 February 2012, accepted 15 February 2012, published 3 April 2012.
Abstract—We present circuit simulation results of an implementation of universal logic that operates at low switching
energy. Information is stored in the position of a single domain wall in a thin, short ferromagnetic wire. The gate is switched
by current-driven domain wall motion, and information is read out using a magnetic tunnel junction. The inputs and outputs
of the device are currents controlled by voltage clocks, making it compatible with CMOS. Using devices that operate at
100–1 mV, we simulate a shift register circuit and a full-adder circuit. The simulations show that the magnetic logic gates
can operate at lower switching energy than CMOS electronics.
Index Terms—Spin electronics, magneto-electronics, domain wall, magnetic logic.
I. INTRODUCTION
Reducing power dissipation is one of the most important
challenges in digital electronics. Due to subthreshold leakage,
CMOS transistors are limited to voltage supplies >0.5 V to
switch from ON to OFF [ITRS 2010]. Leakage is also an obsta-
cle to further reductions in transistor sizes. Other logic families
such as spin-based devices [Behin-Aein 2010] can operate at
lower voltages, and thus with less wasted energy, by exploiting
collective phenomena.
In this letter, we show how a magnetic device that has shown
promise in memory applications [Fukami 2009, Parkin 2008]
can successfully perform logic functions. The logic device is
based on the current-driven motion of a single domain wall
(DW) within a short ferromagnetic bar, with readout accom-
plished using tunneling magnetoresistance. Several magnetic
logic devices have been proposed previously [Allwood 2005,
Xu 2008, Imre 2006, Ney 2003], but there are challenges in
implementation in circuits and performance reliability [Bandy-
opadhyay 2009].This has spurred recent research to overcome
these challenges [Zhu 2012, Yao 2012]. The device described
here is compatible with high-density integration and traditional
electrical interconnects. The simulations show that it satisfies
the requirements for concatenability and gain and is projected
to scale to low supply voltages and switching energies.
II. SINGLE LOGIC GATE OPERATION
The three-terminal magnetic DW logic gate is shown in
Fig. 1(a) and 1(b). The ON or OFF state of the gate is determined
by the position of a single DW in a soft ferromagnetic wire,
such as Ni80Fe20 (NiFe) for the illustrated in-plane magnetic
anisotropy (IMA) material; perpendicular magnetic anisotropy
(PMA) materials can also be used. The wire length Lis greater
Corresponding author: J. A. Currivan (currivan@mit.edu).
Digital Object Identifier: 10.1109/LMAG.2012.2188621
Fig. 1. Cartoon of the device, shown for IMA.
than the width wand thickness t.WefixL=180 nm and t
=2.5 nm, varying w.Forw< 100 nm, the DW is transverse
[McMichael 1997] and the magnetization direction ˆ
Mof the wire
is confined in the (x,y) plane, allowing two possible magnetiza-
tion states for the wire region under the magnetic tunnel junc-
tion, depending on DW position. To ensure that only one DW is
present, antiferromagnetic contacts (e.g., IrMn) are placed on
both ends of the wire, creating exchange bias that pins ˆ
Mat the
ends [Wei 2007].
The gate operation includes a write cycle and a read/reset
cycle. During writing, current injected into wires at the “Input(s)”
contact is spin-polarized and translates the DW along ˆ
x,switch-
ing the gate from ON [see Fig. 1(a)] to OFF [see Fig. 1(b)]. The
DW is translated by spin torque transfer, given by a modified
Landau–Lifshitz–Gilbert equation [Beach 2008]. The magneti-
zation of the DW cants in ˆ
zwhile it moves, but oscillations in
velocity are avoided by operating well below Walker breakdown
[Schryer 1974]. For current-driven motion, the Walker break-
down transition depends on (α–β), where αis the adiabatic
damping parameter and βis the nonadiabatic parameter.
It has been observed [Hayashi 2007] that current-induced
DW motion can exhibit a threshold behavior, where the DW will
only move when the applied current exceeds a threshold value
IT.Whenβ=0, there is an intrinsic threshold, but for finite βthe
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3000104 IEEE MAGNETICS LETTERS, Volume 3 (2012)
threshold is determined by extrinsic pinning sites such as edge
roughness [Jiang 2010] or local magnetic fields. This nonlinear
behavior allows the gate to have distinct OFF and ON currents.
The state of the gate is read using an MTJ (see Fig. 1(a) and
(b)]. A synthetic antiferromagnetic stack minimizes stray fields
[Yoo 2004] that could impede DW motion. To sense the mag-
netization of the soft layer directly beneath the MTJ, a voltage
VCLK is applied to the “Clock” terminal. The output current IOUT
through the MTJ can be either high ION or low IOFF depending
on the tunnel magnetoresistance TMR =(RAP−RP)/RP, where
RPand RAP are the MTJ resistance in the parallel and antipar-
allel states, respectively. TMR values 300–600% have been
observed at room temperature [Ikeda 2008]; RPdecreases with
increasing barrier thickness d. Prior investigations into tunnel
barriers with cross sections as small as 50 ×100 nm [Sankey
2007] suggest that scaling to 10 s of nanometer dimensions is
possible. In our model, we assume TMR =300%, tunnel barrier
area ≈100 nm2,andd=0.75–0.95 nm. The higher the TMR,
the more robust the system is against variations in IT, since high
TMR creates a larger difference between ION and IOFF.
If two wires with currents IA,IBare at the Input terminal and
the Clock terminal is grounded, the device is a logical two-input
NAND: provided that the input impedance is sufficiently low, only
when IA+IB≥IT(where IA<IT,IB<IT)willthedeviceswitch
from Fig. 1(a) ON to Fig. 1(b) OFF. Thus, a single device acts as
a universal NAND gate, replacing four CMOS transistors. If IA,
IB≥IT, the device performs a NOR operation. By reversing the
magnetization of the pinned ferromagnetic layer in the MTJ, the
gate can perform AND/OR operations.
The position of the DW is nonvolatile, making memory-in-logic
possible. It is possible that thermal energy could cause random
displacement of the DW in a very smooth and homogeneous
wire after switching is complete, but this could be avoided by
providing weak pinning sites for the DW at the ends of the
wire. To perform logic only, the DW is reset prior to the gate’s
next operation. The reset is performed together with the read
step. Current from the Clock terminal flows into the MTJ but
also pushes the DW back toward the Input terminal. The MTJ
is physically offset toward the Input terminal so that the output
conductance is preserved for the maximum amount of time.
III. MODELING OF GATE BEHAVIOR
To study the device behavior in a circuit, we construct an iter-
ative model using a SPICE circuit simulator [LTSpice 2011] and
micromagnetic simulations [OOMMF 2002] with α=0.01, β=
0.05, unit cell size (2.5 nm)3, and standard materials parame-
ters for Ni80Fe20 (saturation magnetization 800 kA/m, exchange
stiffness 13 ×10−12 J/m, and magnetocrystalline anisotropy
500 J/m3). The simulation does not include edge roughness or
temperature. However, the simulations show a threshold current
density, which is attributed to the pinning of the DW near the
antiferromagnetic pads, where the spins are fixed. The equiva-
lent SPICE circuit is shown in Fig. 2(a), and allows us to model
all sneak currents between gates. We represent the soft layer
by resistances RIN and RCLK, which are calculated from the ma-
terial resistivity. The MTJ is modeled by a variable resistor RMTJ
and a capacitor CMTJ. For an MgO tunnel barrier with d=1nm
Fig. 2. (a) Model of the logic gate as a three-terminal circuit. (b) Cir-
cuit architecture of three gates connected in series, with a gate-level
diagram of the three devices.
Fig. 3. Circuit behavior of a shift register. (a) Clock voltage transients
and DW positions for each gate in series, compared to output current
IOUT3. All voltages are in millivolts. (b) Different clocking scheme.
and area A=7.5 nm ×20 nm, CMTJ ∼
=30 aF, small enough
to neglect. At every time step #t=0.05 ns, we run the micro-
magnetic simulation, output the resistance RMTJ depending on
the DW position, and use all currents as inputs into the SPICE
simulation. SPICE then yields the current and voltage at ev-
ery node, which is input back in the micromagnetic code. The
process is repeated over the timescale of interest.
To model the gate within a circuit, the tunnel magnetoresis-
tance is defined as TMR =(RAP∗− RP∗)/RP∗,whereRP∗(RAP∗)
is the effective output resistance in the ON (OFF)state:RP∗(RAP∗)
=Rp(Rap)+RCLK +RINTERCONNECT. Operation of the gate re-
quires that TMR > (ION/IOFF −1). The fanout Fof the gate is F
=VCLK/(ION RP∗).
IV. CIRCUIT ARCHITECTURE
Fig. 2(b) shows three 1-fanout NAND gates connected in se-
ries. The output of gate 3 is connected back to the input of gate
1, and the circuit acts as a shift register. Logic propagation oc-
curs in two steps. During the read/reset step of gate 2, VCLK2 is
pulsed while VCLK1 and VCLK3 are grounded. The yellow arrows
represent electron flow through the MTJ, reading gate 2 and
eventually resetting DW 2, while writing gate 3 by translating
its DW. Current also flows back into gate 1, but it has been
previously reset and is in an isolated state; thus, this current
does not affect the logic state of gate 1. VCLK2 writes the state of
gate 3 but VCLK3 reads/resets gate 3; these two voltage sources
controlling one gate provide gain.
Fig. 3(a) shows clock pulses, DW positions, and IOUT3 tran-
sients simulated for the shift register of three NAND gates in
series. Wire width is fixed at w=5 nm; although this is small,
fabrication of sub-10 nm wires has been reported [Yang 2009,

IEEE MAGNETICS LETTERS, Volume 3 (2012) 3000104
Jung 2010], and these dimensions were chosen to investigate
the scaling of the device. Each clock supplies a pulse of VCLK =
120 mV for τ0=2 ns and a wait time of τ=3 ns before the next
gate is clocked, with a ramp time of 0.1 ns, giving a switching
time of 5.2 ns (192 MHz) for each gate. The wait time τis em-
ployed to turn off the driving voltage once the DW reaches the
MTJ. The DW continues to propagate across the MTJ during
τ. The graph of DW position versus time shows that each DW
moves ∼100 nm before being reset.
Fig. 3(a) shows the current IOUT3 as it oscillates at the driving
frequency f0between high and low currents of 6.5 and 2.0 µA,
respectively, with IT=3µA. The low current pulse occasionally
exhibits a high spike, due to the DW passing the MTJ before the
conclusion of the clock pulse, but it does not appreciably affect
the next gate’s DW. The negative pulses in the current occur
when the gate is in isolation and current is flowing backward
from the next gate that is in the read/reset state. The DW move-
ment keeps up with the clocking frequency up to a breakdown
frequency f0,max ≈70 MHz. This is for gates optimized for en-
ergy consumption, not for speed. DW velocity in NiFe wires can
be up to 100 m/s [Beach 2008]; thus, the switching frequency
can in principle be 1 GHz in a 100 nm long wire, and higher
in shorter wires. A simulation was run with w=15 nm wide
wires and TMR =100%, which demonstrated the same circuit
behavior using VCLK =0.7 V.
The circuit used to generate the voltage-pulse clocks in
Fig. 3(a) could rely on RF pulse transformers to produce low
voltage, high current pulses for global distribution to multiple
gates. An even simpler scheme is shown in Fig. 3(b): a global
three-phase sinusoidal clock is used; each successive clock has
a120
◦phase shift from the previous. The clock has amplitude
80 mV and switching time 4.3 ns; f0,max ≈100 MHz.
V. FULL-ADDER SIMULATION
In Fig. 4, we model a full adder as an example of a more
complex circuit. The circuit includes gates of varying fanout,
showing power gain. To modify fanout with a constant clock
voltage VCLK =125 mV, we can decrease the thickness of the
tunnel barrier d, or increase the area of the MTJ, which reduces
Rpwhile leaving the TMR unchanged. The circuit includes two
3-fanout NANDs(Rp=3k%), one 2-fanout NAND (Rp=4k%), six
1-fanout NANDs(Rp=10 k%), and nine COPY elements, with
1.8 k%interconnects. We use w=7.5 nm, RIN +RCLK =2.6 k%
for the NAND gates. The COPY gates have w=5 nm, resulting
in smaller ITsuch that they act as single-input COPY, with RIN
+RCLK =3.9 k%.Theinputandoutputcurrenttransientsin
Fig. 4(b) successfully reproduce the full-adder truth table. This
shows that these gates can operate in computational systems,
and are especially suitable for pipelined architectures since the
clock is distributed with the power supply.
VI. SCALING AND CMOS COMPARISON
In Fig. 5(a), we compare the power-delay products (PDP) and
energy-delay products (EDP) of 5 nm linewidth magnetic logic
(Rp=10 k%)with40nmCMOS.ThePDPistheenergyrequired
to switch a single gate and is expressed in kBTat300K.Ifweas-
sume MTJ length LMTJ =15 nm and DW length is LDW,wecon-
Fig. 4. Full adder. (a) Circuit diagram with input bits A, B, and C, and
output bits S and F, S +2×F=A+B+C. The gates in each column
clock together. (b) Current transients for the input and output bits. Bits
0and1correspondtocurrentsof2and6–7µA. Negative transients
during isolation have been cropped and the output time is offset by 23.7
ns for clarity.
Fig. 5. (a) PDP versus delay, shown for IMA materials (blue), PMA
materials (red), and 40 nm CMOS (green). Dotted lines are constant
EDP. (b) Gate scaling behavior, showing the PDP (square points) and
DW length (diamond points) scale versus wire width, for IMA (blue, top)
and PMA (red, bottom).
sider a gate switched when its DW moves LDW +2×LMTJ.LDW
is defined as the full-width at half-maximum of the transition re-
gion between domains. The results are shown for IMA materials
with parameters for Ni80Fe20 described earlier (blue squares),
for PMA materials, using standard parameters for Co to simulate
Co20Fe60 B20 (red diamonds) [Fukami 2008], and for contempo-
rary 40 nm CMOS (green circles) [Cadence 2011], all for 2-input,
1-output NAND gates. The CMOS simulation is run between
1Vstandardand0.5Vnear-threshold.Itdoesnotinclude
energy dissipation in the clock, like the magnetic logic simu-
lations, and ignores interconnect resistance. The IMA magnetic
logic PDP is competitive with CMOS but with longer delays, cal-
culated for a voltage range of 0.3–0.1 V. PMA magnetic logic is
about 100 times more energy efficient but with even longer de-
lays, for the range 11–4 mV. The EDP (dotted lines) of CMOS,
however, is far superior to the simulated IMA magnetic logic
and also superior to PMA magnetic logic. While a reduction in
gate length will reduce the delay of CMOS further, leakage cur-
rents are expected to affect the PDP. Thus, we conclude that
PMA magnetic logic will perform better than IMA, and is espe-
cially attractive for energy-efficient applications where the merit
parameter is PDP not EDP.
In Fig. 5(b), we simulate the scaling behavior of magnetic
logic. We vary the width of the wire wfrom 40 to 5 nm. The
diamond points show that the length of the DW along the wire
LDW scales with wfor both IMA and PMA, but is smaller for
PMA. The DW length limits device length, since the DW has to
move LDW +2×LMTJ to switch the gate.

3000104 IEEE MAGNETICS LETTERS, Volume 3 (2012)
Fig. 5(b) also shows how the PDP (square points) scales with
w.Atw=5 nm, IMA PDP =4.8 ×104kBT (0.2 fJ) operating at
120 mV, and PMA PDP =4.8 ×102kBT(2×10−3fJ) operating
at 4 mV. The PDP increases slowly with w,andevenatw=40
nm, the PMA PDP =4×103kBT (1.7 ×10−2fJ) which is also
competitive with the 40 nm CMOS node. These are well above
60 kBT, suggesting insensitivity to thermal fluctuations.
VII. CONCLUSION
The simulations show that DW logic satisfies the require-
ments of beyond-CMOS logic: it has power gain and concaten-
ability; devices are scalable; operating voltages are ∼100 mV
for IMA and ∼1 mV for PMA; and at the gate level PMA switch-
ing energies can scale below those of contemporary CMOS. A
single device has a complete set of Boolean operations, and
can support its own circuits or be integrated with CMOS. The
clocking scheme does not require additional logic transistors
at each gate. The devices are non-volatile for memory-in-logic
applications. These results provide motivation for experimen-
tal verification of the scaling behavior, especially the effects of
edge roughness on DW motion and the behavior of nanoscale
MTJs.
ACKNOWLEDGMENT
This work was supported by the Nanoelectronics Research
Initiative INDEX Center, the Department of Energy Office of Sci-
ence Graduate Fellowship Program, the National Science Foun-
dation under contract ECCS-1101798, and the Singapore-MIT
Alliance. The authors thank T. Tong and G-Y Wei for providing
the CMOS simulation.
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