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Artificial neural networks: principles and VLSI implementation
Abstract
This paper gives an overview of the principles and hardware realizations of artificial neural networks. The first section describes the operation of neural networks, using simple examples to illustrate some of its key properties. Next the different architectures are described, including single and multiple perceptron networks, Hopfield and Kohonen nets. A brief discussion of the learning rules employed in feedforward and feedback networks follows. The final section discusses hardware implementations of neural systems with emphasis on analog VLSI. Different approaches for the realizations of neurons and synapses are described. A brief comparison between analog and digital techniques is given.
Competitive-learning neural networks may be much less familiar to the ANN community than the more straightforward multilayer feedforward networks, or the feedback or state-transfer networks. The literature on competitive learning has also been somewhat esoteric all the time. Nonetheless one should not underestimate its importance, especially since development of many neural functions is only explainable by means of competitive-learning models. On the other hand, the spatially ordered mappings such as the SOM seem to be in a central position in explaining observable physiological brain organizations.
A hybrid architecture for neural coprocessing is presented. A
fixed set of analog multipliers and capacitors (analog memory) emulates
multilayer perceptrons through digitally-controlled multiplexing.
Parallelism is partially preserved, then, without direct analog
implementation of the whole structure. Details of system VLSI
implementation are given, along with simulation results that validate
system cells design
A hybrid architecture for neural coprocessing is presented. A fixed set of analog multipliers and capacitors (analog memory) emulates multilayer perceptrons through digitally-controlled multiplexing. Thus parallelism is partially preserved without direct analog implementation of the whole structure. Details of system VLSI implementation are given, along with simulation results and performance estimation
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