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Is Side-Channel Analysis really reliable
for detecting Hardware Trojans?
Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre
161 rue Ada, 34095, Montpellier cedex 5, France
Email: {firstname.lastname}
Abstract—Hardware Trojans are malicious alterations to a cir-
cuit, inserted either during the design phase or during fabrication
process. Due to the diversity of Trojans, detecting and/or locating
them is a challenging task. Numerous approaches have been
proposed to address this problem, whether logic testing based or
side-channel analysis based techniques. In this paper, we focus
on side-channel analysis, and try to underline the fact that no
published technique until now has proven its efficiency on reliable
An IC fabrication process contains three major steps: (1)
design, (2) fabrication and (3) manufacturing test. With ever-
shrinking transistor technologies, the cost of new fabrication
facilities is becoming prohibitive. Outsourcing the fabrication
process to low-cost locations has become a major trend in IC
industry. This raises the concern about untrusted foundries in
which an attacker can manipulate the manufacturing masks
in order to tamper the design with the insertion of malicious
circuitry that triggers a malfunction, referred to as Hardware
Trojans [19]. Very recent issues arose from the possibility of
getting Trojans from untrusted IP vendors [12]. However, this
topic is not covered in this paper. Since the fabrication process
becomes untrusted, testers / IC vendors have to be able to
verify the trustworthiness of the manufactured circuit.
Numerous Trojans detection methods have been proposed
over the past years. We focus mainly in this paper on side-
channel analysis methods, which consist in searching for
degradation in performance or power characteristics modifi-
cation to detect the presence of Trojan. Whether such kind
of method is reliable or not is still an open question. These
methods have indeed a major weakness: they are not robust
with respect to process and test environment variations and
therefore cannot reliably detect very small Trojans. This paper
aims at examining all the previously proposed approaches
in terms of experimentations, in order to show that almost
all methods lack an efficient experimentation to prove their
usefulness. Moreover, we will show that a smart introduction
of the Trojan would make impossible its detection by using
any technique based on delay analysis.
This paper is organized as follows. In Section II, we briefly
recall the different sorts of Trojans and the proposed detection
methods. In Section III, we focus on prior work concerning
side-channel analysis methods. These approaches have various
advantages and disadvantages; this section highlights a number
a1 a2 s1 s2
b1 b2
Trigger Payload
Fig. 1. Trojan circuit model
of these. In Section IV, we detail experiments authors have
made to prove the usefulness of their approach and underline
by simple examples the weakness of each experiment.
A. Trojan taxonomy
Trojans can take many forms. Tehranipoor et al. were the
first to propose a Trojan taxonomy [19], [20]. The taxonomy
decomposes Trojans according to their physical, activation and
action characteristics.
The physical characteristics include the size of the Trojan,
its distribution (Trojan dispersed or not across the layout of
a circuit) and its type that can be functional or parametric.
Functional Trojans modify the functionality of the original cir-
cuit (by adding spare logic gates) for rare input combinations,
while parametric Trojans target the modification of existing
logic (e.g. weakening a transistor or thinning a wire to reduce
the lifetime of the circuit) [14].
The activation characteristics refer to the criteria that causes
the Trojan to become active. It can be always active (often in
the case of parametric Trojans), or triggered by a condition.
The action characteristics refer to the type of behavior
induced by the Trojan. It can be either the disruption of the
circuit, or a malfunction, or a denial of service.
A more concise and general Trojan architecture is presented
by Wolff et al. [21] (see Figure 1). This scheme allows
representing functional Trojans, activated by a triggering con-
dition. For most of the input values the circuit will react the
correct way, i.e. the trigger is not enabled and the payload
has no effects. On the contrary, when the triggering condition
is verified (either intentionally by an attacker who knows
the triggering condition or accidentally because the circuit
elaborated those particular values) the payload will inject an
Proceedings of DCIS 2012: xxviith conference on design of circuits and integrated systems
B. Prior work in Trojan detection
Two main categories exist concerning Trojan detection:
destructive methods, where the circuit is unpackaged and
analyzed by means of “reverse engineering” techniques, or
non-destructive methods, which rely on outside measurements
without physically tampering the design.
Destructive methods are very expensive and time
consuming, and they become even more difficult with
shrinking technologies. Although they are more reliable in
detecting Trojans, they cannot guarantee the not analyzed ICs
to be Trojan free.
Non-destructive methods are categorized as either logic
testing or side-channel analysis. As described afterwards, a
combination of both is also an option.
Concerning logic testing, the assumption is that an attacker
will try to hide the Trojan of IC’s functional behavior i.e. a
Trojan will be mostly inactive and triggered under very rare
conditions. Based on this assumption, the Trojan detection
methods aim at optimizing pattern generation techniques to
maximize the probability of inserted Trojans getting triggered
and therefore detected by logic testing [8], [21].
On the contrary, side channel analysis methods focus on
observing some physical parameters of the circuit (such as
power consumption or timing) while elaborating some input
test data. The main trend is to rely on golden ICs (i.e.
circuit that have been ensured to be Trojan-free by destructive
methods) to make comparison with the circuits under test. The
introduction of additional logic gates should become visible
because of an increase of the power consumption of the circuit
or an increase of the delay in the logic path containing the
trigger or the payload. More details will be given in the next
An idea introduced in [8] consists in using logic testing
techniques in conjunction with side-channel analysis
techniques. In fact, all techniques that help triggerring a
Trojan help also magnifying the Trojan’s impact on power
Both logic testing methods and side-channel analysis meth-
ods aim at testing manufactured circuits. Another approach,
called Design for Hardware Trust, consists in modifying the IC
design flow in order to incorporate into the ICs some features
that should improve Trojan detectability.
Chakraborty et al. presented two approaches, both consist-
ing in modifying the state transition function of a circuit [6],
[7]. The main idea of these modifications is to make the Trojan
either more detectable or functionally benign.
Salmani et al. presented another approach in [18] consisting
in inserting dummy flip-flops i.e. flip-flops that aim at removing
rare triggering conditions in circuits.
A. Dynamic power
Agrawal et al. were the first to address the Trojan issue
and proposed a side-channel analysis detection scheme based
on transient power analysis [1]. They proposed an approach
consisting in generating fingerprints of Trojan-free ICs and
using these fingerprints to check whether the profile of an IC
under authentication masks the fingerprints or not.
In [16], the authors analyze regional transient power supply
signals and propose signal calibration techniques to reduce test
environment variations.
Based on the assumption that the power analysis depends
strongly on the effectiveness of pattern to magnify Trojan
contribution to circuit power consumption, the method pre-
sented in [3] consists in applying a vector to a circuit, and
keeping intact the inputs for several clock cycles in order to
see activities converging to a specific portion of the circuit.
Furthermore, a technique is presented which gives, for each
gate of a circuit, the probability that it is connected to the
A similar approach is presented in [9], in which a region-
based vector generation method is propose that aims to induce
maximum activity in one region and minimum activity in other
Considering design for hardware trust, Salmani et al. pre-
sented in [17] a method consisting in reordering scan cells
based on their geometric position. This can significantly re-
strict switching activity into a specific region and therefore
help enhancing side-channel techniques.
B. Static power
In [2], a method is presented that uses static power to
perform gate leakage estimation.
C. Delay
Jin and Makris proposed in [11] a new fingerprint generating
method using path delay information. The basic idea is to
measure the delay of each path of the circuit and to compare
it with golden references.
In the field of design for hardware trust, Li et al. propose
in [13] a detection framework based on self-authentication of
each circuit. The idea is to put additional gates on the circuit
to be able to compare on-chip delays, in order not to rely on
a golden IC.
D. Power and delay
The only approach to our knowledge exploiting both power
and delay is presented in [15]. A gate-level characterization is
done and a detection is made of gates which have inconsistent
characteristics compared to their original specified character-
istics. Both functional and parametric Trojans are discussed.
4A Security
Researchers Side-channel golden IC Benchmarks Trojans Detection
Models Insertion measurements
Agrawal et al. [1] Dynamic
power Yes RSA Counter: 16-bit, Compara-
tors: 3 & 8-bit RTL level Gate level
Jin et Makris [11] Delay Yes DES 4-bit counter, 2-bit com-
parator Gate level Gate level
Rad et al. [16] Dynamic
power Yes ISCAS85 Comparator Gate & Lay-
out levels Layout level
Potkonjak et al. [15] Static power
& Delay Yes ISCAS85 1 inverter Gate level Gate level
Banga et Hsiao [3] Transient
power Yes ISCAS About 20 gates Gate level Gate level
Alkabani et al. [2] Static power Yes MCNC91 1 & 3 two-inputs gates Gate level Gate level
Du et al. [9] Power Yes 32-bits
small Gate level Gate level
Salmani et al. [17] Power Yes ISCAS89 Comparators: 4 to 18 in-
puts Layout level Transistor level
Li et al. [13] Delay No ISCAS89 Chain of inverters Layout level Layout level
A. Experiments in literature
In this section, focus is made on the experiments done in
literature to prove the uselessness of each method. Table I
summarizes each above-mentioned side-analysis method (first
column) with respect to several criteria. The second column
shows on which side-channel the analysis is based. The third
column tells whether a golden IC is needed or not. The fourth
column specifies the used benchmarks. The fifth and sixth
columns detail the Trojan model and the level of insertion.
The last column tells at what level measurements were made.
In our opinion, two fundamental shortcomings are common
to nearly all of these experiments:
Non realistic Trojans were used. Among others, chains of
inverters presented in [13] seem not convincing enough to
demonstrate the usefulness of the method, especially as
the delay of the described Trojan varies from 3% to 10%
of the circuit delay. Such kind of structures are chosen to
be adapted to the method and do not resemble at all what
practical Trojans would look like (Interested readers can
refer to [4], [5], [10] for realistic Trojans).
In numerous approaches, Trojan were inserted at gate
level, or even RTL level. Furthermore, timing and/or
power analysis were made at gate level. To our knowl-
edge, the only reference to post layout inserted Trojan
and measurements is in [16]. Tools such as Synopsys
PrimeTime and PrimePower give accurate calculations
and are very useful given design closure in today’s IC
market. However, simple experiments can show that they
are not accurate enough when dealing with the Trojan
issue, especially Trojan put in untrusted foundry. To be
as specific as possible, Trojan should be inserted at the
layout level and experimentations should also be made a
the layout level.
Much effort has been made to take into account environment
variations and therefore Trojans getting smaller, which is the
main weakness of these methods. However, not only the
experiments made do not reflect what a Trojan may look like,
but also, they have not been conducted fairly accurately.
B. Delay analysis
One limitation of delay analysis based techniques (often not
mentioned in the published papers) is related to the fact that
measuring such paths is very hard, especially for short paths.
For instance, if the trigger is inserted between two flip flops,
its delay would be of few ps. This delay is not measurable
by using modern tools. Moreover, as we show afterwards, a
smart introduction of the Trojans would make ineffective any
detection method based on the delay measurement.
Referring back to the mechanism of trigger and payload
presented in Figure 1, one can conclude that a Trojan will
have very little impact from a delay point of view. Indeed,
regardless of the size and delay of the Trojan, the original
paths (a1>a2,b1>b2and s1>s2in the figure) are
almost unchanged:
Trigger: the only difference in trigger paths relies in the
connection of the Trojan logic. This has a delay impact
since this connection adds a capacitance to the total
capacitance of the path the Trojan is taping the signal
from. However, besides adding the logic gates belonging
Proceedings of DCIS 2012: xxviith conference on design of circuits and integrated systems
Payload Payload
Fig. 2. Different kinds of payloads
b t
(a) Xor Trojan
b t
(b) Corresponding enhanced Xnor Trojan
Fig. 3. Example: Xor and corresponding Xnor Trojan
to the Trojans, it is reasonable to think that an attacker is
also able to increase the drive strength of the door prior to
the connection of the Trojan. This can balance the slight
increase in delay.
Payload: the only difference in the payload path typically
relies in the adjunction of one gate (e.g. a XOR gate
such as seen in literature) to deliver the payload under
certain conditions. The path will therefore be affected by
a minor delay (e.g. in a 65nm process, the intrinsic delay
of a XOR gate is about a hundred ps). Furthermore,
this payload mechanism is simplistic, and an attacker
will be able to conceive more elaborate mechanisms
to activate the payload, such as depicted in Figure
2. In this figure, for each of the 3 examples, we
have shown a corresponding enhanced version. Such
kinds of mechanisms could generate a delay up to ten
times smaller than the adjunction of a XOR gate (e.g.
transforming a NAND2 gate into a NAND3 gate leads
to a increase of 5ps in the 65nm process).
A simple example consisting of two chains of inverters and
an XOR gate as Trojan is presented in Figure 3.a.
Table II depicts the delay overheads for both paths according
to several variants of the Trojan (a>sis the trigger path
and b>tis the payload path). Xor refers to the Trojan of
Figure 3.a, And and Or to the same type of Trojan, but with
an And and an Or gate. Xnor,Nand and Nor correspond to
the enhanced versions with (1) an inverter with a bigger drive
strength to limit the impact of the trigger, (2) a modification
of the inverter at payload into a Xnor,aNand or a Nor gate
Delay Xor Xnor And Nand Or Nor
Trigger +5% 0% +5% 0% +5% 0%
Payload +35% +20% +20% 0% +25% +5%
to limit the impact of the payload (cf. Xnor version in Figure
As expected, changing the power drive strength of the
inverter totally masks the impact of the Trojan on the path to
which the trigger is connected. Concerning the payload, one
can easily point out the variety of results, with an example
(the Nand gate) for which the payload has been successfully
While side-channel analysis has been reported as an effec-
tive approach to detect Trojans, it seems that most approaches
in literature lack at presenting satisfactory experimental results
to prove the usefulness of the detection method.
Side-channel analyses are sensitive to environment vari-
ations, especially with increasing process variations in
nanoscale technologies. Therefore, much effort has been made
to address problems related to variability. However, too little
effort has been made to assess the veracity of the simulation
Besides, delay based techniques do not seem realistic.
Not only measuring numerous paths on a chip is very hard,
especially for short paths, but also, simulation results show
that an attacker can easily reduce the Trojan impact on delay
to almost zero. Simple examples proposed in this paper have
highlighted this issue.
In future work, larger examples will be studied. We plan
to propose a realistic Trojan on a cryptographic circuit. To
further investigate the simulation imprecisions issues, we will
insert the Trojan at RTL level, gate level and layout level and
analyse side-channels at gate-level and layout-level. We will
also try to hide the Trojan from a delay point of view by
applying simple mechanisms presented in this paper.
As regards design for hardware trust, it seems like a promis-
ing approach that needs to be developed. It indeed allows to
create testable circuits i.e. circuits that contain ways to detect
Trojan without the use of Goden ICs, such as presented in
[13]. It allows also to create circuits that harden the insertion
of a Trojan.
Furthermore, the effectiveness of side-channel-based tech-
niques can be improved by adopting such techniques, which
can add circuitry to support the measurement and analysis
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Proceedings of DCIS 2012: xxviith conference on design of circuits and integrated systems
... b) Side-channel Analysis: The detection techniques based on analysis of side-channel measurements are premised on the assumption that HTs distort the parametric profile of the IC. This includes measuring the variations in the observable physical parameters, such as power, delay and temperature to detect any alteration in the IC [9]. Of these, the most commonly used techniques for HT detection are based on power analysis at the post-silicon stage. ...
... b) Side-channel Analysis: The detection techniques based on analysis of side-channel measurements are premised on the assumption that HTs distort the parametric profile of the IC. This includes measuring the variations in the observable physical parameters, such as power, delay and temperature to detect any alteration in the IC [9]. Of these, the most commonly used techniques for HT detection are based on power analysis at the post-silicon stage. ...
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Conventional Hardware Trojan (HT) detection techniques are based on the validation of integrated circuits to determine changes in their functionality, and on non-invasive side-channel analysis to identify the variations in their physical parameters. In particular, almost all the proposed side-channel power-based detection techniques presume that HTs are detectable because they only add gates to the original circuit with a noticeable increase in power consumption. This paper demonstrates how undetectable HTs can be realized with zero impact on the power and area footprint of the original circuit. Towards this, we propose a novel concept of TrojanZero and a systematic methodology for designing undetectable HTs in the circuits, which conceals their existence by gate-level modifications. The crux is to salvage the cost of the HT from the original circuit without being detected using standard testing techniques. Our methodology leverages the knowledge of transition probabilities of the circuit nodes to identify and safely remove expendable gates, and embeds malicious circuitry at the appropriate locations with zero power and area overheads when compared to the original circuit. We synthesize these designs and then embed in multiple ISCAS85 benchmarks using a 65nm technology library, and perform a comprehensive power and area characterization. Our experimental results demonstrate that the proposed TrojanZero designs are undetectable by the state-of-the-art power-based detection methods.
... Logic testing techniques are based on the generation of random test patterns and employing various methods to trigger the Trojan circuits and observe their effects at the output [13,26,45]. Side channel analysis is based on measuring the variations in observable physical parameters, such as delay, power, electromagnetic signal analysis and current sensing, to detect any alteration with the structural characterization of the IC design [15]. Agarwal et al. propose an approach based on power analysis by applying random patterns at inputs of ICs under test and comparing their measurements with the power signature of a golden model [5]. ...
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The rising trend of globalization in integrated circuits (ICs) design and fabrication process has increased their vulnerability against malicious intrusions and alterations. Such modifications, also referred as Hardware Trojans (HTs), can lead to highly detrimental consequences like causing an IC to subvert normal operation, leak sensitive information or inducing denial of service (DoS). The vulnerability analysis of ICs against the malicious intrusions with conventional design-time testing and exhaustive simulations is computationally intensive, and it takes substantial resources and time for all-encompassing verification. To overcome these limitations, we propose a formal framework, based on gate-level side channel parameters, for a-priori assessment of IC vulnerability against HTs at the early stages of the design. This work employs formal modeling of the IC behavior in terms of switching power, propagation delay and leakage in order to examine the impact of malicious intrusions. We used the bounded model checker nuXmv, to formally verify and analyze the identified properties, owing to its inherent ability to handle real numbers and its support for analyzing infinite state domains. The vulnerabilities of ICs against HTs, and their effects on the IC nodes are assessed by analyzing linear temporal logic (LTL) properties, which are subsequently rendered into behavioral traces. We demonstrate the effectiveness of our approach on a set of ISCAS benchmarks.
... Logic based testing techniques uses generation of random test vectors and implementation of different methods to trigger the Trojan circuits and observe their effects at the output [9]. Side channel analysis is based on measuring the variations in observable physical parameters, such as delay, power, electromagnetic (EM) signal analysis and current sensing in order to detect any alteration with the structural characterization of the integrated circuit design [12]. Side channel analysis techniques are more commonly used because of their higher performance, relatively lower costs and nondestructive testing capabilities. ...
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In order to ensure trusted in–field operation of integrated circuits, it is important to develop efficient low–cost techniques to detect malicious tampering (also referred to as Hardware Trojan) that causes undesired change in functional behavior. Conventional post– manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes. Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side–channel approaches that monitor the impact of a Trojan circuit on power or current signature. Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns.
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Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans in an integrated circuit supply chain in recent years. Most of the recently proposed Trojan detection methods are based on Trojan activation to observe either a faulty output or measurable abnormality on side-channel signals. Time to activate a hardware Trojan circuit is a major concern from the authentication standpoint. This paper analyzes time to generate a transition in functional Trojans. Transition is modeled by geometric distribution and the number of clock cycles required to generate a transition is estimated. Furthermore, a dummy scan flip-flop insertion procedure is proposed aiming at decreasing transition generation time. The procedure increases transition probabilities of nets beyond a specific threshold. The relation between circuit topology, authentication time, and the threshold is carefully studied. The simulation results on s38417 benchmark circuit demonstrate that, with a negligible area overhead, our proposed method can significantly increase Trojan activity and reduce Trojan activation time.
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Editor's note:Today's integrated circuits are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. This article presents a classification of hardware Trojans and a survey of published techniques for Trojan detection.
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Hardware Trojans have become a growing concern in the design of secure integrated circuits. In this work, we present a set of novel hardware Trojans aimed at evading detection methods, designed as part of the CSAW Embedded System Challenge 2010. We introduced and implemented unique Trojans based on side-channel analysis that leak the secret key in the reference encryption algorithm. These side-channel-based Trojans do not impact the functionality of the design to minimize the possibility of detection. We have demonstrated the statistical analysis approach to attack such Trojans. Besides, we introduced Trojans that modify either the functional behavior or the electrical characteristics of the reference design. Novel techniques such as a Trojan draining the battery of a device do not have an immediate impact and hence avoid detection, but affect the long term reliability of the system.
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Chip design and fabrication is becoming increasingly vulnerable to malicious activities and alternations with globalization. An adversary can introduce a Trojan designed to disable and/or destroy a system at some future time (Time Bomb) or the Trojan may serve to leak confidential information covertly to the adversary. This paper proposes a taxonomy for Trojan classification and then describes a statistical approach for detecting hardware Trojans that is based on the analysis of an ICs power supply transient signals. A key component to improving the resolution of power analysis techniques to Trojans is calibrating for process and test environment (PE) variations. The main focus of this research is on the evaluation of four signal calibration techniques, each designed to reduce the adverse impact of PE variations on our statistical Trojan detection method.
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Malicious hardware Trojan circuitry inserted in safety-critical applications is a major threat to national security. In this work, we propose a novel application of a key-based obfuscation technique to achieve security against hardware Trojans. The obfuscation scheme is based on modifying the state transition function of a given circuit by expanding its reachable state space and enabling it to operate in two distinct modes -- the normal mode and the obfuscated mode. Such a modification obfuscates the rareness of the internal circuit nodes, thus making it difficult for an adversary to insert hard-to-detect Trojans. It also makes some inserted Trojans benign by making them activate only in the obfuscated mode. The combined effect leads to higher Trojan detectability and higher level of protection against such attack. Simulation results for a set of benchmark circuits show that the scheme is capable of achieving high levels of security at modest design overhead.
Conference Paper
We discuss a new approach for protecting the secrecy of internal information in an Integrated Circuit (IC) from malicious hardware Trojan threats and, thereby, enhancing hardware trust. The proposed approach is based on Register Transfer Level (RTL) code certification within a formal logic environment. The key novelty lies in the introduction of a new semantic model for the Verilog Hardware Description Language (HDL) in the Coq theorem-proving platform, which facilitates tracking and proving secrecy labels of internal sensitive data and, by extension, security properties of the design. Additional framework enhancements include the ability to encapsulate sub-module properties in the top module proof environment, thereby strengthening the ability of Coq representation to reason on hierarchically organized RTL code. We demonstrate the proposed framework on a DES encryption core, wherein we employ it to prevent secret information (e.g. round keys) leaking by hardware Trojans inserted at the RTL description of the circuit.
Conference Paper
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Conference Paper
Malicious activities and alterations to integrated circuits have raised serious concerns to government agencies and the semiconductor industry. The added functionality, known as hardware Trojan, poses major detection and isolation challenges. In this paper, we present a method to localize design switching to any specific region independent from test patterns. The new architecture allows activating any target region and keeping others quiet which reduces total circuit switching activity. This helps magnify the Trojan's contribution to the total circuit transient power by increasing Trojan-to-circuit switching activity (TCA) and power consumption. The proposed method is aimed at improving the efficiency of power-based side-channel signal analysis techniques for detecting hardware Trojans. Our simulation results demonstrate the efficiency of the method in significantly increasing TCA.